Mediator module, package structure including mediator module

Abstract

The utility model provides a kind of intermediate module, including intermediate, semiconductor die placed on intermediate and multiple wire structures connecting intermediate to semiconductor die, wherein multiple wire structures include first interconnect portion, first interconnect portion includes first alloy barrier layer;Second interconnect portion, second interconnect portion includes second alloy barrier layer;And solder joint, solder joint connects first interconnect portion to second interconnect portion.

Description

Technical Field

[0001] This utility model relates to an intermediary module and an encapsulation structure including the intermediary module. Background Technology

[0002] Metal bumps are commonly used as interconnects in advanced packages. Metal bumps (e.g., copper bumps) can include, for example, C4 (control collapse chip connection) bumps and C2 (chip connection) bumps, which are smaller than C4 bumps. C2 bumps are often referred to as "micro bumps".

[0003] Metal bumps may include metal pillars (copper pillars) having a thin nickel barrier layer (e.g., a nickel diffusion barrier layer) and a tin-silver solder capping layer. Metal bumps may be formed on the surface of a semiconductor die in a series of steps.

[0004] Specifically, the metal bumps can be formed by first depositing a bottom bump metal layer (UBM layer) on the pads. Then, a metal layer (e.g., a copper layer) is formed on the UBM layer using an electrochemical deposition (ECD) system. A nickel diffusion barrier layer can then be formed on the metal layer, and a solder cap can then be formed on the nickel diffusion barrier layer. Utility Model Content

[0005] This utility model provides an intermediary module, including an intermediary, a semiconductor die located on the intermediary, and a plurality of interconnect structures connecting the intermediary and the semiconductor die. The plurality of interconnect structures may include a first interconnect portion having a first alloy barrier layer, a second interconnect portion having a second alloy barrier layer, and a welding joint connecting the first interconnect portion and the second interconnect portion.

[0006] This utility model provides a packaging structure including a packaging substrate and an intermediate module located on the packaging substrate, including an intermediate, a semiconductor die located on the intermediate, and a plurality of interconnect structures connecting the intermediate and the semiconductor die, and including a solder joint and a pair of alloy barrier layers located on opposite sides of the solder joint. Attached Figure Description

[0007] The best understanding of the features disclosed herein will be achieved by reading the following detailed description in conjunction with the accompanying drawings. It should be noted that, according to standard practice in the industry, the features are not drawn to scale. In fact, the dimensions of the features may be increased or decreased arbitrarily for clarity of explanation.

[0008] Figure 1A It is a vertical cross-sectional view of an intermediary module according to one or more embodiments.

[0009] Figure 1B It is a detailed vertical cross-sectional view of the spacing between interconnect structures in an intermediary module according to one or more embodiments.

[0010] Figure 1C This is a detailed vertical cross-sectional view of the interconnect structure in the intermediary module according to one or more embodiments.

[0011] Figure 2A It is a vertical cross-sectional view of an intermediate structure including a portion of an intermediary (e.g., an organic intermediary) located on a first carrier substrate (e.g., a carrier wafer) according to one or more embodiments.

[0012] Figure 2B This is a vertical cross-sectional view of an intermediate structure according to one or more embodiments, the intermediate structure including an upper passivation layer located on the side surface of the intermediate chip.

[0013] Figure 2C This is a vertical cross-sectional view of an intermediate structure according to one or more embodiments, the intermediate structure including an opening in an upper passivation layer located on the side surface of the intermediate chip.

[0014] Figure 2D This is a vertical cross-sectional view of an intermediate structure according to one or more embodiments, the intermediate structure including a first seed layer on an upper passivation layer located on the side surface of the intermediate chip.

[0015] Figure 2E It is a vertical cross-sectional view of an intermediate structure including a patterned photoresist layer on a first seed layer, according to one or more embodiments.

[0016] Figure 2F It is a vertical cross-sectional view of the intermediate structure of a first bump in an opening of a patterned photoresist layer, according to one or more embodiments.

[0017] Figure 2G This is a vertical cross-sectional view of an intermediate structure including a first bump on a first seed layer, according to one or more embodiments.

[0018] Figure 2H This is a vertical cross-sectional view of an intermediate structure including a first bump on a first seed layer, according to one or more embodiments.

[0019] Figure 2I It is a vertical cross-sectional view of an intermediate structure including a first bump after a reflow process, according to one or more embodiments.

[0020] Figure 2J According to one or more embodiments, the intermediate structure includes a vertical cross-sectional view of a semiconductor die located on an intermediary.

[0021] Figure 2K It is a vertical cross-sectional view of an intermediate structure according to one or more embodiments, the intermediate structure including a semiconductor die located on an intermediary.

[0022] Figure 2L It is a vertical cross-sectional view of an intermediate structure including a bottom filler layer of an intermediary module, according to one or more embodiments.

[0023] Figure 2M It is a vertical cross-sectional view of an intermediate structure including a layer of molded material, according to one or more embodiments.

[0024] Figure 2N It is a vertical cross-sectional view of an intermediate structure including a plurality of C4 bumps according to one or more embodiments.

[0025] Figure 3 This is a flowchart of a method for creating an intermediary module according to one or more embodiments.

[0026] Figure 4 This is a detailed vertical cross-sectional view of the interconnect structure in the interfacing module of a first alternative design according to one or more embodiments.

[0027] Figure 5 This is a detailed vertical cross-sectional view of the interconnect structure having a second alternative design in an intermediary module according to one or more embodiments.

[0028] Figure 6 This is a vertical cross-sectional view of a package structure including an intermediary module according to one or more embodiments.

[0029] Figure 7A This is a vertical cross-sectional view of an intermediate structure according to one or more embodiments, the intermediate structure including a packaging substrate having an upper packaging substrate pad and a lower packaging substrate pad.

[0030] Figure 7B It is a vertical cross-sectional view of an intermediate structure according to one or more embodiments, wherein the intermediate module in the intermediate structure can be mounted on a packaging substrate.

[0031] Figure 7C This is a vertical cross-sectional view of an intermediate structure forming a bottom filler layer on a packaging substrate, according to one or more embodiments.

[0032] Figure 7D It is a vertical cross-sectional view of an intermediate structure in which the TIM layer can be formed on (e.g., attached to) an intermediary module, according to one or more embodiments.

[0033] Figure 7E This is a vertical cross-sectional view of an intermediate structure in which an adhesive layer is applied to a packaging substrate, according to one or more embodiments.

[0034] Figure 7F This is a vertical cross-sectional view of an intermediate structure in which the package cover is attached (e.g., mounted) on a package substrate, according to one or more embodiments.

[0035] Figure 7G This is a vertical cross-sectional view of an intermediate structure in which multiple solder balls are formed on a packaging substrate, according to one or more embodiments. Detailed Implementation

[0036] The following disclosure provides numerous different embodiments or examples for implementing various features of the provided object. Specific examples of components and arrangements are described below to simplify this disclosure. Of course, these are merely examples and are not intended to be limiting. For example, the following description of a first feature formed on or on a second feature may include embodiments in which the first and second features are formed in direct contact, and may also include embodiments in which additional features may be formed between the first and second features, thereby preventing direct contact between the first and second features. Furthermore, reference numerals or letters may be repeated in various instances of this disclosure. Such repetition is for the purpose of brevity and clarity, and is not intended to indicate any relationship between the various embodiments or configurations discussed.

[0037] Furthermore, for ease of explanation, spatially relative terms such as "beneath," "below," "lower," "above," "upper," or similar expressions may be used herein to describe the relationship between one device or feature shown in the figures and another device or feature. These spatially relative terms are intended to encompass not only the orientation shown in the figures but also different orientations of the device during use or operation. The device may have other orientations (rotated 90 degrees or in other orientations), and the spatially relative descriptions used herein can be interpreted accordingly.

[0038] In intermediate modules or semiconductor packages, it may be necessary to reduce the spacing between interconnects (metal bumps, such as microbumps) (interconnect pitch). Reducing interconnect pitch can increase input / output (I / O) density, thereby helping to meet the growing demand for heterogeneous integration.

[0039] Currently, interconnect structures using nickel barrier layers may include limited solder amounts to manage collapse risk and reduce joint necking following intermetallic compound (IMC) formation. In particular, nickel barrier layers are not effective against IMC formation and sidewall wetting. Therefore, interconnect structures with nickel barrier layers may not provide good joint yield and high-temperature solder (HTS) reliability.

[0040] In particular, in intermediate modules with 12μm pitch interconnects (e.g., system-on-a-chip), the interconnects may suffer severe solder collapse after reflow processing. Solder collapse can be mitigated by limiting solder volume and performing plasma passivation on the sidewalls. Furthermore, junction necking (i.e., tensile deformation) can be observed after high-temperature storage, as the formation of Ni3Sn4 intermetallic compounds may be accompanied by solder volume shrinkage.

[0041] One or more embodiments of this disclosure provide an interconnect structure including an alloy barrier layer (barrier layer metal). In at least one embodiment, the alloy barrier layer can replace the currently used nickel barrier layer, resulting in an interconnect structure with improved reliability. The interconnect structure can have an extremely slow intermetallic compound (IMC) growth rate with tin (Sn). This can help provide solder volume design constraints without experiencing solder collapse and joint necking. In particular, the alloy barrier layer resists IMC formation and sidewall wetting, allowing the alloy barrier layer to maintain solder volume without shrinkage. The alloy barrier layer can also allow for reduced interconnect spacing (e.g., interconnect spacing of 40 μm or less, even 12 μm or less).

[0042] In at least one embodiment, the interconnect may include a solder joint and a pair of alloy barrier layers on opposite sides of the solder joint. Specifically, the interconnect may include a median-side bump portion (first interconnect portion), a die-side bump portion (second interconnect portion), and a solder joint connecting the die-side bump portion and the median-side bump portion. The median-side bump portion may include an outer median-side bump copper layer (first outer metal layer), an inner median-side bump copper layer (first inner metal layer), and an alloy barrier layer located between the outer and inner median-side bump copper layers. The die-side bump portion may include an outer die-side bump copper layer (second outer metal layer), an inner die-side bump copper layer (second inner metal layer), and an alloy barrier layer located between the outer and inner die-side bump copper layers.

[0043] The thickness of the alloy barrier layer can range from 1 μm to 5 μm. The composition of the alloy barrier layer may include (1) an iron-based binary alloy, wherein the iron content is in the range of 50 wt% to 90 wt%, or (2) a tungsten-based binary alloy, wherein the tungsten content is in the range of 40 wt% to 50 wt%. Iron-based binary alloys may include, for example, FeNi or FeCo. Tungsten-based binary alloys may include, for example, NiW or CoW. Other suitable iron-based and tungsten-based binary alloys may also be used.

[0044] After the solder joint is formed (and after reliability testing), the total thickness of the internal intermediate side bump copper layer may be less than 50% of the solder joint thickness. Furthermore, the solder joint may have a reduced amount of intermetallic compound (IMC) (e.g., not entirely IMC), thus reducing the amount of voids associated with IMC.

[0045] It should be noted that in this embodiment, the formation of the intermetallic compound (IMC) may include two parts. First, the IMC may be formed by the reaction of the solder joint with the internal die-side bump copper layer and / or the internal intermediary-side bump copper layer at the interface and sidewalls. Second, the IMC may be formed by solder wetting through the sidewalls of the internal die-side bump copper layer and / or the internal intermediary-side bump copper layer, and then reacting with the alloy barrier layer. Therefore, the alloy barrier layer can reduce the formation of IMC (even if the alloy barrier layer is not in direct contact with the solder) through the second part that resists the formation of IMC.

[0046] Solder joints in interconnect structures can help reduce sidewall wetting. Sidewall wetting can occur in two situations: First, during the melting of the solder forming the weld joint. Second, during the heat treatment process in subsequent processes and reliability testing.

[0047] The weld joints of the interconnect structure may have a larger sidewall angle compared to existing interconnect structures (e.g., approximately 12° to 15° sidewall angle compared to the 10° sidewall angle of existing interconnect structures). This allows the interconnect structure to achieve less sidewall wetting compared to existing interconnect structures.

[0048] In other interconnect designs, alloy barrier layers located on both sides of the weld joint can contact the weld joint. Specifically, in the first alternative design, the inner die-end bump copper layer and the inner intermediate end bump copper layer can be omitted. That is, the die-end bump portion may include an outer die-end bump copper layer and an alloy barrier layer located between the weld joint and the outer die-end bump copper layer. The intermediate end bump portion may include an outer intermediate end bump copper layer and an alloy barrier layer located between the weld joint and the outer intermediate end bump copper layer.

[0049] In the second alternative design, the internal die-side bump copper layer and the internal intermediary-side bump copper layer can be omitted, as can the external die-side bump copper layer and the external intermediary-side bump copper layer. That is, the die-side bump portion may include an alloy barrier layer located between the solder joint and the die, and the intermediary-side bump portion may include an alloy barrier layer located between the solder joint and the intermediary.

[0050] In the first and second alternative designs, the length of solder wetting to the sidewall of the barrier layer can be less than or equal to about 10% of the thickness of the alloy barrier layer. Furthermore, in the first and second alternative designs, the total IMC thickness (e.g., the combined thickness of the second IMC layer formed above the weld joint and the first IMC layer formed below the weld joint) can be less than or equal to about 10% of the weld joint thickness.

[0051] In summary, novel alloy barrier layer metals can be used for fine-pitch interconnects (e.g., interconnect pitch of 40 micrometers or less) to improve bonding yield and high-temperature storage reliability through the extremely slow IMC growth rate with tin (Sn). The alloy metal composition can include iron-based alloys or tungsten-based alloys, and the alloy ratio can be controlled.

[0052] The design of this invention may have several advantages. First, the design allows for reduced interconnect spacing, thereby reducing solder consumption and support height (e.g., the Z-axis distance between the die and the interposer, such as the distance between the top die surface and the bottom wafer surface), and providing a wider bonding process window. Smaller interconnects can only withstand less molten solder, which is limited by surface tension. Therefore, as interconnect spacing decreases, solder consumption may need to be reduced. With reduced solder consumption, the IMC formation rate may become critical, as solder may be consumed during IMC formation.

[0053] The second advantage is that the ultra-low intermetallic compound growth rate results in less solder necking (joint volume shrinkage), allowing the design to provide a stable microstructure after reliability testing (temperature cycling testing, high-temperature storage testing). The third advantage is that due to less solder consumption, there are no waiting times for the joining processes (thermo-pressurization, vapor reflow soldering, or micro-reflow soldering). The fourth advantage is that less solder sidewall wetting results in a uniform joint shape and good joint yield.

[0054] Figure 1A This is a vertical cross-sectional view of the mediator module 120 according to one or more embodiments. Figure 1B The spacing P between the interconnects 128 in the intermediary module 120 according to one or more embodiments i Detailed vertical cross-sectional view. Figure 1C This is a detailed vertical cross-sectional view of the interconnect 128 in the intermediary module 120 according to one or more embodiments.

[0055] like Figure 1AAs shown, the intermediate module 120 may include one or more semiconductor dies 140 on the intermediate 10. Although the illustrated intermediate module 120 includes a specific number and arrangement of semiconductor dies, the number and arrangement of the semiconductor dies are not limited to any particular number and arrangement. In particular, the intermediate module 120 may include any number and arrangement of semiconductor dies.

[0056] Intermediate 10 is not necessarily limited to any particular material or configuration. Intermediate 10 may include, for example, organic materials (e.g., dielectric polymers), inorganic materials (e.g., silicon), glass substrates, etc. In at least one embodiment, intermediate 10 may include a plurality of dielectric layers 12 and a plurality of redistribution layers 12a stacked alternately. The number of dielectric layers 12 and / or redistribution layers 12a in intermediate 10 is not limited by this disclosure. In at least one embodiment, dielectric layer 12 may include, for example, polyimide (PI), epoxy resin, acrylic resin, phenolic resin, benzocyclobutene (BCB), polybenzoxazole (PBO), or any other suitable polymer-based dielectric material. The thickness of dielectric layer 12 may range from 4 μm to 60 μm. Other thicknesses of dielectric layer 12 are within the scope of this disclosure.

[0057] The redistribution layer 12a may include a conductive material. The conductive material may include, for example, one or more layers, and may include metals, metal alloys, and / or other metal-containing compounds (e.g., Cu, Al, Ni, Mo, Co, Ru, Ti, Ta, W, TiN, TaN, WN, etc.). Other suitable metallic materials are within the scope of this disclosure.

[0058] The redistribution layer 12a may include a metallic interconnect structure, such as a metallic structure providing electrical connections between nodes in the structure. The redistribution layer 12a may include a metal seed layer (not shown) and a metallic filler material on the metal seed layer. The metal seed layer may include, for example, a stack of titanium barrier layers and copper seed layers. The titanium barrier layer may have a thickness ranging from 50 nm to 500 nm, and the copper seed layer may have a thickness ranging from 50 nm to 500 nm, although smaller or larger thicknesses may also be used. The metallic filler material of the redistribution layer 12a may include copper, nickel, or copper and nickel. Other suitable metallic filler materials are within the scope of this disclosure. The thickness of the metallic filler material deposited for each redistribution layer 12a may range from 2 μm to 40 μm, for example from 4 μm to 10 μm, although smaller or larger thicknesses may also be used.

[0059] In at least one embodiment, the redistribution layer 12a may include a plurality of metal traces 12a1 and a plurality of metal vias 12a2, the plurality of metal vias 12a2 connecting the plurality of metal traces 12a1 to each other. The metal traces 12a1 may be located on the dielectric layer 12 and may extend to the upper surface of the dielectric layer 12 in the x direction (first horizontal direction) and y direction (second horizontal direction).

[0060] One or more interposer pads 16 may be formed on the chip-side surface 10s1 of the interposer 10. The interposer pads 16 may be formed of, for example, metals, metal alloys, and / or other metal-containing compounds (e.g., Cu, Al, Ni, Mo, Co, Ru, Ti, Ta, W, TiN, TaN, WN, etc.). Other suitable materials may be used for the interposer pads 16.

[0061] The upper passivation layer 13 may also be formed on the chip-side surface 10s1 of the dielectric 10. The upper passivation layer 13 may cover the outer portion of the dielectric pad 16. The upper passivation layer 13 may include silicon dioxide, silicon nitride, a low dielectric constant dielectric material such as carbon-doped oxide, an extremely low dielectric constant dielectric material such as porous carbon-doped silicon dioxide, a combination thereof, or other suitable materials.

[0062] A first seed layer 17 may be formed on the upper passivation layer 13. The first seed layer 17 may include a lower portion that contacts the upper surface of the intermediate pad 16 via an opening in the upper passivation layer 16. The first seed layer 17 may also include an upper portion located on the upper surface of the upper passivation layer 13. The first seed layer 17 may be used as a substrate in subsequent electroplating processes. The first seed layer 17 may include one or more layers and one or more metals, such as copper, titanium, etc. In at least one embodiment, the first seed layer 17 may include a copper layer and a titanium layer. Other suitable metals may be used in the first seed layer 17.

[0063] The semiconductor die 140 can be connected to the intermediate 10 via one or more interconnects 128. In at least one embodiment, each of the interconnects 128 may include a first interconnect portion 128a, which includes a first alloy barrier layer, and a second interconnect portion 128b, which includes a second alloy barrier layer. The interconnects 128 may also include a solder joint 128c connecting the first interconnect portion 128a and the second interconnect portion 128b.

[0064] The first interconnect portion 128a can be attached to the chip-side surface 10s1 of the intermediate 10. Specifically, the first interconnect portion 128a can be formed on the first seed layer 17 on the upper surface of the contact intermediate pad 16. The outer wall of the first interconnect portion 128a can be substantially aligned with the outer wall of the first seed layer 17. The first interconnect portion 128a can be electrically coupled to the redistribution layer 12a through the first seed layer 17 and the intermediate pad 16.

[0065] One or more die pads 146 may be formed on the front side 140f of the semiconductor die 140. The die pads 146 may be substantially the same as the dielectric pads 16. A die passivation layer 145 may also be formed on the front side 140f of the semiconductor die 140. The die passivation layer 145 may cover the outer portion of the die pads 146. The die passivation layer 145 may be substantially the same as the upper passivation layer 13 on the dielectric 10.

[0066] A second seed layer 147 may be formed in the die passivation layer 145. The second seed layer 147 may be substantially the same as the first seed layer 17 on the intermediate pad 16. The second seed layer 147 may include a lower portion that contacts the upper surface of the die pad 146, the lower portion contacting through an opening in the die passivation layer 145. The second seed layer 147 may also include an upper portion located on the upper surface of the die passivation layer 145.

[0067] The second interconnect portion 128b can be connected to the front side 140f of the semiconductor die 140. Specifically, the second interconnect portion 128b can be formed on the second seed layer 147 contacting the upper surface of the die pad 146. The outer wall of the second interconnect portion 128b can be substantially aligned with the outer wall of the second seed layer 147. The second interconnect portion 128b can be electrically coupled to the front-end process (FEOL) region 141 of the semiconductor die 140 through the second seed layer 147 and the die pad 146.

[0068] The solder joint 128c may include a solder material comprising one or more of tin, copper, silver, bismuth, indium, zinc, and antimony. In at least one embodiment, the solder material may include a tin-silver alloy. In at least one embodiment, the solder material may include a tin-silver-copper alloy comprising about 3-4% silver, 0.5-0.7% copper, and the remainder (95% or more) tin. A fourth metal, such as zinc or manganese, may be added to the tin-silver-copper alloy. The solder material may have a melting point in the range of 90°C to 450°C, and more specifically, in the range of about 220°C to 260°C.

[0069] The lower passivation layer 14 may be formed on the plate-side surface 10s2 of the intermediate 10. The lower passivation layer 14 may also include silicon dioxide, silicon nitride, a low dielectric constant dielectric material such as carbon-doped oxide, an extremely low dielectric constant dielectric material such as porous carbon-doped silicon dioxide, a combination of the foregoing materials, or other suitable materials.

[0070] One or more intermediate under-pads (not shown) may also be located on the plate-side surface 10s2 of the intermediate 10. The intermediate under-pads may be soldered and electrically connected to the redistribution layer 12a. The intermediate under-pads may be located in the lower passivation layer 14. The lower passivation layer 14 may at least partially cover the intermediate under-pads. That is, the intermediate under-pads may at least partially expose the plate-side surface of the intermediate 10. The intermediate under-pads may also comprise, for example, one or more layers, and may include metals, metal alloys, and / or other metal-containing compounds (e.g., Cu, Al, Ni, Mo, Co, Ru, Ti, Ta, W, TiN, TaN, WN, etc.). Other suitable metallic materials are within the scope of this application.

[0071] In at least one embodiment, one or more integrated passive components (IPDs) (not shown) may be selectively located on the plate-side surface 10s2 of the interposer 10. The IPDs may be bonded and electrically connected to the redistribution layer 12a. The IPDs may be located within the lower passivation layer 14. The IPDs may include exposed portions protruding from the lower passivation layer 14. The IPDs may include one or more electronic components, such as capacitors, resistors, inductors, coils, choke coils, filters, impedance matching components, attenuators, etc. The IPDs may be electrically coupled to the semiconductor die 140 through the interposer 10.

[0072] like Figure 1A As further shown, one or more C4 bumps 121 may be connected to the board-side surface 10s2 of the interposer 10. The C4 bumps may be connected to the redistribution layer 12a in the bottom dielectric layer 12 of the interposer. The C4 bumps 121 may also be connected to the pads at the bottom of the interposer (if present).

[0073] In at least one embodiment, the C4 bump 121 may include a bottom metal layer (UBM) (not shown) located on the under-intermediate pad. The material layer sequence within the UBM layer may be selected such that solder material portions can subsequently be attached to portions of the bottom surface of the UBM layer. The UBM layer may include, but is not limited to, stacks of Cr / Cr-Cu / Cu / Au, Cr / Cr-Cu / Cu, TiW / Cr / Cu, Ti / Ni / Au, and Cr / Cu / Au. Other suitable materials are within the scope of this disclosure. The thickness of the UBM layer may range from 5 μm to 60 μm, for example from 10 μm to 30 μm, although smaller and larger thicknesses may also be used. A photoresist layer may be applied to the UBM layer and may be photolithographically patterned to form an array of discrete patterned photoresist material portions. An etching process may be performed to remove unmasked portions of the UBM layer. The etching process may be a co-directional etching process or an anisotropic etching process.

[0074] In at least one embodiment, the C4 bump 121 may also include contact pads (e.g., copper / nickel contact pads) (not shown) on the UBM layer and solder bumps (e.g., SnAg solder bumps) on the contact pads. The C4 bump 121 may allow the intermediate module 120 to be connected to a substrate such as a package substrate.

[0075] like Figure 1A To further explain, the semiconductor dies 140 can be mounted on the intermediate 10 such that the heights of the semiconductor dies 140 are approximately the same. Generally, the thickness of each semiconductor die 140 in the z-direction can be approximately the same. Therefore, the upper surfaces of each semiconductor die 140 can be approximately coplanar (e.g., formed on the same xy plane).

[0076] The front side 140f (e.g., the upper surface of the semiconductor die) of the semiconductor die 140 may face the dielectric 10. The semiconductor die 140 may also include a back side 140b, which faces away from the dielectric 10. The semiconductor die 140 may also include a back-end process (BEOL) region 142 (e.g., a silicon substrate region). The BEOL region 142 may be located on the back side 140b of the semiconductor die 140, opposite to the front-end process (FEOL) region 141. The semiconductor die 140 may be electrically coupled to the redistribution layer 12a in the dielectric 10 via interconnects 128.

[0077] An underfill layer 229 of the interposer module (e.g., individually or in connection) may be formed under and around each semiconductor die 140. The underfill layer 229 may also be formed around the interconnect 128. Thus, the underfill layer 229 secures each semiconductor die 140 to the interposer 10. The underfill layer 229 may be formed from an epoxy resin-based polymer material. Other suitable materials may be used for the underfill layer 229.

[0078] Semiconductor dies 140 may each have the same or different types. Each semiconductor die 140 may include, for example, a single semiconductor die, a chip system, or an integrated chip system die on a substrate, and may be implemented by on-chip-on-a-substrate technology or on-substrate integrated fan-out technology. In particular, each semiconductor die 140 may include, for example, semiconductor dies or chiplets for high-performance computing (HPC) applications, artificial intelligence (AI) applications, and 5G cellular network applications; logic dies (e.g., mobile application processors, microcontrollers, etc.); or memory dies (e.g., high-bandwidth memory (HBM) dies, hybrid memory cubes (HMC), dynamic random access memory (DRAM) dies, wide I / O dies, M-RAM dies, R-RAM dies, inverted AND (NAND) dies, static random access memory (SRAM), etc.); central processing unit (CPU) chips; graphics processing unit (GPU) chips; and field-programmable gates. FPGA chips, network chips, application-specific integrated circuit (ASIC) chips, artificial intelligence / deep neural network (AI / DNN) accelerator chips, coprocessors, accelerators, on-chip memory buffers, high data rate transceiver dies, I / O interface dies, integrated passive component (IPD) dies, power management dies (e.g., power management integrated circuit (PMIC) dies), frequency modulation (RF) dies, sensor dies, microelectromechanical systems (MEMS) dies, signal processing dies (e.g., digital signal processing (DSP) dies), front-end dies (e.g., analog front-end (AFE) dies), single-crystal 3D heterogeneous die stacks, etc. Other dies are within the scope of this disclosure.

[0079] In at least one embodiment, at least one of the semiconductor dies 140 may include a main die (e.g., a SOC die). Another semiconductor die 140 may include an auxiliary die (e.g., a memory / SOC die, an HBM die, etc.).

[0080] The intermediate module 120 may also include a molding material layer 127 formed around the semiconductor die 140. The molding material layer 127 may also be formed on and around the bottom filler layer 229 of the intermediate module. The molding material layer 127 may have an outer wall substantially aligned with the outer wall of the intermediate 10.

[0081] In at least one embodiment, a molding material layer 127 may be formed on the sidewalls (inner and outer sidewalls) of each semiconductor die 140. The molding material layer 127 may be formed between and bonded to the sidewalls of each semiconductor die 140. The molding material layer 127 may also be bonded to the bottom filler layer 229 of the interposer module and the upper passivation layer 13 on the chip side surface 10s1 of the interposer 10.

[0082] like Figure 1AAs shown, the molding material layer 127 may include a substantially uniform (e.g., flat) upper surface. The upper surface of the molding material layer 127 may alternatively or additionally include recessed portions (not shown) that are recessed in the z-direction from the upper surface of the semiconductor die 140.

[0083] In at least one embodiment, the molding material layer 127 may be formed of a curable material that can be cured to form a rigid solid structure. The molding material layer 127 may include, for example, an epoxy molding compound (EMC). In at least one embodiment, the molding material layer 127 may include a material substantially similar to the bottom filler layer 229 of the intermediate module. In at least one embodiment, the molding material layer 127 may include a polymeric material, particularly an epoxy-based polymeric material. Other suitable molding materials are within the scope of this disclosure.

[0084] In at least one embodiment, the molding material layer 127 may have a CTE substantially similar to that of the intermediate 10. In at least one embodiment, the molding material layer 127 may include additive materials (e.g., filler materials) to improve the properties of the molding material layer 127 (e.g., thermal conductivity, CTE, etc.). Additive materials may include, for example, metal powders, metal oxide powders, etc. Other materials in the molding material layer 127 are included within the scope contemplated by this disclosure.

[0085] Refer again Figure 1B The first interconnect portion 128a may include a first outer metal layer 128a1 (e.g., an outer copper layer) and a first inner metal layer 128a3 (e.g., an inner copper layer). A first alloy barrier layer 128a2 may be located between the first outer metal layer 128a1 and the first inner metal layer 128a3. The first alloy barrier layer 128a2, the first outer metal layer 128a1, and the first inner metal layer 128a3 may be substantially aligned (in the z-direction) and may have substantially the same diameter.

[0086] The second interconnect portion 128b may also include a second outer metal layer 128b1 (e.g., an outer copper layer) and a second inner metal layer 128b3 (e.g., an inner copper layer). A second alloy barrier layer 128b2 may be located between the second outer metal layer 128b1 and the second inner metal layer 128b3. The second alloy barrier layer 128b2, the second outer metal layer 128b1, and the second inner metal layer 128b3 may be substantially aligned (in the z-direction) and may have substantially the same diameter.

[0087] like Figure 1B To further explain, interconnect 128 can be determined by interconnect spacing P. i Separated. In at least one embodiment, the interconnect spacing P... i The interconnect spacing P can be 40μm or smaller, but greater than 40μm is acceptable. iAlso within the scope of this disclosure. The semiconductor die 140 can be connected to the intermediary 10 by a support height H. s Separate. Typically, the support height H... s This can refer to the distance between the bottom surface of a semiconductor die and the top surface of the intermediate material. For example... Figure 1B As shown, the support height H s This can refer to the distance between the die passivation layer 145 and the upper passivation layer 13 on the intermediary 10.

[0088] The support height H between the semiconductor die 140 and the intermediary 10 s This may vary depending on the specific design and requirements of the intermediary module 120. Support height H s It may range from a few micrometers to tens of micrometers. Support height H s The exact value may depend on factors such as bump size, material properties, thermal considerations, and overall design constraints of the intermediary module 120. In at least one embodiment, the support height H s The support height H may be in the range of 6μm to 40μm, but less than 6μm or greater than 40μm is acceptable. s This is also within the scope of the information disclosed herein.

[0089] The interconnect structure 128 can have an interconnect height H. i Intra-line height H i The thickness can be defined as the total thickness of the first interconnect portion 128a, the second interconnect portion 128b, and the weld joint 128c. In at least one embodiment, the interconnect height H i It can be substantially related to the support height H s The same. Therefore, the height H of the inner connector is... i The height H of the interconnect can be in the range of 6μm to 40μm, but the height H of the interconnect is less than 6μm or greater than 40μm. i Within the scope of this disclosure.

[0090] The first internal connection portion 128a may have a diameter D 128a Furthermore, the second inner connection portion 128b may have a diameter D. 128b The interconnect 128 may have an interconnect diameter D. i In essence, it is equal to the diameter D of the first inner connection portion 128a. 128a And it is essentially equal to the diameter D of the second inner connection portion 128b. 128b The diameter D of weld joint 128c 128c It can be larger than the diameter D of the internal interconnect. i In at least one embodiment, the diameter D of the weld joint 128c 128c The diameter D of the internal interconnect can be... iThe percentage is greater than 5% to 30%. Inner wire diameter D i The diameter D of the interconnect can be in the range of 1μm to 20μm, but smaller than 1μm or larger than 20μm. i It can also be expected within the scope of what has been revealed.

[0091] Inner connection height H i It can be smaller than the spacing P between interconnects. i In at least one embodiment, the interconnect height H i The spacing P between the inner lines can be adjusted. i The range is 25% to 75%. The diameter D of the internal interconnect is... i It can be smaller than the height H of the interconnect. i In at least one embodiment, the interconnect diameter D i It can be in the interconnect height H i The range is between 25% and 75%.

[0092] Refer again Figure 1C The solder layer 128c can have a thickness T 128c The first outer metal layer 128a1 may have a thickness T. 128a1 The first alloy barrier layer 128a2 may have a thickness T 128a2 Furthermore, the first inner metal layer 128a3 may have a thickness T. 128a3 The thickness of the first interconnect portion 128a can be expressed as the combined thickness of the first outer metal layer 128a1, the first alloy barrier layer 128a2, and the first inner metal layer 128a3 (e.g., T). 128a1 +T 128a2 +T 128a3 The thickness T of the first alloy barrier layer 128a2 128a2 The thickness T of the first outer metal layer 128a1 can be in the range of 1μm to 5μm. 128a1 The thickness can be approximately the same as that of the first alloy barrier layer 128a2. The thickness T of the first inner metal layer 128a3 is... 128a3 Thickness T less than 128c of solder layer 128c 25%. The thickness T of the 128c solder layer. 128c The thickness T can be greater than that of the first alloy barrier layer 128a2. 128a2 .

[0093] The second outer metal layer 128b1 may have a thickness T. 128b1 The second alloy barrier layer 128b2 may have a thickness T 128b2 Furthermore, the second inner metal layer 128b3 may have a thickness T. 128b3The thickness of the second interconnect portion 128b can be expressed as the combined thickness of the second outer metal layer 128b1, the second alloy barrier layer 128b2, and the second inner metal layer 128b3 (e.g., T). 128b1 +T 128b2 +T 128b3 The thickness T of the second alloy barrier layer 128b2 128b2 The thickness T of the second outer metal layer 128b1 can be in the range of 1μm to 5μm. 128b1 It can be approximately the same as the thickness T of the second alloy barrier layer 128b2. 128b2 Same. The thickness T of the second inner metal layer 128b3 128b3 Thickness T less than 128c of solder layer 128c 25%. The combined thickness of the first inner metal layer 128a3 and the second inner metal layer 128b3 can be less than the thickness T of the solder layer 128c. 128c Half of (T) 128a3 +T 128b3 <0.5T 128c Thickness T of solder layer 128c 128c The thickness T can be greater than that of the second alloy barrier layer 128b2. 128b2 .

[0094] The thickness of the first connecting portion 128a can be substantially the same as the thickness of the second connecting portion 128b. The thickness T of the first outer metal layer 128a1 128a1 The thickness T of the second outer metal layer 128b1 can be... 128b1 Essentially the same. The thickness T of the first alloy barrier layer 128a2 128a2 The thickness T of the second alloy barrier layer 128b2 can be... 128b2 They are essentially the same. The thickness T of the first inner metal layer 128a3 is... 128a3 The thickness T of the second inner metal layer 128b3 can be... 128b3 They are essentially the same.

[0095] like Figure 1C Further, the interconnect 128 may also include a first IMC layer 129a (lower IMC layer or interposer-side IMC layer) located at the interface between the solder layer 128c and the first inner metal layer 128a3. The interconnect 128 may also include a second IMC layer 129b (upper IMC layer or semiconductor die-side IMC layer) located at the interface between the solder layer 128c and the second inner metal layer 128b3. In at least one embodiment, the total thickness of the first IMC layer 129a and the second IMC layer 129b may be less than the thickness T of the solder layer 128c. 128c In at least one embodiment, the total thickness of the first IMC layer 129a and the second IMC layer 129b may be less than or equal to the thickness T of the solder layer 128c. 128c10%.

[0096] Figures 2A to 2N This is a vertical cross-sectional view of an intermediate structure of a method for fabricating a semiconductor module 120 according to one or more embodiments. Figure 2A This is a vertical cross-sectional view of an intermediate structure including a portion of an intermediary 10 (e.g., an organic intermediary) located on a first carrier substrate 1 (e.g., a carrier wafer) according to one or more embodiments. The lower passivation layer 14 of the intermediary 10 may be formed later in the method of forming the intermediary module 120.

[0097] The first carrier substrate 1 may comprise a circular wafer or a rectangular wafer. The lateral dimension of the first carrier substrate 1 (e.g., the diameter of a circular wafer or one side of a rectangular wafer) may range from 100 mm to 500 mm, for example from 200 mm to 400 mm, although smaller and larger lateral dimensions may also be used. The first carrier substrate 1 may comprise a semiconductor substrate, an insulating substrate, or a conductive substrate. The first carrier substrate 1 may be transparent or opaque. The thickness of the first carrier substrate 1 may be sufficient to provide mechanical support for the array of intermediates formed thereon. For example, the thickness of the first carrier substrate 1 may range from 60 μm to 1 mm, although smaller and larger thicknesses may also be used.

[0098] An adhesive layer (not shown) may be applied to the top surface of the first carrier substrate 1. In one embodiment, the first carrier substrate 1 may include an optically transparent material, such as glass or sapphire. In this embodiment, the adhesive layer may include a photothermal conversion (LTHC) layer. The LTHC layer is a solvent-based coating applied using a spin-coating method. The LTHC layer may form a layer that converts ultraviolet light into heat, causing the LTHC layer to lose its adhesiveness. For example, the LTHC layer may include any commercially available LTHC layer. Alternatively, the adhesive layer may include a thermally degradable adhesive material. For example, the adhesive layer may include an acrylic pressure-sensitive adhesive that decomposes at elevated temperatures. The debonding temperature of the thermally degradable adhesive material may be in the range of 150°C to 400°C. Other suitable thermally degradable adhesive materials that decompose at other temperatures are within the scope of this disclosure.

[0099] Multiple dielectric layers 12 and multiple redistribution layers 12a may be alternately formed on the first carrier substrate 1 (e.g., on an adhesive layer on the first carrier substrate 1). It should be noted that, although Figure 2A Two dielectric layers 12 and two redistribution layers 12a are shown, but this disclosure also considers more or fewer dielectric layers 12 and redistribution layers 12a.

[0100] Each dielectric layer 12 can be formed by depositing a layer of dielectric polymer material (such as polyimide (PI), benzocyclobutene (BCB), or polybenzodioxazole (PBO)) by means of chemical vapor deposition (CVD), physical vapor deposition (PVD), or other suitable deposition techniques. Other suitable materials are also within the scope of this disclosure. The thickness of the dielectric polymer material layer can range from 4 μm to 60 μm, although smaller and larger thicknesses can also be used. The dielectric layer 12 can then be patterned by a photolithography process to form vias in the dielectric layer 12. The photolithography process may include forming a patterned photoresist shield (not shown) on the dielectric material layer and etching (e.g., wet etching, dry etching, etc.) the exposed upper surface of the dielectric material through openings in the photoresist shield. The photoresist shield can then be removed by ashing, dissolving the photoresist shield, or consuming the photoresist shield during the etching process.

[0101] A redistribution layer 12a (e.g., metal lines and metal vias) may be formed on the dielectric layer 12. The redistribution layer 12a may be formed by depositing (e.g., by CVD, PVD, or other suitable deposition techniques) one or more layers of a metallic material (such as copper, aluminum, nickel, titanium, combinations thereof, or other suitable metals) on the dielectric layer 12 and in vias formed by patterning the dielectric layer 12. The metallic material layer may then be patterned by a photolithography process to form the redistribution layer. The photolithography process may include forming a patterned photoresist shield (not shown) on the metallic material layer and etching (e.g., wet etching, dry etching, etc.) through openings in the photoresist shield to expose the upper surface of the metallic material. The photoresist shield may subsequently be removed by ashing, dissolving the photoresist shield, or consuming the photoresist shield during the etching process.

[0102] like Figure 2A To further explain, an intermediary pad 16 may then be formed on the uppermost insulating layer 12 (e.g., on the chip-side surface 10s1 of the intermediary 10). In at least one embodiment, the intermediary pad 16 may be arranged as a two-dimensional array, which may be a two-dimensional periodic array, such as a rectangular periodic array.

[0103] Each dielectric pad 16 may be formed in a respective via 12a2 in the contact uppermost dielectric layer 12. The dielectric pad 16 may comprise any metallic material that can bond with solder material. The dielectric pad 16 may be formed by depositing (e.g., by CVD, PVD, or other suitable deposition techniques) one or more layers of a metal comprising metals, metal alloys, and / or other metal-containing compounds (e.g., Cu, Al, Ni, Mo, Co, Ru, Ti, Ta, W, TiN, TaN, WN, etc.). The metal layers may then be patterned by a photolithography process to form the dielectric pad 16. The photolithography process may include forming a patterned photoresist shield (not shown) on the metallic material and etching (e.g., wet etching, dry etching, etc.) through openings in the photoresist shield to expose the upper surface of the metallic material. The photoresist shield may subsequently be removed by ashing, dissolving the photoresist shield, or by consuming the photoresist shield during the etching process.

[0104] Figure 2B This is a vertical cross-sectional view of an intermediate structure, which, according to one or more embodiments, includes an upper passivation layer 13 located on the chip-side surface 10s1 of the interposer 10. The upper passivation layer 13 may be formed to have a thickness greater than the thickness of the interposer pad 16. Therefore, the upper passivation layer 13 may cover the interposer pad 16.

[0105] The upper passivation layer 13 can be formed by depositing one or more layers of passivation material (e.g., by CVD, PVD or other suitable deposition techniques), including silicon dioxide, silicon nitride, low dielectric constant dielectric materials (such as carbon-doped oxides), very low dielectric constant dielectric materials (such as porous carbon-doped silicon dioxide), combinations of the foregoing, or other suitable materials. The passivation material can then be planarized (e.g., by wet etching, dry etching, chemical mechanical polishing (CMP), etc.) to form the upper passivation layer 13.

[0106] Figure 2C According to one or more embodiments, an opening O is included in the upper passivation layer 13 on the chip-side surface 10s1 of the intermediate 10. 13 A vertical cross-sectional view of the intermediate structure. Opening O 13 It can be formed in the upper passivation layer 13 to expose the upper surface of the intermediate pad 16. Opening O 13 It can be formed by, for example, using a photolithography process.

[0107] Used to form an opening O 13The photolithography process (e.g., a process) may include forming a patterned photoresist shield (not shown) on the upper passivation layer 13 and etching (e.g., wet etching, dry etching, etc.) the upper surface of the upper passivation layer 13 exposed through openings in the photoresist shield. The photoresist shield may be subsequently removed by ashing, dissolving the photoresist shield, or consuming the photoresist shield during the etching process. An opening O is formed in the upper passivation layer 13. 13 Subsequently, the upper passivation layer 13 (upper solder resist layer) can be cured by heat curing or ultraviolet (UV) light curing.

[0108] Figure 2D This is a vertical cross-sectional view of an intermediate structure including a first seed layer 17 on an upper passivation layer 13 located on the chip-side surface 10s1 of the interposer 10, according to one or more embodiments. The first seed layer 17 can be formed, for example, by deposition (e.g., by CVD, PVD, or other suitable deposition techniques) of one or more seed layer material layers. The seed layer material may include, for example, titanium, copper, etc. Figure 2D As shown, the seed layer material can be deposited on the opening O. 13 On the upper surface of the neutralizing intermediary pad 16.

[0109] Figure 2E This is a vertical cross-sectional view of an intermediate structure including a patterned photoresist layer 5 on a first seed layer 17, according to one or more embodiments. The patterned photoresist layer 5 can be formed, for example, by deposition (e.g., by CVD, PVD, or other suitable deposition techniques) of a photoresist material layer (e.g., a UV-sensitive material). The photoresist material can then be exposed to UV light through a photomask including a pattern to be transferred onto the photoresist material. The photoresist material can then be developed (e.g., by immersion in a developer) to form the patterned photoresist layer 5. Figure 2E As shown, the patterned photoresist layer 5 may include openings O in the upper passivation layer 13. 13 The opening O5 is actually aligned.

[0110] Figure 2F This is a vertical cross-sectional view of an intermediate structure, which, according to one or more embodiments, includes a first bump 128aB in an opening O5 of a patterned photoresist layer 5. (See diagram below.) Figure 2F As shown, the first bump 128aB may include a first interconnect portion 128a and a first bump solder layer 128ca located on the first interconnect portion 128a.

[0111] The layers of the first bump 128aB can be sequentially deposited in the openings O5 of the patterned photoresist layer 5 in a series of separate deposition steps. For example, the layers of the first bump 128aB can be deposited by an electrochemical deposition process, although other suitable deposition techniques may also be used.

[0112] Specifically, a first outer metal layer 128a1 may be deposited in the opening O5. Then, a first alloy barrier layer 128a2 may be deposited on the first outer metal layer 128a1 in the opening O5. Next, a first inner metal layer 128b3 may be deposited on the first alloy barrier layer 128a2 in the opening O5. Finally, a first bump solder layer 128ca may be deposited on the first inner metal layer 128a3 in the opening O5.

[0113] Figure 2G This is a vertical cross-sectional view of an intermediate structure including a first bump 128aB located on a first seed layer 17, according to one or more embodiments. Figure 2G As shown, after the first bump 128aB is formed, the patterned photoresist layer 5 can be removed. The patterned photoresist layer 5 can be removed by, for example, ashing or dissolving the patterned photoresist layer 5.

[0114] Removing the patterned photoresist layer 5 exposes the upper surface of the first seed layer 17. The first bumps 128aB remain respectively on the first seed layer 17 on the interposer pad 16.

[0115] Figure 2H This is a vertical cross-sectional view of an intermediate structure including a first bump 128aB located on a first seed layer 17, according to one or more embodiments. Figure 2H As shown, after the patterned photoresist layer 5 is removed, the exposed portion of the first seed layer 17 can be removed. The exposed portion of the first seed layer 17 may include those portions of the first seed layer 17 not covered by the first bump 128aB.

[0116] The exposed portion of the first seed layer 17 can be removed, for example by an etching process (e.g., wet etching, dry etching, etc.). Removing the exposed portion of the first seed layer 17 exposes the upper passivation layer 13 located between the first bumps 128aB.

[0117] Figure 2I This is a vertical cross-sectional view of an intermediate structure including a first bump 128aB after a reflow process, according to one or more embodiments. Figure 2I As shown, after removing the exposed portion of the first seed layer 17, a reflow process can be performed on the first bump solder layer 128ca. The reflow process can be performed by heating the solder material of the solder layer 128ca to its melting point and then carefully controlling the cooling process. The reflow process allows for precise control of the shape and size of the first bump solder layer 128ca.

[0118] Figure 2J This is a vertical cross-sectional view of an intermediate structure, including a semiconductor die 140 located on an intermediary 10, according to one or more embodiments. For example... Figure 2JAs shown, the semiconductor die 140 may include a second bump 128bB. The second bump 128bB may be substantially similar to the first bump 128aB. In particular, the second bump 128bB may include a second interconnect portion 128b and a second bump solder layer 128cb located on the second interconnect portion 128b.

[0119] The second protrusion 128bB can be accessed by the aforementioned Figures 2A to 2I The process of forming the first bump 128aB is essentially the same as the process of forming the first bump. Specifically, the die pad 146 may be formed on the front side 140f of the semiconductor die 140 (e.g., see...). Figure 2A A die passivation layer 145 may be formed on the front side 140f of the semiconductor die 140 and on the die pad 146 (see, for example, see...). Figure 2B An opening may be formed in the die passivation layer 145 above the die pad 146 (see, for example, see...). Figure 2C The second seed layer 147 can be deposited in the die passivation layer 145 and the opening (e.g., see...). Figure 2D A patterned photoresist layer may be formed on the second seed layer 147 (e.g., see...). Figure 2E Furthermore, the second bump 128bB can be formed in the opening of the patterned photoresist layer (e.g., see [reference]). Figure 2F The patterned photoresist layer can then be removed (e.g., see...). Figure 2G This can remove the exposed portion of the second seed layer 147 (e.g., see...). Figure 2H Then a reflow process can be performed on the second bump solder layer 128cb (e.g., see...). Figure 2I ).

[0120] After forming the second bump 128bB on the semiconductor die 140, the semiconductor die 140 can be positioned on the interposer 10. The semiconductor die 140 can be positioned on the interposer 10 using an electromechanical pick-and-place (PNP) machine. In particular, the semiconductor die 140 can be positioned on the interposer 10 such that the second bump 128bB can be substantially aligned with the first bump 128aB. The second bump solder layer 128cb of the second bump 128bB can be adjacent to the first bump solder layer 128ca of the first bump 128aB. In at least one embodiment, the second bump solder layer 128cb of the second bump 128bB can contact the first bump solder layer 128ca of the first bump 128aB.

[0121] Figure 2KThis is a vertical cross-sectional view of an intermediate structure including a semiconductor die 140 located on an interposer 10, according to one or more embodiments. A reflow process can be performed after the second bump solder layer 128cb of the second bump 128bB contacts the first bump solder layer 128ca of the first bump 128aB. During the reflow process, the first bump solder layer 128ca and the second bump solder layer 128cb are melted together to form a solder joint 128c. During the reflow process, the position of the semiconductor die 140 can be adjusted to ensure a desired support height H is achieved between the semiconductor die 140 and the interposer 10. s .

[0122] Each semiconductor die 140 may be coupled to the intermediate 10 by one or more interconnects 128. In at least one embodiment, the interconnects 128 may comprise a two-dimensional array of interconnects 128.

[0123] Figure 2L This is a vertical cross-sectional view including an underfill layer 229 of a median module according to one or more embodiments. The underfill layer 229 of the median module can be formed by depositing and / or injecting an underfill material (e.g., an epoxy-based polymer material) onto the median 10. The underfill material can be applied to the median 10 to form below the semiconductor die 140 and around the interconnects 128. In at least one embodiment, the underfill material can fill virtually all the gap between the semiconductor die 140 and the median 10. The underfill material can then be cured to form the underfill layer 229 of the median module. For example, the underfill material can be cured in an oven in the temperature range of 120°C to 180°C for a duration ranging from 60 minutes to 120 minutes to provide an underfill layer 229 of the median module with sufficient rigidity and mechanical strength.

[0124] Figure 2M This is a vertical cross-sectional view of an intermediate structure including a molding material layer 127 according to one or more embodiments. The molding material layer 127 (e.g., an encapsulation layer) may be formed on the semiconductor die 140 and the interposer 10. In at least one embodiment, the molding material layer 127 may be formed by a sequence of molding and planarization processes. Specifically, the molding material layer 127 may include an epoxy polymer material (e.g., an epoxy molding compound (EMC)). The molding material layer 127 may be formed on the interposer 10 and fill the gaps between the semiconductor dies 140. The molding material layer 127 may encapsulate (e.g., in the x and y directions) the semiconductor die 140. The molding material layer 127 may be formed, for example, by a deposition process such as CVD, PECVD, PVD, spin coating, lamination, or other suitable deposition techniques.

[0125] A molding material layer 127 may be deposited to completely cover the semiconductor die 140 and the bottom fill layer 229 of the intermediate module. After the molding material layer 127 has cured, a planarization process may be used to make the upper surface of the molding material layer 127 substantially coplanar with the upper surface of the semiconductor die 140. The planarization process may be performed on the upper surface of the molding material layer 127 until the upper surface of the semiconductor die 140 is exposed. The planarization process may include, for example, a mechanical polishing process and / or a chemical mechanical polishing process.

[0126] Figure 2N A vertical cross-sectional view of an intermediate structure is shown, comprising a plurality of C4 bumps 121, according to one or more embodiments. After the molding material layer 127 has been cured and planarized (e.g., by grinding, chemical mechanical polishing, etc.), the intermediate structure can be attached to a second carrier substrate 2. The second carrier substrate 2 can be substantially similar to the first carrier substrate 1. In particular, the second carrier substrate 2 can be attached to the upper surface of the molding material layer 127 and the upper surface of the semiconductor die 140.

[0127] Figure 2N The intermediate structure can then be inverted, and the first carrier substrate 1 can be separated from the plate-side surface 10s2 of the intermediate 10. The first carrier substrate 1 can be separated from the intermediate 10 by deactivating the adhesive layer (not shown) attached to the first carrier substrate 1 to the intermediate 10. The adhesive layer can be deactivated by thermal annealing at an elevated temperature (e.g., for adhesive materials that can be deactivated by heat) or by exposing the adhesive layer to ultraviolet light (e.g., for adhesive materials that can be deactivated by ultraviolet light).

[0128] Then, a lower dielectric pad (if present) may be formed on the bottom dielectric layer 12 of the intermediate 10. The lower dielectric pad may be formed using substantially the same material and substantially the same photolithography process as the aforementioned intermediate pad 16. Then, a lower passivation layer 14 may be formed on the lower dielectric layer 12 of the intermediate 10 and on the lower dielectric pad (if present).

[0129] The lower passivation layer 14 can be formed by depositing one or more layers of passivation material (e.g., by CVD, PVD or other suitable deposition techniques), including silicon dioxide, silicon nitride, low-dielectric-constant dielectric materials (such as carbon-doped oxides), very low-dielectric-constant dielectric materials (such as porous carbon-doped silicon dioxide), combinations of the foregoing or other suitable materials. The passivation material can then be planarized (e.g., by wet etching, dry etching, chemical mechanical polishing (CMP) or the like) to form the lower passivation layer 14. The lower passivation layer 14 can then be etched by a suitable etching process (e.g., by wet etching, dry etching, or the like) to form an opening above the redistribution layer 12a in the lower dielectric layer 12 (or above the pads below the intermediate, if present).

[0130] Next, a plurality of C4 bumps 121 are formed on the intermediate structure. The C4 bumps 121 may include solder bumps, for example, formed within openings in the lower passivation layer 14. The C4 bumps 121 may be formed by one or more processes, including ball loading, electroplating, solder printing, solder immersion, and solder implantation. The C4 bumps 121 may contact the redistribution layer 12a (or pads below the intermediate, if present) within the lower dielectric layer 12 of the intermediate 10 through the openings in the lower passivation layer 14.

[0131] In at least one embodiment, the C4 bump 121 can be formed by forming one or more bottom metal layers (UBM) (not shown) on the exposed surface of the redistribution layer 12a (or, if present, the exposed surface of the under-intermediate pad), forming metal pillars on the UBM layers, and then forming solder bumps on the metal pillars.

[0132] Figure 3 This is a flowchart illustrating a method for fabricating an intermediate module 120 according to one or more embodiments. Step 310 includes forming a plurality of first bumps on the intermediate, wherein the plurality of first bumps includes a first alloy barrier layer and a first bump solder layer. Step 320 includes forming a plurality of second bumps on a semiconductor die, wherein the plurality of second bumps includes a second alloy barrier layer and a second bump solder layer. Step 330 includes positioning the semiconductor die on the intermediate such that the second bump solder layers are adjacent to the first bump solder layers. Step 340 includes forming a plurality of interconnects connecting the intermediate to the semiconductor die by melting the second bump solder layers together with the first bump solder layers to form solder joints.

[0133] Figure 4 This is a detailed vertical cross-sectional view of the interconnect 128 in the intermediary module 120 having a first alternative design, according to one or more embodiments. Figure 4 As shown, the first alternative design of the intermediary module 120 can be with Figures 1A to 1C The designs in the embodiments are basically the same. However, with Figures 1A to 1CCompared to the embodiments, the first alternative design may omit the first inner metal layer 128a3 (e.g., an inner copper layer) and the second inner metal layer 128b3 (e.g., an inner copper layer). The first interconnect portion 128a may include a first outer metal layer 128a1 and a first alloy barrier layer 128a2. The second interconnect portion 128b may include a second outer metal layer 128b1 and a second alloy barrier layer 128b2.

[0134] like Figure 4 To further explain, in the first alternative design, the interconnect height H i (and support height H) s It may be smaller than Figures 1A to 1C The interconnect height H in the embodiment i In at least one embodiment, the interconnect height H i (and support height H) s It may be in the range of 5μm to 35μm, although the interconnect height H i The spacing P of the interconnects in the first alternative design is less than 5 μm or greater than 35 μm, which is within the scope of this disclosure. i It may also be smaller than Figures 1A to 1C The spacing P between interconnects in the embodiment i In at least one embodiment, the interconnect spacing P i It may be 35μm or smaller, but the interconnect spacing P i Greater than 35 μm is within the expected range of this disclosure.

[0135] In the first alternative design, the interconnect diameter D i The diameter D of the weld joint 128c 128c Possibly with Figures 1A to 1C The embodiments are essentially the same. In at least one embodiment, the interconnect diameter D in the first alternative design is... i The diameter D of the weld joint 128c 128c They may be less than (for example, at most about 15%). Figures 1A to 1C In the embodiment, the interconnect diameter D i The diameter D of the weld joint 128c 128c .

[0136] Figure 5 This is a detailed vertical cross-sectional view of the interconnect 128 in the intermediary module 120 having a second alternative design, according to one or more embodiments. (See attached image.) Figure 5 As shown, the second alternative design of the intermediary module 120 can be combined with... Figures 1A to 1C Design in the embodiments and Figure 4 The first alternative design is essentially the same. However, it is different from... Figures 1A to 1CCompared to the embodiments, besides omitting the first inner metal layer 128a3 and the second inner metal layer 128b3, the second alternative design may also omit the first outer metal layer 128a1 and the second outer metal layer 128b1. The first interconnect portion 128a may include a first alloy barrier layer 128a2. The second interconnect portion 128b may include a second alloy barrier layer 128b2.

[0137] like Figure 5 To further explain, in the first alternative design, the interconnect height H i (and support height H) s It may be smaller than Figures 1A to 1C The interconnect height H in the embodiment i In at least one embodiment, the interconnect height H i (and support height H) s It may be in the range of 3μm to 25μm, although the interconnect height H i A spacing of less than 3 μm or greater than 25 μm is still within the expected range of this disclosure. The interconnect spacing P in the first alternative design... i It may also be smaller than Figures 1A to 1C The spacing P between interconnects in the embodiment i In at least one embodiment, the interconnect spacing P i It may be 25μm or smaller, but the interconnect spacing P i Sizes greater than 25 μm are still within the expected range of this disclosure.

[0138] In the second alternative design, the interconnect diameter D i The diameter D of the weld joint 128c 128c Possibly with Figures 1A to 1C The embodiments are essentially the same. In at least one embodiment, the interconnect diameter D in the second alternative design is different. i The diameter D of the weld joint 128c 128c They may be less than (for example, at most about 20%). Figures 1A to 1C The diameter D of the interconnect in the embodiment i The diameter D of the weld joint 128c 128c .

[0139] Figure 6 This is a vertical cross-sectional view of an encapsulation structure 100 including an intermediary module 120 according to one or more embodiments.

[0140] like Figure 6As shown, the package structure 100 may include a package substrate 110 and an intermediate module 120 located on the package substrate 110. The package structure 100 may also include a package cover 130 located on the intermediate module 120. The package cover 130 may include a package cover pin portion 130a attached to the package substrate 110. The package cover 130 may also include a package cover plate portion 130p connected to the package cover pin portion 130a. The package structure 100 may also include a TIM layer 170 located between the intermediate module 120 and the package cover plate portion 130p.

[0141] The packaging substrate 110 may include a cored or coreless substrate. For example, in at least one embodiment, the packaging substrate 110 may include a core layer 112, an upper dielectric layer 114 formed on the core layer 112 (e.g., on a first side or chip side of the packaging substrate 110), and a lower dielectric layer 116 formed on the core layer 112 (e.g., on a second side or circuit board side of the packaging substrate 110). In particular, the packaging substrate 110 may include a stacked thin film substrate, such as an Ajinomoto build-up film (ABF) substrate. That is, in at least one embodiment, each of the upper dielectric layer 114 and the lower dielectric layer 116 may be described as an ABF layer.

[0142] The core layer 112 may be used to provide rigidity to the encapsulation substrate 110. The core layer 112 may include, for example, epoxy resins such as bismaleimide triazine epoxy (BT epoxy) and / or braided glass laminates. The core layer 112 may alternatively or additionally include organic materials, such as polymeric materials. In particular, the core layer 112 may include dielectric polymeric materials such as polyimide (PI), benzocyclobutene (BCB) polymers, or polybenzodioxazole (PBO). Other suitable dielectric materials are within the scope of this disclosure.

[0143] The core layer 112 may include one or more vias 112a. The vias 112a may extend from the lower surface of the core layer 112 to the upper surface of the core layer 112. The vias 112a may allow electrical connection between the dielectric layer 114 on the package substrate and the dielectric layer 116 below the package substrate. The vias 112a may include, for example, one or more layers, and may include metals, metal alloys, and / or other metal-containing compounds (e.g., Cu, Al, Mo, Co, Ru, W, TiN, TaN, WN, etc.). Other suitable metallic materials are within the scope of this disclosure.

[0144] A dielectric layer 114 on the packaging substrate may be formed on the upper surface of the core layer 112. The dielectric layer 114 on the packaging substrate may include multiple layers, and in particular may include stacked thin films (e.g., ABF). The dielectric layer 114 on the packaging substrate may also include organic materials, such as polymeric materials. In particular, the dielectric layer 114 on the packaging substrate may include dielectric polymeric materials such as polyimide (PI), benzocyclobutene (BCB), or polybenzodioxazole (PBO). Other suitable dielectric materials are also included within the scope of this disclosure.

[0145] The dielectric layer 114 on the package substrate may include one or more on-package substrate pads 114a located on the chip-side surface of the dielectric layer 114 on the package substrate. The on-package substrate pads 114a may be exposed on the chip-side surface of the dielectric layer 114 on the package substrate. The dielectric layer 114 on the package substrate may also include one or more metal interconnect structures 114b. The metal interconnect structures 114b may electrically couple the on-package substrate pads 114a to vias 112a in the core layer 112. The metal interconnect structures 114b may include a metal layer (e.g., a copper conductor) and metal vias connecting the metal layer. The on-package substrate pads 114a and the metal interconnect structures 114b may include, for example, one or more layers, and may include metals, metal alloys, and / or other metal-containing compounds (e.g., Cu, Al, Mo, Co, Ru, W, TiN, TaN, WN, etc.). Other suitable metallic materials are within the scope of this disclosure.

[0146] A passivation layer 110a on the package substrate may be formed on the chip-side surface of the dielectric layer 114 on the package substrate. The passivation layer 110a on the package substrate may at least partially cover the pad 114a on the package substrate. The passivation layer 110a may include silicon dioxide, silicon nitride, a low dielectric constant dielectric material such as carbon-doped oxide, an extremely low dielectric constant dielectric material such as porous carbon-doped silicon dioxide, a combination of the foregoing materials, or other suitable materials.

[0147] A substrate-under dielectric layer 116 may be formed on the lower surface of the core layer 112. The substrate-under dielectric layer 116 may also comprise multiple layers, particularly stacked thin films (e.g., ABF). The substrate-under dielectric layer 116 may also comprise organic materials, such as polymeric materials. In particular, the substrate-under dielectric layer 116 may comprise dielectric polymeric materials such as polyimide (PI), benzocyclobutene (BCB), or polybenzodioxazole (PBO). Other suitable dielectric materials are also included within the scope of this disclosure.

[0148] The under-package dielectric layer 116 may include one or more under-package pads 116a located on the board-side surface of the under-package dielectric layer 116. The under-package dielectric layer 116 may also include one or more metal interconnect structures 116b. The metal interconnect structures 116b may electrically couple the under-package pads 116a to vias 112a located in the core layer 112. The metal interconnect structures 116b may include metal layers (e.g., copper wires) and metal vias connecting the metal layers. The under-package pads 116a and the metal interconnect structures 116b may include, for example, one or more layers, and may include metals, metal alloys, and / or other metal-containing compounds (e.g., Cu, Al, Mo, Co, Ru, W, TiN, TaN, WN, etc.). Other suitable metallic materials are within the scope of this disclosure.

[0149] A passivation layer 110b under the package substrate may be formed on the board-side surface of the dielectric layer 116 under the package substrate. The passivation layer 110b under the package substrate may at least partially cover the pad 116a under the package substrate. The passivation layer 110b under the package substrate may include silicon dioxide, silicon nitride, low dielectric constant dielectric materials such as carbon-doped oxides, very low dielectric constant dielectric materials such as porous carbon-doped silicon dioxide, combinations thereof, or other suitable materials.

[0150] The ball grid array (BGA) includes a plurality of solder balls 110c, which may be formed on the board-side surface of the package substrate 110. The solder balls 110c allow the package structure 100 to be securely mounted on a substrate, such as a printed circuit board (PCB), and electrically coupled to the PCB substrate. The solder balls 110c may contact the lower pads 116a of the package substrate. Therefore, the solder balls 110c may be electrically connected to the upper pads 114a of the package substrate via metal interconnect structures 116b, vias 112a, and metal interconnect structures 114b. The solder balls 110c of the BGA may be formed in a two-dimensional array located on the board-side surface of the package substrate 110. For example, the solder balls 110c may be located below the package lead portion 130a and below the intermediate module 120.

[0151] like Figure 6 As shown, the width of the packaging substrate 110 in the x-direction may be greater than the width of the intermediate module 120 in the x-direction. The length of the packaging substrate 110 in the y-direction may also be greater than the length of the intermediate module 120 in the y-direction. The intermediate module 120 may be located in the central portion of the packaging substrate 110.

[0152] Intermediate module 120 can be attached to package substrate pad 114a in package substrate 110 via C4 bump 121. C4 bump 121 may include metal pillars (not shown) and solder bumps (e.g., tin-silver solder bumps) located on the metal pillars. The solder bumps may be crushed to connect C4 bump 121 to package substrate pad 114a.

[0153] An underfill layer 129 may be formed on the package substrate 110, located below and around the intermediate module 120. The underfill layer 129 may also be formed around the C4 bump 121. In this way, the underfill layer 129 securely attaches the intermediate module 120 to the package substrate 110. The underfill layer 129 may be formed of an underfill material, such as an epoxy-based polymer. Other suitable materials may also be used for the underfill layer 129.

[0154] TIM layer 170 may be located on mediator module 120. TIM layer 170 may include one or more layers. In at least one embodiment, the center of TIM layer 170 may be substantially aligned with the center of mediator module 120. In at least one embodiment, TIM layer 170 may extend laterally (e.g., in the xy plane) beyond the outer wall of molding material layer 127.

[0155] The TIM layer 170 may have low bulk thermal resistance and high thermal conductivity. The TIM layer 170 may cover the entire area of ​​the upper surface of the intermediate module 120. The TIM layer 170 may be attached to the upper surface of the intermediate module 120 by means of a thermally conductive adhesive.

[0156] In at least one embodiment, the TIM layer 170 may include one or more metals. The TIM layer 170 may include, for example, a low-melting-point (LMT) metal TIM or a liquid metal TIM. The TIM layer 170 may include one or more metals, such as indium, tin, gallium, silver, etc. The TIM layer 170 may include, for example, gallium-based, indium-based, silver-based, solder-based, etc. The solder base may include tin and one or more other elements, such as copper, silver, bismuth, indium, zinc, antimony, etc.

[0157] The TIM layer 170 may alternatively or additionally include thermal paste, thermal adhesive, thermal film, thermal sealant, thermal gap filler, thermal pad (e.g., silicone), thermal tape, or gel-type TIM (e.g., cross-linked polymer film). In at least one embodiment, the TIM layer 170 may include graphite, carbon nanotubes (CNTs), phase change materials (PCMs), etc. The PCM may include, for example, polymer-based PCMs. In at least one embodiment, the PCM can change its phase from solid to a high-viscosity semi-liquid at approximately 60°C. Other materials in the TIM layer 170 are contemplated within the scope of this disclosure.

[0158] like Figure 6 To further explain, the encapsulation cover 130 may be located on the TIM layer 170 and may serve as a cover for the intermediate module 120. The encapsulation cover 130 may be formed, for example, of a metal, ceramic, or polymer material. Other suitable materials for the encapsulation cover 130 may be used.

[0159] The package lead portion 130a may be attached to the package substrate 110. The package lead portion 130a may extend from the package cover portion 130p in a generally vertical direction. The package lead portion 130a may be connected to the package substrate 110 by an adhesive layer 160. The adhesive layer 160 may include, for example, an epoxy adhesive or a silicone adhesive. Other adhesives are within the scope of this disclosure.

[0160] A cover portion 130p (e.g., the body of the cover 130) may be connected to a foot portion 130a (e.g., the upper end of the foot portion 130a). In at least one embodiment, the cover portion 130p may be integrally formed as a unit with the foot portion 130a. Alternatively, the cover portion 130p may be formed separately from the foot portion 130a and attached to the foot portion 130a by an adhesive (not shown). The adhesive may be substantially similar to the adhesive layer 160 described above.

[0161] The encapsulation cover portion 130p may have an extended plate shape, for example, extending to... Figure 6 The outer periphery of the package cover portion 130p may be substantially aligned with the outer periphery of the package cover foot portion 130a. The package cover portion 130p may be substantially parallel to the upper surface of the package substrate 110. The package cover portion 130p may include a central region formed above the intermediate module 120. In at least one embodiment, the center point of the central region (in the xy plane) may be substantially aligned with the center point of the intermediate module 120 and / or the center point of the TIM layer 170.

[0162] The encapsulation substrate 110 may have a generally rectangular shape, with its length in the x-direction greater than its width in the y-direction. Alternatively, the encapsulation substrate 110 may have a generally square shape. The encapsulation lead portion 130a and the interposer module 120 may each have a shape substantially the same as that of the encapsulation substrate 110. Other shapes of the encapsulation substrate 110, encapsulation lead 130, and interposer module 120 are also considered within the scope of the disclosure. The interposer module 120 may be arranged in the central portion of the encapsulation substrate 110 such that the space between the interposer module 120 and the encapsulation lead portion 130a is substantially uniform around the periphery of the interposer module 120.

[0163] Figures 7A to 7G Various intermediate structures in a method of forming a package structure 100 according to one or more embodiments are shown. Figure 7A This is a vertical cross-sectional view of an intermediate structure of a package substrate 110 having an upper package substrate pad 114a and a lower package substrate pad 116a, according to one or more embodiments. A package substrate 110 may be provided including a core layer 112, an upper package substrate dielectric layer 114, and a lower package substrate dielectric layer 116.

[0164] The on-substrate pad 114a may be formed on, for example, the uppermost dielectric layer of the on-substrate dielectric layer 114. The on-substrate pad 114a may be formed as a contact metal interconnect structure 114b. The on-substrate pad 114a may be formed by depositing a metal layer (e.g., copper, aluminum, or other suitable conductive material) on the upper surface of the on-substrate dielectric layer 114. The metal layer may then be patterned by etching (e.g., by wet etching, dry etching, etc.) to form the on-substrate pad 114a. Other suitable metal layer materials and etching processes are available within the scope disclosed.

[0165] The lower substrate pad 116a can be formed on, for example, the bottom dielectric layer of the lower substrate dielectric layer 116. The lower substrate pad 116a can be formed as a contact metal interconnect structure 116b. The formation method of the lower substrate pad 116a can be similar to the formation method of the upper substrate pad 114a (e.g., depositing a metal layer, patterning the metal layer by etching, etc.).

[0166] After formation, the upper package substrate pad 114a and the lower package substrate pad 116a may selectively undergo surface roughening treatment (e.g., copper zarazara (CZ) treatment). In the surface roughening treatment, the surfaces of the upper package substrate pad 114a (e.g., copper surface) and the lower package substrate pad 116a (e.g., copper surface) may be etched using an organic acid-based micro-etching solution to create ultra-rough surfaces (e.g., copper surfaces). The uniquely rough copper surfaces of the upper package substrate pad 114a and the lower package substrate pad 116a can contribute to achieving high copper-resin adhesion.

[0167] Next, an upper passivation layer 110a and a lower passivation layer 110b can be formed on the upper pad 114a and the lower pad 116a of the packaging substrate, respectively. In at least one embodiment, the upper passivation layer 110a and the lower passivation layer 110b may each include a solder resist layer (e.g., a polymer material), also referred to as a solder resist film. The upper passivation layer 110a can also be referred to as the upper solder resist layer 110a, and the lower passivation layer 110b can also be referred to as the lower solder resist layer 110b.

[0168] The passivation layer 110a on the packaging substrate and the passivation layer 110b on the packaging substrate can be applied simultaneously. For example, the passivation layer 110a on the packaging substrate and the passivation layer 110b on the packaging substrate can be applied as a liquid photo-imageable film. For example, the liquid photo-imageable film can be applied to the surface of the packaging substrate 110 by screen printing or spraying. The liquid photo-imageable film can be applied to the upper pad 114a and the lower pad 116a of the packaging substrate. Alternatively, the passivation layer 110a on the packaging substrate and the passivation layer 110b on the packaging substrate can be applied as a dry film photo-imageable film, which can be vacuum-laminated onto the surface of the packaging substrate 110 and cover the upper pad 114a and the lower pad 116a of the packaging substrate, respectively. The passivation layer 110a on the packaging substrate and the passivation layer 110b under the packaging substrate may be formed alternatively or additionally, for example by chemical vapor deposition (CVD), physical vapor deposition (PVD), spin coating, lamination or other suitable deposition techniques.

[0169] The thickness of the passivation layer 110a on the package substrate and the passivation layer 110b on the package substrate can be slightly greater than the thickness of the upper pad 114a and the lower pad 116a on the package substrate. Alternatively, the upper surfaces of the passivation layer 110a on the package substrate and the passivation layer 110b on the package substrate can be approximately coplanar with the upper surfaces of the upper pad 114a and the lower pad 116a on the package substrate.

[0170] Next, an opening O can be formed in the passivation layer 110a on the packaging substrate. 110a This exposes the upper surface of the pad 114a on the packaging substrate. An opening O can be formed in the passivation layer 110b under the packaging substrate. 110b This exposes the upper surface of the lower pad 116a of the package substrate. Opening O 110a and opening O 110b It can be formed, for example, using a photolithography process. In at least one embodiment, the opening O 110a and opening O 110b It can be formed in different photolithography processes.

[0171] Used to form an opening O 110a The photolithography process (e.g., a process) may include forming a patterned photoresist shield (not shown) on a passivation layer 110a on a package substrate, and etching (e.g., wet etching, dry etching, etc.) the upper surface of the passivation layer 110a on the package substrate through openings in the photoresist shield. The photoresist shield may then be removed by ashing, dissolving the photoresist shield, or consuming the photoresist shield during the etching process.

[0172] Used to form an opening O 110bThe photolithography process (e.g., a process) may include forming a patterned photoresist shield (not shown) on a passivation layer 110b under the package substrate and etching (e.g., wet etching, dry etching, etc.) through openings in the photoresist shield to expose the upper surface of the passivation layer 110b under the package substrate. The photoresist shield may then be removed by ashing, dissolving the photoresist shield, or consuming the photoresist shield during the etching process.

[0173] An opening O is formed in the passivation layer 110a on the packaging substrate. 110a And an opening O is formed in the passivation layer 110b under the packaging substrate. 110b Subsequently, the passivation layer 110a (upper solder resist layer) on the packaging substrate and the passivation layer 110b (lower solder resist layer) on the packaging substrate can be cured by means of heat curing or ultraviolet (UV) curing.

[0174] Figure 7B This diagram illustrates a vertical cross-sectional view of an intermediate structure on a package substrate 110, according to one or more embodiments. The intermediate module 120 can be mounted on the package substrate 110 via a die-on-chip (FCB) process. The intermediate module 120 can be positioned above the package substrate 110 via an electromechanical placement (PNP) machine. C4 bumps 121 (e.g., solder bumps) on the intermediate module 120 can then be visible through openings O in the passivation layer 110a on the package substrate. 110a (see Figure 7A The intermediate structure, including the intermediate module 120 and the package substrate 110, is then heated to cause the C4 bump 121 to collapse and bond to the package substrate pad 114a. In at least one embodiment, laser-assisted bonding (LAB) can be used to reflow the C4 bump 121, allowing the intermediate module 120 to be attached to the package substrate pad 114a.

[0175] Figure 7C This diagram shows a vertical cross-sectional view of an intermediate structure of a package substrate 110 on which an underfill layer 129 may be formed, according to one or more embodiments. The underfill layer 129 may be formed by applying a liquid material, such as an epoxy-based polymer material, to the surface of the package substrate 110. Figure 7C As shown, an underfill layer 129 may be formed (e.g., injected) under and around the intermediate module 120 and the C4 bump 121, and is formed on the package substrate 110. The underfill layer 129 may then be cured, for example, in a box oven at a temperature ranging from 120°C to 740°C for 60 to 120 minutes, to provide an underfill layer 129 with sufficient rigidity and mechanical strength.

[0176] After the bottom filler layer 129 of the package has cured, a test procedure can be performed to test the intermediate structure (e.g., the intermediate module 120 and the package substrate 110). After the test procedure is completed, optional surface mount devices (SMDs) (not shown), such as DRAM devices and multilayer ceramic capacitor (MLCC) devices, can be mounted on the surface of the package substrate 110 adjacent to the intermediate module 120. In one embodiment, a 3D template can be used to define which areas can be covered with solder paste, and the DRAM devices and MLCC devices can be attached to the package substrate 110 by solder bumps (e.g., a reflow process). The procedure for attaching the DRAM devices and MLCC devices to the package substrate 110 can be substantially similar to the procedure described above for attaching the intermediate module 120 to the package substrate 110.

[0177] Figure 7D The diagram illustrates a vertical cross-sectional view of an intermediate structure, according to one or more embodiments, in which a TIM layer 170 may be formed on (e.g., attached to) an intermediary module 120. The TIM layer 170 may be applied to have a width in the x-direction and a length in the y-direction, the width and length being less than the final width and length of the TIM layer 170, because the imprinting of the encapsulation cap 130 will cause deformation of the TIM layer 170 and lateral expansion of the TIM layer 170 in the x and y directions.

[0178] In at least one embodiment, a thermally conductive adhesive may or may not be applied to the upper surface of the intermediary module 120, depending on the type of TIM layer 170 used. The material of the TIM layer 170 may be dispensed onto the upper surface of the intermediary module 120 in liquid form (e.g., grease, gel, paste, etc.) (or, if present, onto the thermally conductive adhesive). In embodiments where the TIM layer 170 comprises a solid material, the TIM layer 170 may be pressed onto the intermediary module 120 or onto the adhesive (if present).

[0179] After the TIM layer 170 is formed on the intermediate module 120, additional processes can be performed to prepare for attaching the package cap 130 to the package substrate. These processes may include, for example, flux cleaning, pre-baking, and plasma processes.

[0180] Figure 7EThe diagram shows a vertical cross-sectional view of an intermediate structure to which an adhesive layer 160 may be applied to a package substrate 110 according to one or more embodiments. The adhesive layer 160 may be applied to the package substrate 110 using a dispensing tool (e.g., an automated dispensing tool). The dispensing tool may dispense the adhesive layer 160 in a frame shape around the intermediate module 120. Upon application, the adhesive layer 160 may be rigid enough to form semi-solid beads on the surface of the package substrate 110. In at least one embodiment, the viscosity of the adhesive layer 160 may be 50,000 centipoise or greater upon application. The shape of the semi-solid beads may remain substantially unchanged between application by the dispensing tool and subsequent attachment of the package cap 130. The position of the frame shape of the adhesive layer 160 may correspond to the position of the foot portion 130a of the package cap 130. Pressing the package cap 130 onto the adhesive layer 160 may deform the adhesive layer 160.

[0181] Figure 7F The diagram shows a vertical cross-sectional view of an intermediate structure, according to one or more embodiments, on which a package cap 130 may be attached (e.g., mounted) onto a package substrate 110. In at least one embodiment, the package substrate 110, having an intermediate module 120, may be placed on a surface. The package cap 130 may then be positioned over the package substrate 110, for example, by an electromechanical pick-and-place (PNP) machine. The package cap 130 may then be lowered and placed over the intermediate module 120 onto the package substrate 110. The foot portion 130a of the package cap 130 may then be aligned with an adhesive layer 160 formed on the package substrate 110.

[0182] The encapsulation cap 130 can then be pressed down onto the TIM layer 170. By applying downward pressure to the encapsulation cap 130, the foot portion 130a of the encapsulation cap 130 can be attached to the encapsulation substrate 110 through the adhesive layer 160. In at least one embodiment, the pressure may cause the encapsulation cap portion 130p to compress the TIM layer 170. The encapsulation cap 130 can then be clamped onto the encapsulation substrate 110 for a sufficient time to allow the adhesive layer 160 to cure and form a strong bond between the encapsulation substrate 110 and the encapsulation cap 130. In at least one embodiment, the adhesive layer 160 is a fast-curing adhesive that can be cured by exposure to ultraviolet (UV) light.

[0183] Clamping the package cap 130 onto the package substrate 110 can, for example, be performed additionally or alternatively using a thermal clamping module. The thermal clamping module can apply a uniform force to the upper surface of the package cap 130. In one or more embodiments, the thermal clamping module can apply pressure to the package cap 130. For example, the adhesive layer 160 can be additionally or alternatively cured in a box oven to provide sufficient rigidity and mechanical strength to the adhesive layer 160.

[0184] Figure 7G This diagram shows a vertical cross-sectional view of an intermediate structure in which a plurality of solder balls 110c are formed on a package substrate 110 according to one or more embodiments. The plurality of solder balls 110c are permeable through an opening O in the passivation layer 110b beneath the package substrate. 110b Formed on the lower pad 116a of the package substrate (see Figure 7A Solder balls 110c can be formed by, for example, an electroplating process. Other methods for forming solder balls 110c are also included within the intended scope of disclosure. For example, the solder balls 110c can be formed below the lead portion 130a and below and between the intermediate module 120. A plurality of solder balls 110c can constitute a ball grid array (BGA), which allows the package structure 100 to be securely mounted on and electrically coupled to a substrate such as a printed circuit board by surface mount technology (SMT).

[0185] At this point, one or more selected integrated passive components (IPDs) (e.g., passive components) (not shown) may be mounted on the board-side surface of the package substrate 110. The selected IPDs may be mounted using a mounting process similar to that described above for SMD applications. Specifically, the mounting process may include a solder reflow process to electrically couple the IPDs to the package substrate 110. After the selected IPDs are mounted on the package substrate 110, additional processes may be used to clean the package substrate 110 and maintain its surface. These processes may include, for example, flux cleaning, pre-baking, and plasma processes. An IPD underfill layer (e.g., a passive component underfill layer) may then be applied to and around the package substrate 110 and the IPDs. The IPD underfill layer may include a material substantially the same as that used for the package underfill layer 129. The IPD underfill layer may also be applied and cured in a manner substantially similar to that described above for applying and curing the package underfill layer 129.

[0186] After the selective IPD underfill layer has cured, one or more processes can be performed before final testing. These processes may include, for example, one or more inspections, such as inspections by optical inspection systems (e.g., ICOS, HEXA, etc.) and a final visual inspection. These inspections can provide a plausibility check on the completed package structure 100 (e.g., checking z-height, package appearance, etc.). The final testing process can then be performed on the package structure 100.

[0187] Reference Figures 1A to 7GThe intermediary module 120 may include an intermediary 10, a semiconductor die 140 located on the intermediary 10, and a plurality of interconnect structures 128 connecting the intermediary 10 and the semiconductor die 140. The plurality of interconnect structures 128 may include a first interconnect portion 128a having a first alloy barrier layer 128a2, a second interconnect portion 128b having a second alloy barrier layer 128b2, and a solder joint 128c connecting the first interconnect portion 128a and the second interconnect portion 128b.

[0188] In one embodiment, each of the first alloy barrier layer 128a2 and the second alloy barrier layer 128b2 may include one of an iron-based binary alloy or a tungsten-based binary alloy. In one embodiment, the iron-based binary alloy may include iron ranging from 50 wt% to 90 wt%, and the tungsten-based binary alloy may include tungsten ranging from 40 wt% to 50 wt%. In one embodiment, the iron-based binary alloy may include one of FeNi or FeCo, and the tungsten-based binary alloy may include one of NiW or CoW. In one embodiment, each of the first alloy barrier layer 128a2 and the second alloy barrier layer 128b2 may include a thickness ranging from 1 μm to 5 μm. In one embodiment, the spacing P between the plurality of interconnect structures 128 iThe thickness can be 40 μm or smaller. In one embodiment, the first interconnect portion 128a may further include a first outer metal layer 128a1 and a first inner metal layer 128a3, and a first alloy barrier layer 128a2 may be located between the first outer metal layer 128a1 and the first inner metal layer 128a3. The second interconnect portion 128b may further include a second outer metal layer 128b1 and a second inner metal layer 128b3, and a second alloy barrier layer 128b2 may be located between the second outer metal layer 128b1 and the second inner metal layer 128b3. In one embodiment, the first alloy barrier layer 128a2 may contact the solder joint 128c, and the second alloy barrier layer 128b2 may contact the solder joint 128c. In one embodiment, the intermediary module 120 may further include a first intermetallic compound (IMC) layer 129a located on the intermediary side of the solder joint 128c, and a second IMC layer 129b located on the semiconductor die side of the solder joint 128c. In one embodiment, the total thickness of the second IMC layer 129b and the first IMC layer 129a may be less than or equal to about 10% of the thickness of the solder joint 128c. In one embodiment, the wetting length of the solder on the sidewall of the first alloy barrier layer 128a2 may be less than or equal to about 10% of the thickness of the first alloy barrier layer 128a2, and the wetting length of the solder on the sidewall of the second alloy barrier layer 128b2 may be less than or equal to about 10% of the thickness of the second alloy barrier layer 128b2. In one embodiment, the first interconnect portion 128a further includes a first outer metal layer 128a1, and the first alloy barrier layer 128a2 is contactable between the first outer metal layer 128a1 and the solder joint 128c, and the second interconnect portion 128b further includes a second outer metal layer 128b1, and the second alloy barrier layer 128b2 is contactable between the second outer metal layer 128b1 and the solder joint 128c. In one embodiment, the intermediary 10 may include an intermediary pad 16, the semiconductor die 140 may include a semiconductor die pad 146, and the interconnect structures 128 of the plurality of interconnect structures 128 may connect the intermediary pad 16 to the semiconductor die pad 146. In one embodiment, the intermediary 10 may further include a first seed layer 17 located on the intermediary pad 16, and a first alloy barrier layer 128a2 may contact the first seed layer 17 and the solder joint 128c, and the semiconductor die 140 may further include a second seed layer 147 located on the semiconductor die pad 146, and a second alloy barrier layer 128b2 may contact the second seed layer 147 and the solder joint 128c.

[0189] Refer again Figures 1A to 7GThe method of forming the intermediate module 120 may include forming a plurality of first bumps 128aB on the intermediate 10, wherein the plurality of first bumps 128aB may include a first alloy barrier layer 128a2 and a first bump solder layer 128ca; forming a plurality of second bumps 128bB on the semiconductor die 140, wherein the plurality of second bumps 128bB may include a second alloy barrier layer 128b2 and a second bump solder layer 128cb; positioning the semiconductor die 140 on the intermediate 10 such that the second bump solder layer 128cb is adjacent to the first bump solder layer 128ca; and forming a plurality of interconnect structures 128 connecting the intermediate 10 and the semiconductor die 140 by melting the second bump solder layer 128cb and the first bump solder layer 128ca to form a solder joint 128c.

[0190] In one embodiment, forming a plurality of first bumps 128aB may include forming a first outer metal layer 128a1, forming a first alloy barrier layer 128a2 on the first outer metal layer 128a1, forming a first inner metal layer 128a3 on the first alloy barrier layer 128a2, and forming a first bump solder layer 128ca on the first inner metal layer 128a3. In one embodiment, forming a plurality of second bumps 128bB may include forming a second outer metal layer 128b1, forming a second alloy barrier layer 128b2 on the second outer metal layer 128b1, forming a second inner metal layer 128b3 on the second alloy barrier layer 128b2, and forming a second bump solder layer 128cb on the second inner metal layer 128b3. In one embodiment, forming the first alloy barrier layer 128a2 may include forming the first alloy barrier layer 128a2 having a thickness ranging from 1 μm to 5 μm, and forming the second alloy barrier layer 128b2 may include forming the second alloy barrier layer 128b2 having a thickness ranging from 1 μm to 5 μm. In one embodiment, forming a plurality of first bumps 128aB may include forming a plurality of first bumps 128aB having a spacing P of 40 μm or less. i The formation of a plurality of second bumps 128bB may include forming a plurality of second bumps 128bB having a spacing P of 40 μm or less. i .

[0191] Refer again Figures 1A to 7GThe package structure 100 may include a package substrate and an intermediary module 120 located on the package substrate 110, including an intermediary 10, a semiconductor die 140 located on the intermediary 10, and a plurality of interconnect structures 128 connecting the intermediary 10 and the semiconductor die 140, and including a solder joint 128c and a pair of alloy barrier layers 128a2 and 128b2 located on opposite sides of the solder joint 128c. The package structure 100 may also include a thermal interface material (TIM) layer 170 located on the intermediary module 120, and a package cover portion 130p located on the TIM layer 170, and a package cover 130 protruding from the package cover portion 130p and connected to a package cover foot portion 130a of the package substrate 110.

[0192] The foregoing has outlined features of several embodiments to enable those skilled in the art to better understand the nature of this disclosure. Those skilled in the art should understand that they can readily use this disclosure as a basis for designing or modifying other processes and structures to achieve the same purposes or attain the same advantages as the embodiments described herein. Those skilled in the art should also recognize that these equivalent constructions do not depart from the spirit and scope of this disclosure, and that various changes, substitutions, and modifications can be made herein without departing from the spirit and scope of this disclosure.

Claims

1. A mediator module, characterized in that, include: Intermediary; A semiconductor die is located on the intermediate material; as well as Multiple interconnect structures connect the intermediate to the semiconductor die, wherein the multiple interconnect structures include: The first internal interconnect portion includes a first alloy barrier layer; The second interconnect portion includes a second alloy barrier layer; and The welding joint connects the first internal wiring portion to the second internal wiring portion.

2. The intermediary module according to claim 1, characterized in that, The first alloy barrier layer and the second alloy barrier layer have a thickness of 1 μm to 5 μm.

3. The intermediary module according to claim 1, characterized in that, The spacing between the multiple interconnect structures is 40 μm or less.

4. The intermediary module according to claim 1, characterized in that, The first interconnect portion further includes a first outer metal layer and a first inner metal layer, and the first alloy barrier layer is located between the first outer metal layer and the first inner metal layer. The second interconnect portion further includes a second outer metal layer and a second inner metal layer, and the second alloy barrier layer is located between the second outer metal layer and the second inner metal layer.

5. The intermediary module according to claim 1, characterized in that, The first alloy barrier layer contacts the weld joint, and the second alloy barrier layer contacts the weld joint.

6. The intermediary module according to claim 5, characterized in that, Also includes: A first intermetallic compound layer is located on the intermediary side of the weld joint; as well as A second intermetallic compound layer is located on the semiconductor die side of the weld joint.

7. The intermediary module according to claim 6, characterized in that, The total thickness of the second intermetallic compound layer and the first intermetallic compound layer is less than or equal to 10% of the thickness of the weld joint.

8. The intermediary module according to claim 5, characterized in that, The solder wetting length on the sidewall of the first alloy barrier layer is less than or equal to 10% of the thickness of the first alloy barrier layer, and the solder wetting length on the sidewall of the second alloy barrier layer is less than or equal to 10% of the thickness of the second alloy barrier layer.

9. A packaging structure, characterized in that, include: Packaging substrate; as well as Intermediate module, disposed on the packaging substrate, includes: Intermediary; Semiconductor die, located on the intermediate; and Multiple interconnect structures connect the intermediary to the semiconductor die, and include solder joints and a pair of alloy barrier layers on opposite sides of the solder joints.

10. The packaging structure according to claim 9, characterized in that, Also includes: A thermal interface material layer is applied to the intermediate module; as well as The encapsulation cover includes: The encapsulation cover portion is located on the thermal interface material layer; as well as The package cover portion protrudes from the package cover portion and is connected to the package substrate.

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