A power mosfet wide soa structure layout and mosfet

Abstract

The application provides a power MOSFET wide SOA structure layout and a MOSFET. The application sets a reverse layout area on the layout, the reverse layout area can prevent a formation of an injection area below a well area in a region where the reverse layout area is located, an appropriate threshold voltage value is obtained by increasing the injection area, and the overcurrent capacity of the SOA is improved by nearly 2-3 times.

Description

Technical Field

[0001] The embodiments of this application belong to the field of semiconductor technology, and in particular relate to a power MOSFET wide SOA structure layout and MOSFET. Background Technology

[0002] Power MOSFETs, with their advantages of small size, fast switching speed, and low power consumption, are widely used in communications, industrial automation, transportation, and consumer electronics. With the continuous development of the modern communications industry, electronic systems often require hot-swappable functionality. The key to achieving hot-swappable technology lies in the sufficiently wide safe operating area (SOA) of the power MOSFET. However, as power MOSFETs continuously strive for lower characteristic on-resistance (Ron, sp), their chip area is constantly shrinking, inevitably leading to a shrinking SOA. Therefore, designing MOSFET devices with a wider safe operating area is of great significance. Summary of the Invention

[0003] In order to solve or alleviate the problems in the prior art, in a first aspect, this application provides a power MOSFET wide SOA structure layout, including multiple first source contact hole mask areas and multiple trench mask areas;

[0004] The first source contact hole mask area is spaced apart between the trench mask areas;

[0005] The first source contact hole mask area is used to form the first source contact hole to bring out the source electrode, and the trench mask area is used to form a trench in the trench mask area and fill the trench with gate polysilicon and source polysilicon from top to bottom.

[0006] A corresponding first reverse area is provided in part of the first source contact hole mask area. The first reverse area is used to prevent the formation of an injection area below the well area in the area where the first reverse area is located.

[0007] As a preferred embodiment of this application, it also includes a second source contact hole mask area;

[0008] The second source contact hole mask area is disposed in the trench corresponding to the second trench mask area. The second source contact hole mask area is used to form the second source contact hole. The source polysilicon in the trench corresponding to the third trench mask area is led out through the second source contact hole. The second source contact holes in the trenches corresponding to adjacent second trench mask areas are arranged intersectingly. The second source contact hole mask area and the second trench mask area are provided with a second reflection area. The second reflection area is used to prevent the formation of an injection area below the well area in the region where the second reflection area is located.

[0009] As a preferred embodiment of this application, it also includes a gate contact hole mask area;

[0010] The gate contact hole mask area is disposed in the trench corresponding to the third trench mask area. The gate contact hole mask area is used to form gate contact holes. The gate polysilicon in the trench corresponding to the third trench mask area is led out through the gate contact holes. The gate contact holes in the trenches corresponding to adjacent third trench mask areas are arranged intersectingly. The gate contact hole mask area and the third trench mask area are provided with a third reverse area. The third reverse area is used to prevent the formation of an injection region below the well region in the area where the third reverse area is located.

[0011] As a preferred embodiment of this application, it also includes a terminal area;

[0012] The terminal area is located outside the cell area;

[0013] The terminal area is located outside the cell area;

[0014] A fourth reverse printing area is provided below the well area in the region where the terminal area is located. The fourth reverse printing area is used to prevent the formation of an injection area below the well area in the region where the fourth reverse printing area is located.

[0015] Secondly, embodiments of this application also provide a MOSFET fabricated using the layout described in any one of the first aspects.

[0016] Compared with the prior art, this application sets a reverse area on the layout, which can prevent the formation of an injection area below the well area where the reverse area is located. By increasing the injection area, an appropriate threshold voltage value can be obtained, and the overcurrent capability of SOA can be improved by nearly 2-3 times. Attached Figure Description

[0017] The accompanying drawings, which are included to provide a further understanding of this application and form part of this application, illustrate exemplary embodiments and are used to explain this application, but do not constitute an undue limitation of this application. Some specific embodiments of this application will be described in detail below with reference to the accompanying drawings in an exemplary and non-limiting manner. The same reference numerals in the drawings designate the same or similar parts or components. Those skilled in the art should understand that these drawings are not necessarily drawn to scale. In the drawings:

[0018] Figure 1 This application provides a power MOSFET wide SOA structure layout.

[0019] Figure 2 This application provides another power MOSFET wide SOA structure layout. Detailed Implementation

[0020] To enable those skilled in the art to better understand the present application, the technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are merely some, not all, of the embodiments of the present application. All other embodiments obtained by those skilled in the art based on the embodiments of the present application without creative effort should fall within the scope of protection of the present application.

[0021] like Figure 1 As shown, in a first aspect, this application provides a power MOSFET wide SOA structure layout, with multiple first contact hole mask areas 2 and multiple trench mask areas 1, wherein the first source contact hole mask areas 2 are disposed between the first trench mask areas 1;

[0022] The first contact hole mask area 2 and the first trench mask area 1 are alternately arranged;

[0023] The first contact hole mask area 2 is used to form source contact holes to bring out the source electrode, and the first trench mask area 1 is used to form trenches in the trench mask area 1 and fill the trenches from top to bottom with gate polysilicon and source polysilicon;

[0024] A corresponding first reverse area 3 is provided in part of the first source contact hole mask plate area 2. The first reverse area 3 is used to prevent the formation of an injection area below the well area in the area where the first reverse area 3 is located.

[0025] It should be noted that, Figure 1 The diagram only shows a portion of the source region (partial cell region), but does not show the layout of the gate region, the termination region, and other source regions.

[0026] This application sets up a reverse area on the layout, which can prevent the formation of an injection region below the well region in the reverse area. By increasing the injection region, an appropriate threshold voltage value can be obtained, and the overcurrent capability of SOA can be improved by nearly 2-3 times.

[0027] like Figure 2 As shown, it also includes a second source contact hole mask area 4 and a gate contact hole mask area 6;

[0028] The second source contact hole mask area 4 is disposed in the trench corresponding to the second trench mask area 5. The second source contact hole mask area 4 is used to form the second source contact hole. The source polysilicon in the trench corresponding to the second trench mask area 5 is led out through the second source contact hole.

[0029] The second source contact holes in the trenches corresponding to adjacent second trench mask areas 5 are arranged in an intersecting manner; the areas corresponding to the second source contact hole mask area 4 and the third trench mask area 5 are provided with a second reverse area 8, which is used to prevent the injection area from forming below the well area of ​​the second reverse area.

[0030] The gate contact hole mask area 6 is disposed in the trench corresponding to the third trench mask area 7. The gate contact hole mask area 6 is used to form a gate contact hole. The gate polysilicon in the trench corresponding to the third trench mask area 7 is led out through the gate contact hole.

[0031] The gate contact holes in the trenches corresponding to adjacent third trench mask areas 7 are arranged in a cross pattern; a third reverse area 9 is provided in the area where the gate contact hole mask area 6 and the third trench mask area 7 are located, and the third reverse area 9 is used to prevent the injection area from forming below the well area of ​​the third reverse area.

[0032] Figure 2 The provided map also includes the terminal area;

[0033] The terminal area 10 is located around the cell area;

[0034] A fourth reverse printing area (not shown) is provided below the well area in the region where the terminal area 10 is located. The fourth reverse printing area (not shown) is used to prevent the formation of an injection area below the well area in the region where the fourth reverse printing area is located.

[0035] Secondly, embodiments of this application also provide a MOSFET fabricated using the layout described in any one of the first aspects.

[0036] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of this application, and are not intended to limit them. Although this application has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some or all of the technical features therein. Such modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of this application.

Claims

1. A power MOSFET wide SOA structure layout, characterized in that, Multiple first source contact hole mask areas and multiple trench mask areas; The first source contact hole mask area is spaced apart between the trench mask areas; The first source contact hole mask area is used to form the first source contact hole to bring out the source, and the trench mask area is used to form a trench in the trench mask area and fill the trench with gate polysilicon and source polysilicon from top to bottom; A corresponding first reverse area is provided in part of the first source contact hole mask area. The first reverse area is used to prevent the formation of an injection area below the well area in the area where the first reverse area is located.

2. The power MOSFET wide SOA structure layout as described in claim 1, characterized in that, It also includes the second source contact hole mask area; The second source contact hole mask area is disposed in the trench corresponding to the second trench mask area. The second source contact hole mask area is used to form the second source contact hole. The source polysilicon in the trench corresponding to the third trench mask area is led out through the second source contact hole. The second source contact holes in the trenches corresponding to adjacent second trench mask areas are arranged in an intersecting manner. The second source contact hole mask area and the second trench mask area are provided with a second reverse area. The second reverse area is used to prevent the formation of an injection area below the well area in the region where the second reverse area is located.

3. The power MOSFET wide SOA structure layout as described in claim 1, characterized in that, It also includes the gate contact hole mask area; The gate contact hole mask area is disposed in the trench corresponding to the third trench mask area. The gate contact hole mask area is used to form a gate contact hole. The gate polysilicon in the trench corresponding to the third trench mask area is led out through the gate contact hole. The gate contact holes in the trenches corresponding to adjacent third trench mask areas are arranged in an intersecting manner. The gate contact hole mask area and the third trench mask area are provided with a third reverse area. The third reverse area is used to prevent the formation of an injection region below the well region in the area where the third reverse area is located.

4. The power MOSFET wide SOA structure layout as described in claim 3, characterized in that, It also includes the terminal area; The terminal area is located outside the cell area; A fourth reverse printing area is provided below the well area in the region where the terminal area is located. The fourth reverse printing area is used to prevent the formation of an injection area below the well area in the region where the fourth reverse printing area is located.

5. A MOSFET, characterized in that, The layout is prepared according to any one of claims 1 to 4.

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