A planar probe test structure

By using a planar probe made of a graphite and metal mixture, the problems of chip surface contamination and high-temperature damage caused by existing probes in the testing of third-generation semiconductor materials have been solved, achieving stability and efficiency in high-current testing and improving product quality and yield.

CN224436406UActive Publication Date: 2026-06-30POWERTECH CO LTD
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Patent Information

Authority / Receiving Office
CN · China
Patent Type
Utility models(China)
Current Assignee / Owner
POWERTECH CO LTD
Filing Date
2025-06-30
Publication Date
2026-06-30

AI Technical Summary

Technical Problem

Existing probe structures cannot meet the high-current testing requirements when testing wafers or KGD chips of third-generation semiconductor materials. They are prone to contamination of the chip surface material, resulting in scratches and pin marks, and may cause high-temperature accumulation that damages the chip structure.

Method used

The planar probe, made of a mixture of graphite and metal, has a smooth surface, which increases the contact area, reduces pressure, and prevents surface damage. At the same time, the high thermal conductivity and high melting point of graphite ensure test stability and high temperature resistance.

Benefits of technology

It improves product quality and yield, reduces testing costs, extends probe lifespan, avoids chip surface scratches and high-temperature damage, and meets the testing requirements of high-requirement products such as SiC MOSFET, SiMOSFET, and IGBT.

✦ Generated by Eureka AI based on patent content.

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Abstract

This utility model relates to the field of semiconductor technology and discloses a planar probe test structure for testing a structure under test. A first test electrode is disposed on a first surface of the structure under test. The planar probe test structure includes a first test probe, which has a planar detection surface adapted to contact and connect with the first test electrode of the structure under test for testing. Compared with related technologies, this utility model increases the contact area between the first test probe and the first test electrode through the planar detection surface, reducing damage to the surface of the structure under test, thereby improving the product quality and yield of the structure under test. It also extends the service life of the first test probe and reduces the cost of the test structure.
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