Semiconductor devices and pixel arrays

Abstract

Some embodiments of this disclosure provide a semiconductor device and a pixel array. The semiconductor device includes a photodetector located in a substrate having a front side and a back side, a vertical transmission gate located on the front side of the substrate, a first deep trench isolation feature disposed in the substrate and located on one side of the photodetector, an epitaxial layer disposed in the substrate above the first deep trench isolation feature and located on the first side of the vertical transmission gate, and a p-type well disposed in the substrate and located around the epitaxial layer.

Description

Technical Field

[0001] This disclosure relates to semiconductor devices, and more particularly to pixel arrays of image sensor semiconductor devices. Background Technology

[0002] Semiconductor devices are used in a variety of electronic applications, such as personal computers, mobile phones, digital cameras, and other electronic devices. The fabrication of semiconductor devices typically involves depositing insulating or dielectric layers, conductive layers, and semiconductor layers sequentially on a semiconductor substrate, and using lithography to pattern the multiple material layers to form circuit components and elements on the semiconductor substrate.

[0003] The semiconductor industry continues to improve the integration density of various electronic components (such as transistors, diodes, resistors, capacitors, etc.) by continuously shrinking the minimum feature size, thereby allowing more components to be integrated into a given area. However, as the minimum feature size shrinks, additional problems also arise that need to be addressed. Utility Model Content

[0004] According to some embodiments of the present disclosure, a semiconductor device includes a photodetector in a substrate having a front side and a back side, a vertical transfer gate located on the front side of the substrate, a first deep trench isolation feature disposed in the substrate and located on one side of the photodetector, an epitaxial layer in the substrate disposed above the first deep trench isolation feature and located on the first side of the vertical transfer gate, and a p-type well disposed in the substrate and located around the epitaxial layer.

[0005] According to some embodiments of the present disclosure, a semiconductor device includes a substrate having a front side and a back side, a groove located in the substrate and extending from the front side of the substrate to an interior region of the substrate, a high-dielectric-constant dielectric layer located in the groove, an epitaxially grown silicon region located above the high-dielectric-constant dielectric layer in the groove and on the front side of the substrate, and a complementary metal-oxide-semiconductor image sensor device located on the front side of the substrate.

[0006] According to some embodiments of the present disclosure, a pixel array includes a substrate having a front side and a back side, a front deep trench isolation feature located in the front side of the substrate, an epitaxial layer located above the front deep trench isolation feature, and a first pixel region, wherein the first pixel region includes a first photodetector located in the substrate and on one side of the front deep trench isolation feature, a first vertical transfer gate located in the substrate and above the first photodetector, a first floating diffusion region located in the substrate and above the epitaxial layer, and a first p-type well located in the substrate and around the epitaxial layer. Attached Figure Description

[0007] The various aspects of this disclosure can be best understood from the following detailed description when read in conjunction with the accompanying drawings. It should be noted that, in accordance with standard industrial methods, the various features are not drawn to scale. In fact, the dimensions of the various features may be arbitrarily increased or decreased for clarity of discussion.

[0008] Figure 1A A plan view or layout diagram of a complementary metal-oxide-semiconductor image sensor is shown according to some embodiments;

[0009] Figure 1B A schematic cross-sectional view of the pixel region of a complementary metal-oxide-semiconductor image sensor is shown according to some embodiments;

[0010] Figure 2 A schematic cross-sectional view of an example sub-pixel region of a back-illuminated stacked sensor with inter-pixel isolation and inter-node isolation is shown according to some embodiments;

[0011] Figure 3 An example method flowchart for manufacturing a complementary metal-oxide-semiconductor image sensor device is illustrated according to some embodiments;

[0012] Figures 4 to 21 Schematic cross-sectional views of an example complementary metal-oxide-semiconductor image sensor device at various manufacturing stages are illustrated according to some embodiments.

[0013] Figure 22 A schematic cross-sectional view of an example subpixel region is illustrated according to some embodiments, wherein the example subpixel region is formed using a front deep trench isolation feature and a back deep trench isolation feature;

[0014] Figure 23 A schematic cross-sectional view of an example subpixel region is illustrated according to some embodiments, wherein the example subpixel region is formed using a front deep trench isolation feature and a back deep trench isolation feature;

[0015] Figure 24 A schematic cross-sectional view of an example subpixel region is illustrated according to some embodiments, wherein the example subpixel region is formed using a front deep trench isolation feature and a back deep trench isolation feature;

[0016] Figure 25 A schematic cross-sectional view of an example size in an example subpixel region is shown according to some embodiments, wherein the example subpixel region is formed using a front deep trench isolation feature;

[0017] Figure 26 A schematic cross-sectional view of an example size in an example subpixel region is shown according to some embodiments, wherein the example subpixel region is formed using a first back-side deep trench isolation feature and a second back-side deep trench isolation feature;

[0018] Figure 27 A schematic top view of pixels is shown according to some embodiments;

[0019] Figure 28 A schematic top view of the first pixel and the second pixel is shown according to some embodiments.

[0020] [Symbol Explanation]

[0021] 100: Complementary Metal-Oxide-Semiconductor Image Sensor

[0022] 102: Pixel area

[0023] 102U: Unit Pixel

[0024] 104: Optical isolation area

[0025] 106: Physically isolated area

[0026] 108: Pad Electrode

[0027] 110: Black level correction area

[0028] 112: Photodiode layer

[0029] 114: Semiconductor substrate

[0030] 116: First Surface

[0031] 118: Second Surface

[0032] 120: Color Filter

[0033] 122: Microlens

[0034] 124: Inner Dielectric Liner

[0035] 126: First isolation structure

[0036] 128: Second isolation structure

[0037] 130: Dielectric materials

[0038] 132: Transmission Gate

[0039] 134: Third isolation structure

[0040] 150: Subpixel region

[0041] 152: Vertical Transfer Gate

[0042] 154: Light Detector

[0043] 156:Substrate

[0044] 158: Front

[0045] 160: Dorsal side

[0046] 162: Front deep trench isolation feature

[0047] 164: Epitaxial silicon growth region

[0048] 166: p-type trap

[0049] 168:n+ doped region

[0050] 170: Floating diffusion region

[0051] 172: Pad oxide layer

[0052] 174: Gate spacer

[0053] 200: Method

[0054] 210,220,222,224,226,230,232,233,234,235,236,237,240,242,244,250,260,262,264,266,268,270: Step 301: First side

[0055] 302:Substrate

[0056] 303: Second side

[0057] 304: Sacrificial oxide layer

[0058] 306: Hard mask

[0059] 308: Groove

[0060] 310: Lining

[0061] 312: High aspect ratio process oxide

[0062] 314: Pre-determined distance

[0063] 318: Epitaxial silicon growth region

[0064] 320: Sacrifice Structure

[0065] 321: CIS device

[0066] 322: p-type trap

[0067] 324: n+ doped region

[0068] 326: Pad oxide layer

[0069] 328: Gate polysilicon region

[0070] 330: Interconnection Structure

[0071] 332: Groove

[0072] 334: High dielectric constant dielectric layer

[0073] 336: Front deep trench isolation feature

[0074] 338: Gate spacer

[0075] 340: Light Detector

[0076] 342: Sub-pixel region

[0077] 400: Subpixel region

[0078] 402: Front deep trench isolation feature

[0079] 404: Deep trench isolation feature on the dorsal side

[0080] 406: Characteristics of epitaxial silicon growth

[0081] 408: Vertical Transfer Gate

[0082] 410: Light Detector

[0083] 412: Gate spacer

[0084] 414: p-type trap

[0085] 416: n+ doped region

[0086] 418: Shallow trench isolation features

[0087] 420: p-type trap

[0088] 500: Subpixel region

[0089] 502: Front deep trench isolation feature

[0090] 504: Deep trench isolation features on the dorsal side

[0091] 506: Characteristics of epitaxial silicon growth

[0092] 508: Vertical Transfer Gate

[0093] 510: Light Detector

[0094] 512: Gate spacer

[0095] 514: p-type trap

[0096] 516:n+ doped region

[0097] 518: Shallow trench isolation features

[0098] 520: p-type trap

[0099] 600: Subpixel region

[0100] 602: Front deep trench isolation feature

[0101] 604: Deep trench isolation features on the dorsal side

[0102] 606: Characteristics of epitaxial silicon growth

[0103] 608: Vertical Transfer Gate

[0104] 610: Light Detector

[0105] 612: Gate spacer

[0106] 614: p-type trap

[0107] 616:n+ doped region

[0108] 618: Shallow trench isolation features

[0109] 620: p-type trap

[0110] 700: Subpixel region

[0111] 702: Front deep trench isolation feature

[0112] 704: Depth

[0113] 706: Epitaxial silicon growth region

[0114] 708: Length

[0115] 710: Critical Size

[0116] 712: p-type trap

[0117] 714: Width

[0118] 800: Subpixel region

[0119] 802-1: First dorsal deep trench isolation feature

[0120] 802-2: Second dorsal deep trench isolation feature

[0121] 804-1, 804-2: Depth

[0122] 806: Shallow trench isolation features

[0123] 808: Length

[0124] 810: Critical Size

[0125] 812: p-type trap

[0126] 814: Width

[0127] 900:Substrate

[0128] 902: pixels

[0129] 902-1, 902-2, 902-3, 902-4: Subpixels

[0130] 904: Floating Diffusion Region

[0131] 906: Source Follows Gate

[0132] 908: Column Select Gate

[0133] 910: Reset Gate

[0134] 940:Substrate

[0135] 952: First pixel

[0136] 952-1, 952-2, 952-3, 952-4: Subpixels

[0137] 954: Floating Diffusion Region

[0138] 956: Source Follows Gate

[0139] 958: Column Select Gate

[0140] 960: Reset Gate

[0141] 972: Second pixel

[0142] 972-1, 972-2, 972-3, 972-4: Subpixels

[0143] 974: Floating Diffusion Region

[0144] 976: Reset Gate

[0145] BDTI: Deep Trench Isolation

[0146] EPI: Epitaxial Growth

[0147] FD: Floating Diffusion

[0148] FDTI: Front Deep Trench Isolation

[0149] N+: n-type doping

[0150] LL′: Tangent

[0151] PD: Light Detector

[0152] PW: p-type well

[0153] RS: Column Selection

[0154] RST: Reset

[0155] SF: Source of Pursuit

[0156] STI: Shallow Trench Isolation

[0157] TX: Transmission Gate Detailed Implementation

[0158] To achieve the different features of the mentioned subject matter, the following disclosure provides many different embodiments or examples. Specific examples of components, configurations, etc., are described below to simplify this disclosure. Of course, these are merely examples and not limiting.

[0159] For the sake of brevity, the known techniques associated with the manufacture of conventional semiconductor devices may not be described in detail herein. Furthermore, the various tasks and processes described herein can be incorporated into more comprehensive procedures or processes with additional functionality not described in detail herein. Specifically, the various processes for manufacturing semiconductor devices are well known; therefore, for the sake of brevity, many known processes will only be briefly mentioned herein or will be completely omitted without providing details of the well-known processes. As will be readily apparent to those skilled in the art upon a full reading of this disclosure, the structures disclosed herein can be used with various techniques and incorporated into various semiconductor devices and products. Additionally, it should be noted that semiconductor device structures include different numbers of elements, and a single element shown in the description may represent multiple elements.

[0160] Furthermore, this document may use spatial relative terms such as “above,” “overlapping,” “above,” “upper,” “top,” “top,” “below,” “under,” “below,” “lower,” “bottom,” and similar terms to describe the relationship of one element or feature to another element or feature as shown in the figure. In addition to the orientations shown in the figure, spatial relative terms are intended to include different orientations of the device in use or operation. The device may be oriented in other ways (rotated 90 degrees or in other directions), and the spatial relative descriptive symbols used herein may be interpreted accordingly. When using spatial relative terms such as those listed above to describe the relationship of a first component relative to a second component, the first component may be directly on top of the other component, or there may be intermediate components or layers present.

[0161] Additionally, reference numerals and / or letters may be repeated in various examples within this disclosure. This repetition is for simplicity and clarity and does not in itself imply a relationship between the various embodiments and / or configurations discussed.

[0162] It should be noted that the description of an embodiment, such as "an embodiment," "an example embodiment," "exemplary embodiment," "model," or "example," indicates that the described embodiment may include a specific feature, structure, or characteristic, but not every embodiment necessarily includes that specific feature, structure, or characteristic. Furthermore, such phrases do not necessarily refer to the same embodiment. Additionally, when a specific feature, structure, or characteristic is described in connection with an embodiment, whether explicitly described or not, incorporating other embodiments to affect that feature, structure, or characteristic is within the knowledge of those skilled in the art.

[0163] It should be understood that the wording or terminology used herein is for descriptive purposes and not for limiting purposes, and that the terminology or terminology used herein shall be interpreted by one skilled in the art in light of the teachings herein.

[0164] To achieve the various features of the mentioned subject matter, the following disclosure provides numerous different embodiments or examples. Specific examples of components, configurations, etc., are described below to simplify this disclosure. Of course, these are merely examples and not limiting. For example, in the following description, forming a first feature on or over a second feature may include embodiments where the first and second features are formed in direct contact, and may also include embodiments where an additional feature is formed between the first and second features such that the first and second features do not need to be in direct contact. Throughout this description, unless otherwise specifically stated, the same reference numerals in the different figures represent the same or similar components formed using the same or similar materials and in the same or similar methods.

[0165] It should be understood that although the terms "first," "second," "third," etc., may be used herein to describe various elements, components, regions, layers, parts, and / or sections, these elements, components, regions, layers, parts, and / or sections should not be limited by these terms. These terms are used only to distinguish one element, component, region, layer, part, or section from another. Unless expressly stated in the text, the use of terms such as "first," "second," and "third" herein does not imply any order or sequence.

[0166] In this document, the terms “approximately,” “substantially,” “substantial,” and “about” are used to describe and indicate small errors. When used in conjunction with an event or condition, these terms can represent instances of the event or condition being exact or approximate. For example, when used in conjunction with a numerical value, these terms can represent an error range less than or equal to ±10% of the stated numerical value, such as less than or equal to ±5%, less than or equal to ±4%, less than or equal to ±3%, less than or equal to ±2%, less than or equal to ±1%, less than or equal to ±0.5%, less than or equal to ±0.1%, or less than or equal to ±0.05%. For example, if the difference between two values ​​is less than or equal to ±10% of the average of the values, such as less than or equal to ±5%, less than or equal to ±4%, less than or equal to ±3%, less than or equal to ±2%, less than or equal to ±1%, less than or equal to ±0.5%, less than or equal to ±0.1%, or less than or equal to ±0.05%, the two values ​​can be considered "substantially" the same or equal. For example, "substantially" parallel can mean an angular error range of less than or equal to ±10° relative to 0°, such as less than or equal to ±5°, less than or equal to ±4°, less than or equal to ±3°, less than or equal to ±2°, less than or equal to ±1°, less than or equal to ±0.5°, less than or equal to ±0.1°, or less than or equal to ±0.05°. For example, “substantially” vertical can mean an angular error range of less than or equal to ±10° relative to 90°, such as less than or equal to ±5°, less than or equal to ±4°, less than or equal to ±3°, less than or equal to ±2°, less than or equal to ±1°, less than or equal to ±0.5°, less than or equal to ±0.1°, or less than or equal to ±0.05°.

[0167] Semiconductor image sensors are used to sense incident visible or invisible radiation, such as visible light and infrared light. Complementary metal-oxide-semiconductor (CMOS) image sensors (CIS) are used in a variety of applications, such as digital cameras, mobile phones, tablets, and eyepieces. These image sensors use pixel arrays, where pixels absorb (e.g., sense) incident radiation and convert it into electronic signals.

[0168] A backside illumination (BSI) image sensor is a type of CIS device. A BSI image sensor includes pixel regions having an array of pixels or radiation sensing regions formed on a substrate (e.g., a semiconductor substrate). In embodiments of this disclosure, the terms "radiation sensing region" and "pixel" may be used interchangeably. Pixels are configured to convert photons of incident radiation into electronic signals. These electronic signals are then distributed to processing components attached to the backside illumination image sensor. Therefore, the pixel regions are overlaid on interconnect structures in a multilevel metallization layer, wherein the multilevel metallization layer is configured to distribute the electronic signals generated in the pixels to appropriate processing components. The multilevel metallization layer is formed on a first surface of the substrate. The pixel regions are formed on a second surface of the substrate, wherein the second surface is relative to the first surface of the substrate. The pixel regions include a grid structure providing optical isolation between adjacent pixels. Furthermore, the pixel regions include a color filter layer. The material of the color filter layer is selected such that light with a desired wavelength passes through the color filter layer, while light with other wavelengths is absorbed by the color filter layer.

[0169] The challenge with small pixels lies in maintaining dynamic range (DR), signal-to-noise ratio (SNR), and sensitivity compatible with large-pixel sensors. According to some embodiments of this disclosure, to maximize dynamic range and minimize optical / electronic crosstalk with large full-well capacity (FWC), back-illuminated stacked sensors use front deep trench isolation (FDTI) for inter-pixel and inter-node isolation to reduce the size of consecutive pixels. According to some embodiments of this disclosure, using FDTI structures instead of shallow trench isolation structures for isolation simplifies fabrication. According to some embodiments of this disclosure, using FDTI structures with smaller critical dimensions (CD) instead of back deep trench isolation (BDTI) structures for isolation simplifies fabrication. According to some embodiments of this disclosure, using FDTI structures etched from both the front and back sides of the substrate. According to some embodiments of this disclosure, using a front-side deep trench isolation structure can improve the signal-to-noise ratio of a CIS sensor and reduce crosstalk.

[0170] According to some embodiments, Figure 1AA plan view or layout diagram of an example complementary metal-oxide-semiconductor (CMOS) image sensor 100 is shown. The example CMOS image sensor 100 includes a pixel region 102 and an optically isolated region 104 surrounding the pixel region 102, wherein a plurality of unit pixels in the pixel region 102 are arranged in a matrix. Furthermore, a physical isolation region 106 surrounds the optically isolated region 104. In some embodiments, the CMOS image sensor 100 includes a plurality of pad electrodes 108 for wiring to external circuitry. The example CMOS image sensor 100 further includes one or more black level calibration (BLC) regions 110 to block incident light and provide a reference dark voltage current.

[0171] According to some embodiments, Figure 1B The pixel region 102 of the complementary metal-oxide-semiconductor image sensor 100 is shown along... Figure 1A A cross-sectional view of the tangent LL′ in pixel region 102. Pixel region 102 includes a plurality of unit pixels 102U, each unit pixel 102U including a photodiode layer 112 formed in a semiconductor substrate 114 (e.g., a Si substrate) having a first surface 116 and an opposing second surface 118, a color filter 120 disposed above the second surface 118 and substantially aligned with the photodiode layer 112, and a microlens 122 disposed above the color filter 120 and aligned with the color filter 120. In some embodiments, an inner dielectric layer 124 is disposed between the color filter 120 and the microlens 122. The complementary metal-oxide-semiconductor image sensor 100 also includes a first isolation structure 126 to laterally separate adjacent color filters 120. An example complementary metal-oxide-semiconductor (CMOS) image sensor 100 includes a second isolation structure 128 disposed in a semiconductor substrate 114 to laterally separate an adjacent photodiode layer 112, wherein the second isolation structure 128 is a deep trench isolation structure filled with one or more dielectric materials 130. Additionally, the CMOS image sensor 100 includes a transfer gate 132 coupled to the photodiode layer 112 and disposed on a first surface 116 of the semiconductor substrate 114. In some embodiments, a third isolation structure 134 is disposed between the second isolation structure 128 and the first surface 116 and aligned with the second isolation structure 128 to serve as an electrical isolation structure, wherein the third isolation structure 134 is a doped region implanted with, for example, boron. In some embodiments, each unit pixel 102U is square or rectangular in plan view and is surrounded by the first isolation structure 126, the second isolation structure 128, and the third isolation structure 134.

[0172] Figure 2A schematic cross-sectional view of an example subpixel region 150 of a back-illuminated stacked sensor with inter-pixel and inter-node isolation is shown. In this example, subpixel region 150 includes a gate poly region for a vertical transfer gate (VTG) 152, wherein the vertical transfer gate 152 is disposed above a photodetector 154 in a substrate 156 having a front side 158 and a back side 160. The substrate 156 may be a semiconductor substrate, such as a bulk semiconductor, a semiconductor-on-insulator (SOI) substrate, a semiconductor wafer, or the like, and may be doped (e.g., having p-type or n-type dopants) or undoped. Other substrates, such as multilayer substrates or gradient substrates, may also be used. In some embodiments, the semiconductor material of the substrate may include silicon.

[0173] The sub-pixel region 150 further includes a front deep trench isolation feature 162 disposed in the substrate 156 and located on one side of the photodetector 154, an epitaxial silicon region 164 (e.g., an epitaxial layer) formed above the front deep trench isolation feature 162 and located on the first side of the vertical transfer gate 152 in the substrate 156, and a p-type well 166 disposed in the substrate 156 and located around the epitaxial silicon region 164. The sub-pixel region 150 also includes an n+ doped region 168 serving as a floating diffusion (FD) region 170, a pad oxide layer 172, and a gate spacer 174.

[0174] According to some embodiments, Figure 3 A flowchart illustrating an example method 200 for manufacturing a CIS device (e.g., subpixel region 150) is provided. For illustrative purposes, Figure 3 The steps shown in the diagram will be referenced. Figures 4 to 21 Describe, in which Figures 4 to 21 Cross-sectional views of a CIS device at various stages of the manufacturing process are shown according to some embodiments. Depending on the specific application, some steps may be performed in a different order or without performing others. It should be noted that method 200 may not produce a complete CIS device. Therefore, it should be understood that additional processes may be provided before, during, and after the method, and these additional processes may be described only briefly herein. In some figures, for ease of illustration, some reference numerals for components or features may be omitted to avoid obscuring other components or features.

[0175] Method 200 is merely an example and is not intended to limit the embodiments of this disclosure beyond those explicitly stated in the claims. Additional steps may be provided before, during, and after example method 200, and other embodiments of example method 200 may move, replace, or omit some of the stated steps. Additional features may be added to the semiconductor device in the drawings, and other embodiments of the semiconductor device may replace, modify, or omit some of the features described below.

[0176] It should be understood that some semiconductor devices can be manufactured using typical semiconductor technology processes, and therefore only some processes are described briefly herein. Furthermore, the example semiconductor device may include a variety of other devices and features, such as additional transistors, bipolar junction transistors, resistors, capacitors, inductors, diodes, fuses, and / or other logic devices, but the example semiconductor device is simplified to better understand the concepts of the embodiments of this disclosure. In some embodiments, the example device includes multiple interconnectable semiconductor devices (e.g., transistors), including p-type field-effect transistors (PFETs), n-type field-effect transistors (NFETs), etc. Additionally, it should be noted that the steps of method 200, including any description provided with reference to the accompanying drawings, are merely examples and are not intended to limit the scope beyond what is specifically described in the claims.

[0177] In step 210, method 200 includes providing a semiconductor substrate. (See reference...) Figure 4 For example, in one embodiment of step 210, a semiconductor substrate 302 is provided. The semiconductor substrate 302 includes a first side 301 and a second side 303 opposite to the first side 301. In some embodiments, the first side 301 may be defined as the front side of the semiconductor substrate 302, while the second side 303 may be defined as the back side of the semiconductor substrate 302.

[0178] In step 220, method 200 includes forming a groove in the front side of the substrate for a front-side deep trench isolation feature. In several embodiments, forming a groove in the front side of the substrate for a front-side deep trench isolation feature includes the operations described in steps 222, 224, and 226.

[0179] In step 222, method 200 includes forming a sacrificial (SAC) oxide layer over a first side 301 of the semiconductor substrate 302. (See reference...) Figure 5 For example, in one embodiment of step 222, a sacrificial oxide layer 304, such as a silicon oxide layer (e.g., SiO2), is formed over a first side 301 of the semiconductor substrate 302.

[0180] In step 224, method 200 includes forming a hard mask over the sacrificial oxide layer. (Reference) Figure 6 For example, in one embodiment of step 224, a hard mask 306 is formed over the sacrificial oxide layer 304.

[0181] In step 226, method 200 includes forming a groove extending from the first side 301 into the substrate 302. (See reference) Figure 7 For example, in one embodiment of step 226, a recess 308 is formed extending from the first side 301 into the substrate 302. In some embodiments, the recess 308 is formed using photolithography and etching techniques. As an example, a hard mask 306 may be patterned to expose a portion of the first side 301 of the semiconductor substrate 302. In some embodiments, the hard mask 306 may be a multilayer hard mask. As an example, the material of the hard mask 306 may include silicon nitride (SiN). The hard mask 306 is then used as an etching mask to etch the semiconductor substrate 302 from the first side 301 to form the recess 308.

[0182] In step 230, method 200 includes partially filling the groove using a sacrificial structure. In several embodiments, partially filling the groove using a sacrificial structure includes the operations described in steps 232, 233, 234, 235, 236, and 237.

[0183] In step 232, method 200 includes forming a liner 310 to cover the sidewalls and bottom of the recess 308. (See reference) Figure 8 For example, in one embodiment of step 232, a liner 310 is formed to cover the sidewalls and bottom of the recess 308. In some embodiments, a flowable dielectric material fills the recess 308 to form a flowable dielectric film. The flowable dielectric film may include a flowable silicon oxide material. In some embodiments, annealing is performed to convert the flowable dielectric film into the liner 310, wherein annealing may also improve the liner quality. In some embodiments, the material of the liner 310 may include SiO2.

[0184] In step 233, method 200 includes forming a high aspect ratio (HARP) oxide over the hard mask 306, over the liner 310, and in the recess 308. (Reference) Figure 9For example, in one embodiment of step 233, a high aspect ratio process oxide 312 is formed over the hard mask 306, over the liner 310, and in the recess 308. In some embodiments, the high aspect ratio process oxide 312 is formed by a single high aspect ratio process, or a high aspect ratio process combined with some high-density plasma (HDP) chemical vapor deposition (CVD) process or other chemical vapor deposition techniques. In some embodiments, the material of the high aspect ratio process oxide 312 may include SiO2.

[0185] In step 234, method 200 includes removing the high aspect ratio process oxide 312 over the hard mask 306. In one embodiment, a chemical mechanical polishing (CMP) operation is used to remove the high aspect ratio process oxide 312 over the hard mask 306. (See reference...) Figure 10 For example, in one embodiment of step 234, a chemical mechanical polishing operation is used to remove the high aspect ratio process oxide 312 above the hard mask 306.

[0186] In step 235, method 200 includes removing a high aspect ratio process oxide 312 from the recess 308 located a predetermined distance 314 below the hard mask 306 and above the top of the sacrificial oxide layer 304. (See reference) Figure 11 For example, in one embodiment of step 235, the high aspect ratio process oxide 312 (and liner 310) is removed from a predetermined distance 314 below the hard mask 306. In some embodiments, the high aspect ratio process oxide 312 from the predetermined distance 314 below the hard mask 306 is removed using a hydrogen fluoride (HF) wet cleaning process in a wet bench. In some embodiments, the predetermined distance is approximately 250 angstroms. ).

[0187] In step 236, method 200 includes removing the hard mask 306. In several embodiments, the hard mask 306 is removed using a wet etching step in a wet cleaning station, the etching process using an etchant such as an acidic solution comprising metaphosphoric acid (HPO3). Reference Figure 12 For example, in one embodiment of step 236, the hard mask 306 is removed.

[0188] In step 237, method 200 includes removing the sacrificial oxide layer 304 and etching the liner 310 and the high aspect ratio process oxide 312 back into the groove 308. (See reference) Figure 13For example, in one embodiment of step 237, the sacrificial oxide layer 304 is removed, and the liner 310 and the high aspect ratio process oxide 312 are etched back into the groove 308. In some embodiments, a wet etching step is used to remove the sacrificial oxide layer 304 and etch back the liner 310 and the high aspect ratio process oxide 312. This forms a sacrificial structure 320, which includes the remaining portions of the liner 310 and the high aspect ratio process oxide 312.

[0189] In step 240, method 200 includes forming an epitaxial growth silicon region on the top of the recess above the sacrificial structure and on the front side of the substrate. In several embodiments, forming the epitaxial growth silicon region on the top of the recess above the sacrificial structure and on the front side of the substrate includes the operations described in steps 242 and 244.

[0190] In step 242, method 200 includes an epitaxial growth operation to grow silicon in the recess 308 and over the substrate 302. (Reference) Figure 14 As an example, in one embodiment of step 242, the epitaxial growth silicon region 318 is grown in the groove 308 and above the substrate 302.

[0191] In step 244, method 200 includes performing an annealing operation on the substrate. (See reference...) Figure 15 For example, in one embodiment of step 244, an annealing operation is performed on the epitaxially grown silicon region 318 to make the epitaxially grown silicon region 318 consistent with the rest of the silicon substrate.

[0192] In step 250, method 200 includes forming a complementary metal-oxide-semiconductor image sensor device isolated by deep trench isolation (DTI). Reference Figure 16 For example, in one embodiment of step 250, an example CIS device 321 is formed. In various embodiments, the CIS device 321 includes at least one p-type well 322 formed over the sacrificial structure 320 and surrounding a portion of an epitaxially grown silicon region 318, an n+ doped region 324 formed over the at least one p-type well 322 for a floating diffusion region, a pad oxide layer 326 (e.g., similar to the sacrificial oxide layer 304) formed over the substrate 302, a gate polysilicon region 328 for delivering the gate, and a photodetector (not shown). In various embodiments, an interconnect structure 330 including a metallization layer and / or an interlayer dielectric (ILD) layer is formed to connect the CIS device 321 to multiple circuits.

[0193] In step 260, method 200 includes replacing the sacrificial structure from the back side with a high dielectric constant (HK) dielectric to complete the front-side deep trench isolation feature. In several embodiments, replacing the sacrificial structure from the back side with a high dielectric constant dielectric to complete the front-side deep trench isolation feature includes the operations described in steps 262, 264, 266, and 268.

[0194] In step 262, method 200 includes thinning the back side of the substrate to a high aspect ratio process oxide 312. (See reference) Figure 17 For example, in one embodiment of step 262, substrate 302 is flipped upward (e.g., about 180 degrees), and the back side of substrate 302 (e.g., second side 303) is thinned to the level of liner 310 in sacrificial structure 320. In several embodiments, chemical mechanical polishing is used to thin the back side of the substrate.

[0195] In step 264, method 200 includes removing the sacrificial structure to open a recess for the deep trench isolation feature. In several embodiments, a wet etching operation is used to remove the sacrificial structure. (See reference...) Figure 18 In one embodiment of step 264, the sacrificial structure 320, including the liner 310 and the high aspect ratio process oxide 312, is removed, leaving the groove 332.

[0196] In step 266, method 200 includes depositing a high-dielectric-constant dielectric material in the groove 332. (Reference) Figure 19 As an example, in one embodiment of step 266, a high-dielectric-constant dielectric layer 334 is deposited in the groove 332. In various embodiments, the high-dielectric-constant dielectric layer 334 is deposited using a suitable deposition technique.

[0197] In step 268, method 200 includes planarizing the substrate. (See reference...) Figure 20 For example, in one embodiment of step 268, the substrate is planarized to form a front-side deep trench isolation feature 336. In several embodiments, a chemical mechanical polishing operation is used to planarize the substrate. This forms the front-side deep trench isolation feature 336 in the semiconductor substrate 302, which can be used for inter-pixel and inter-node isolation in a back-illuminated stacked sensor.

[0198] In step 270, method 200 includes performing further manufacturing steps to form a CIS device. Figure 21A schematic cross-sectional view of a sub-pixel region 342 of an example back-illuminated stacked sensor with inter-pixel and inter-node isolation is shown. In this example, the sub-pixel region 342 includes at least one p-type well 322 above a front-side deep trench isolation feature 336 and surrounding a portion of an epitaxially grown silicon region 318, an n+ doped region 324, a pad oxide layer 326, a gate polysilicon region 328 for delivering the gate, a gate spacer 338, a front-side deep trench isolation feature 336, and a photodetector 340 (e.g., a photodiode).

[0199] Figure 22 A schematic cross-sectional view of an example sub-pixel region 400 formed using a front deep trench isolation feature 402 and a back deep trench isolation feature 404 is shown. In this example, for example... Figure 3 The techniques described in Method 200 can be used to form a front-side deep trench isolation feature 402, and combined with techniques suitable for forming a back-side deep trench isolation feature 404 to provide isolation for the sub-pixel region 400. In several embodiments, forming the sub-pixel region 400 can be achieved by forming the front-side deep trench isolation feature 402 and the epitaxial silicon feature 406 (e.g., using the techniques described in Method 200), followed by forming a CIS device including a vertical transfer gate 408, a photodetector 410, a gate spacer 412, a p-type well 414, and an n+ doped region 416, and then subsequently forming the back-side deep trench isolation feature 404, the shallow trench isolation feature 418, and the p-type well 420.

[0200] Figure 23 A schematic cross-sectional view of an example sub-pixel region 500 formed using a front deep trench isolation feature 502 and a back deep trench isolation feature 504 is shown. In this example, for example... Figure 3 The techniques described in Method 200 can be used to form a front-side deep trench isolation feature 502, and combined with techniques suitable for forming a back-side deep trench isolation feature 504 to provide isolation for the sub-pixel region 500. In various embodiments, forming the sub-pixel region 500 can be achieved by forming the front-side deep trench isolation feature 502 and the epitaxial silicon feature 506 (e.g., using the techniques described in Method 200), followed by the formation of a CIS device including a vertical transfer gate 508, a photodetector 510, a gate spacer 512, a p-type well 514, and an n+ doped region 516, and then by the formation of the back-side deep trench isolation feature 504, the shallow trench isolation feature 518, and the p-type well 520.

[0201] Figure 24 A schematic cross-sectional view of an example sub-pixel region 600 formed using a front deep trench isolation feature 602 and a back deep trench isolation feature 604 is shown. In this example, for example... Figure 3The techniques described in Method 200 can be used to form a front-side deep trench isolation feature 602, and combined with techniques suitable for forming a back-side deep trench isolation feature 604 to provide isolation for the sub-pixel region 600. In various embodiments, forming the sub-pixel region 600 can be achieved by forming the front-side deep trench isolation feature 602 and the epitaxial silicon feature 606 (e.g., using the techniques described in Method 200), followed by forming a CIS device including a vertical transfer gate 608, a photodetector 610, a gate spacer 612, a p-type well 614, and an n+ doped region 616, and then subsequently forming the back-side deep trench isolation feature 604, the shallow trench isolation feature 618, and the p-type well 620.

[0202] Figure 25 A schematic cross-sectional view of an example subpixel region 700 formed using a front-side deep trench isolation feature 702 is shown to illustrate example dimensions. In several embodiments, the front-side deep trench isolation feature 702 has a depth 704 of approximately 2.5 micrometers to 3 micrometers. In several embodiments, the epitaxially grown silicon region 706 (e.g., an epitaxial layer) has a length 708 of approximately 150 nanometers (nm) to approximately 300 nanometers. In several embodiments, the front-side deep trench isolation feature 702 (and the epitaxially grown silicon region 706) have a critical dimension 710 of approximately 60 nanometers to approximately 90 nanometers. In several embodiments, the p-type well 712 has a width 714 that is 0 nanometers to approximately 20 nanometers wider than the critical dimension 710.

[0203] Figure 26 A schematic cross-sectional view of an example subpixel region 800 formed using a first back-side deep trench isolation feature 802-1 and a second back-side deep trench isolation feature 802-2 is shown to illustrate the example dimensions. In several embodiments, the first back-side deep trench isolation feature 802-1 has a depth 804-1 of approximately 2.7 micrometers to 2.9 micrometers. In several embodiments, the second back-side deep trench isolation feature 802-2 has a depth 804-2 of approximately 1.8 micrometers to 2.2 micrometers. In several embodiments, the shallow trench isolation feature 806 has a length 808 of approximately 100 nanometers to approximately 300 nanometers. In several embodiments, the first back-side deep trench isolation feature 802-1 and the second back-side deep trench isolation feature 802-2 have a critical dimension 810 of approximately 110 nanometers to approximately 150 nanometers. In several embodiments, the width 814 of the p-type well 812 is 0 nanometers to approximately 10 nanometers wider than the critical dimension 810. Figure 25 and Figure 26 As illustrated, the critical dimension for manufacturing the front deep trench isolation feature can be smaller than the critical dimension for the back deep trench isolation feature.

[0204] Figure 25 and Figure 26The illustration shows that when using a front-side deep trench isolation feature instead of a back-side deep trench isolation feature, shallow trench isolation is not required for inter-pixel isolation. For example... Figure 25 As illustrated, pixel-to-pixel isolation can be achieved using the front deep trench isolation feature 702, but as... Figure 26 As illustrated, using shallow trench isolation feature 806 requires the first back-side deep trench isolation feature 802-1 and the second back-side deep trench isolation feature 802-2 to complete inter-pixel isolation.

[0205] Figure 25 and Figure 26 It is also illustrated that when using a front-side deep trench isolation feature instead of a rear-side deep trench isolation feature, the isolation structure can achieve a smaller critical size. For example... Figure 25 As illustrated, the critical size of the front deep trench isolation feature 702 can be in the range of approximately 60 nanometers to approximately 90 nanometers, but as... Figure 26 As illustrated, the first back-side deep trench isolation feature 802-1 and the second back-side deep trench isolation feature 802-2 may have a critical size of approximately 110 nanometers to approximately 150 nanometers. This may also result in the p-type well 712 having a smaller width than the p-type well 812. Compared to the first back-side deep trench isolation feature 802-1 and the second back-side deep trench isolation feature 802-2, the front-side deep trench isolation feature 702 with its smaller critical size can have a higher pixel density.

[0206] According to some embodiments of this disclosure Figure 27 A schematic top view of pixel 902 is shown. Pixel 902 is depicted in a so-called 4T configuration. As illustrated in the figures, pixel 902 has four sub-pixels (sub-pixel 902-1, sub-pixel 902-2, sub-pixel 902-3, and sub-pixel 902-4). However, this disclosure is not limited to this embodiment. In some other embodiments, depending on design requirements, pixel 902 may have three or more sub-pixels.

[0207] In an example embodiment, a first sub-pixel 902-1 includes a first photosensitive region located in a substrate 900 and a first transmission gate (e.g., a vertical transmission gate 152) extending into the first photosensitive region. A second sub-pixel 902-2 includes a second photosensitive region located in a substrate 900 and a second transmission gate extending into the second photosensitive region. A third sub-pixel 902-3 includes a third photosensitive region located in a substrate 900 and a third transmission gate extending into the third photosensitive region. Similarly, a fourth sub-pixel 902-4 includes a fourth photosensitive region located in a substrate 900 and a fourth transmission gate extending into the fourth photosensitive region. In some embodiments, the photosensitive regions in each sub-pixel (sub-pixel 902-1, sub-pixel 902-2, sub-pixel 902-3, sub-pixel 902-4) can be formed in the same step. Additionally, the transmission gates in each sub-pixel (sub-pixel 902-1, sub-pixel 902-2, sub-pixel 902-3, sub-pixel 902-4) can be formed in the same step.

[0208] In the example embodiment, the first, second, third, and fourth photosensitive regions share a floating diffusion region 904. In other words, the image charge accumulated in each photosensitive region can be transferred to the same floating diffusion region 904 for reading. In some embodiments, the floating diffusion region 904 may overlap the first, second, third, and fourth photosensitive regions. Additionally, associated with the example pixel 902 are a source follower (SF) gate 906, a row select (RS) gate 908, and a reset (RST) gate 910.

[0209] According to some embodiments of this disclosure Figure 28 A schematic top view of a first pixel 952 and a second pixel 972 is shown. The first pixel 952 and the second pixel 972 are shown in a so-called 8T configuration. As illustrated in the figures, the first pixel 952 has four sub-pixels (sub-pixel 952-1, sub-pixel 952-2, sub-pixel 952-3, and sub-pixel 952-4), and the second pixel 972 has four sub-pixels (sub-pixel 972-1, sub-pixel 952-2, sub-pixel 972-3, and sub-pixel 972-4). However, this disclosure is not limited to this embodiment. In some other embodiments, depending on design requirements, the first pixel 952 may have three or more sub-pixels, and the second pixel 972 may have three or more sub-pixels.

[0210] In an example embodiment, a first sub-pixel 952-1 includes a first photosensitive region located in a substrate 940 and a first transmission gate (e.g., a vertical transmission gate 152) extending into the first photosensitive region. A second sub-pixel 952-2 includes a second photosensitive region located in a substrate 940 and a second transmission gate extending into the second photosensitive region. A third sub-pixel 952-3 includes a third photosensitive region located in a substrate 940 and a third transmission gate extending into the third photosensitive region. Similarly, a fourth sub-pixel 952-4 includes a fourth photosensitive region located in a substrate 940 and a fourth transmission gate extending into the fourth photosensitive region.

[0211] Similarly, in the example embodiment, the first sub-pixel 972-1 includes a first photosensitive region located in the substrate 940 and a first transmission gate (e.g., a vertical transmission gate 152) extending into the first photosensitive region. The second sub-pixel 972-2 includes a second photosensitive region located in the substrate 940 and a second transmission gate extending into the second photosensitive region. The third sub-pixel 972-3 includes a third photosensitive region located in the substrate 940 and a third transmission gate extending into the third photosensitive region. Similarly, the fourth sub-pixel 972-4 includes a fourth photosensitive region located in the substrate 940 and a fourth transmission gate extending into the fourth photosensitive region.

[0212] In the example embodiment, the first photosensitive area, the second photosensitive area, the third photosensitive area and the fourth photosensitive area of ​​the first pixel 952 share a floating diffusion area 954, and the first photosensitive area, the second photosensitive area, the third photosensitive area and the fourth photosensitive area of ​​the second pixel 972 share a floating diffusion area 974.

[0213] In this example embodiment, the first pixel 952 has an associated reset gate 960, the second pixel 972 has an associated reset gate 976, and the first pixel 952 and the second pixel 972 share a source follower gate 956 and a column select gate 958. Because the 8T configuration shares the source follower gate 956 and the column select gate 958, the 8T configuration can have a higher pixel density than the 4T configuration.

[0214] In some embodiments, the technology described herein relates to a method of forming a semiconductor device, including providing a substrate having a front side and a back side, forming a groove in the substrate extending from the front surface of the front side to an interior region of the substrate, forming a sacrificial structure in the groove, forming an epitaxially grown silicon region on the top of the groove above the sacrificial structure and on the front side of the substrate, forming a complementary metal-oxide-semiconductor image sensor device on the front side of the substrate, removing the sacrificial structure to create an opening, and forming a high-dielectric-constant dielectric layer in the opening.

[0215] In some cases, the technique described herein is about a method in which the sacrificial structure comprises an inner liner and a high aspect ratio process oxide layer.

[0216] In some cases, the technique described herein relates to a method in which an epitaxial growth silicon region is formed on the top of a recess above a sacrificial structure and on the front side of a substrate, further comprising performing an annealing step on the substrate.

[0217] In some cases, the technique described herein relates to a method in which removing the sacrificial structure to create an opening includes planarizing the back side of a substrate to expose the sacrificial structure.

[0218] In some cases, the technique described herein relates to a method in which removing the sacrificial structure to create an opening includes performing a wet etching step using hydrogen fluoride.

[0219] In some cases, the technology described herein relates to a method in which a complementary metal-oxide-semiconductor image sensor device includes a transfer gate, a photodetector, and a floating diffusion region.

[0220] In some embodiments, the technology described herein relates to a semiconductor device including a photodetector located in a substrate having a front side and a back side, a vertical transfer gate located on the front side of the substrate, a first deep trench isolation feature disposed in the substrate and located on one side of the photodetector, an epitaxial layer disposed in the substrate above the first deep trench isolation feature and located on the first side of the vertical transfer gate, and a p-type well disposed in the substrate and located around the epitaxial layer.

[0221] In some embodiments, the technology described herein relates to a semiconductor device that further includes a floating diffusion region comprising an n-type doped region formed in a substrate and located above an epitaxial layer.

[0222] In some embodiments, the technology described herein relates to a semiconductor device in which a first deep trench isolation feature has a depth of about 2.5 micrometers to 3 micrometers, an epitaxial layer has a length of about 150 nanometers to about 300 nanometers, the first deep trench isolation feature and the epitaxial layer have a critical dimension of about 60 nanometers to about 90 nanometers, and the p-type well has a width that is 0 nanometers to about 20 nanometers wider than the critical dimension.

[0223] In some embodiments, the technology described herein relates to a semiconductor device, which further includes a second deep trench isolation feature disposed in a substrate and located on a second side of a photodetector, a second epitaxial layer disposed in a substrate above the second deep trench isolation feature and located on a second side of a vertical transmission gate, a second p-type well disposed in the substrate and located around the second epitaxial layer, and an n-type doped region formed in the substrate and located above the second epitaxial layer.

[0224] In some embodiments, the technology described herein relates to a semiconductor device, which further includes a second deep trench isolation feature disposed in a substrate and located on a second side of a photodetector, a shallow trench isolation feature in the substrate located above the second deep trench isolation feature and on a second side of a vertical transmission gate, and a second p-type well disposed in the substrate and located around the shallow trench isolation feature.

[0225] In some embodiments, the technology described herein relates to a semiconductor device wherein a first deep trench isolation feature has a depth of approximately 2.5 micrometers to 3 micrometers, a second deep trench isolation feature has a depth of approximately 2.7 micrometers to 2.9 micrometers, an epitaxial layer has a length of approximately 150 nanometers to approximately 300 nanometers, a shallow trench isolation feature has a length of approximately 100 nanometers to approximately 300 nanometers, the first deep trench isolation feature has a critical dimension of approximately 60 nanometers to approximately 90 nanometers, the second deep trench isolation feature has a second critical dimension of approximately 110 nanometers to approximately 150 nanometers, a p-type well has a width that is 0 nanometers to approximately 20 nanometers wider than the critical dimension, and the second p-type well has a width that is 0 nanometers to approximately 10 nanometers wider than the second critical dimension.

[0226] In some embodiments, the technology described herein relates to a semiconductor device in which a shallow trench isolation feature contacts a second deep trench isolation feature, the first deep trench isolation feature having a depth of approximately 2.5 micrometers to 3 micrometers, the second deep trench isolation feature having a depth of approximately 1.8 micrometers to 2.2 micrometers, an epitaxial layer having a length of approximately 150 nanometers to approximately 300 nanometers, the shallow trench isolation feature having a length of approximately 100 nanometers to approximately 300 nanometers, the first deep trench isolation feature having a critical dimension of approximately 60 nanometers to approximately 90 nanometers, the second deep trench isolation feature having a second critical dimension of approximately 110 nanometers to approximately 150 nanometers, a p-type well having a width 0 nanometers to approximately 20 nanometers wider than the critical dimension, and the second p-type well having a width 0 nanometers to approximately 10 nanometers wider than the second critical dimension.

[0227] In some embodiments, the technology described herein relates to a semiconductor device, which further includes an n-type doped region formed in a substrate and adjacent to a shallow trench isolation feature.

[0228] In some embodiments, the technology described herein relates to a method of forming a pixel array, comprising providing a substrate having a front side and a back side, forming a recess in the front side of the substrate for a front-side deep trench isolation feature, partially filling the recess using a sacrificial structure, forming an epitaxially grown silicon region in the top of the recess above the sacrificial structure and on the front side of the substrate, forming a vertical transfer gate, a photodetector, a floating diffusion region and a p-type well in the substrate, and replacing the sacrificial structure from the back side with a high-dielectric-constant dielectric to complete the front-side deep trench isolation feature.

[0229] In some cases, the technique described herein relates to a method in which completing a front deep trench isolation feature includes completing a front deep trench isolation feature with a depth of approximately 2.5 micrometers to 3 micrometers.

[0230] In some cases, the technique described herein relates to a method in which forming a groove in the front side of a substrate includes forming a groove in the front side of the substrate having a critical size of about 60 nanometers to about 90 nanometers.

[0231] In some cases, the techniques described herein relate to a method in which completing a front-side deep trench isolation feature includes planarizing the back side of a substrate to expose a sacrificial structure, creating an opening by removing the sacrificial structure using a wet etching step with hydrogen fluoride, and filling the opening with a high-dielectric-constant dielectric.

[0232] In some embodiments, the technology described herein relates to a method in which a formed pixel array has a first pixel region and a second pixel region, the first pixel region being configured to convert incident light into a first signal of the first pixel, and the second pixel region being configured to convert incident light into a second signal of the second pixel. Forming a vertical transfer gate, a photodetector, a floating diffusion region, and a p-type well in a substrate includes forming the vertical transfer gate, photodetector, floating diffusion region, and p-type well in the substrate of each of the first and second pixel regions. The first and second pixel regions share a source follower device and a column select device.

[0233] In some embodiments, the technique described herein relates to a method in which each first pixel region and second pixel region includes a plurality of sub-pixel regions that share a floating diffusion region of a particular pixel, and these sub-pixel regions are configured to generate sub-pixel signals of each sub-pixel region of the particular pixel, wherein generating a first signal is based on the sub-pixel signals generated by the respective sub-pixel regions of the first pixel region, and generating a second signal is based on the sub-pixel signals generated by the respective sub-pixel regions of the second pixel region.

[0234] In some embodiments, the technology described herein relates to a pixel array having a first pixel region and a second pixel region, the first pixel region being configured to convert incident light into a first signal of the first pixel, and the second pixel region being configured to convert incident light into a second signal of the second pixel. Each of the first and second pixel regions includes a vertical transmission gate disposed above a photodetector in a substrate having a front side and a back side, a front deep trench isolation feature disposed in the substrate and located on one side of the photodetector, an epitaxial layer formed in the substrate above the front deep trench isolation feature and located on the first side of the vertical transmission gate, and a p-type well disposed in the substrate and located around the epitaxial layer.

[0235] In some embodiments, the technology described herein relates to a semiconductor device including a substrate having a front side and a back side, a recess located in the substrate and extending from the front side of the substrate into an interior region of the substrate, a high-dielectric-constant dielectric layer located in the recess, an epitaxially grown silicon region located above the high-dielectric-constant dielectric layer in the recess and on the front side of the substrate, and a complementary metal-oxide-semiconductor image sensor device located on the front side of the substrate.

[0236] In some embodiments, the technology described herein relates to a pixel array including a substrate having a front side and a back side, a front deep trench isolation feature located in the front side of the substrate, an epitaxial layer located above the front deep trench isolation feature, and a first pixel region, wherein the first pixel region includes a first photodetector located in the substrate and on one side of the front deep trench isolation feature, a first vertical transfer gate located in the substrate and above the first photodetector, a first floating diffusion region located in the substrate and above the epitaxial layer, and a first p-type well located in the substrate and around the epitaxial layer.

[0237] In some embodiments, the technology described herein relates to a pixel array including a second pixel region, wherein the second pixel region includes a second photodetector, a second vertical transfer gate, a second floating diffusion region and a second p-type well located in a substrate, and the first pixel region and the second pixel region share a source follower device and a column select device.

[0238] In some cases, the technique described herein relates to a pixel array in which a first pixel region comprises multiple sub-pixel regions and the sub-pixel regions share a first floating diffusion region.

[0239] While at least one exemplary embodiment has been presented in the foregoing detailed description, it should be understood that numerous variations exist in the embodiments. It should also be understood that one or more exemplary embodiments are merely examples and are not intended to limit the scope, applicability, or configuration of this disclosure in any way. Rather, the foregoing detailed description will provide those skilled in the art with convenient planning for implementing exemplary embodiments of this disclosure. It should be understood that various changes may be made to the function and configuration of the components described in the exemplary embodiments without departing from the scope of this disclosure as set forth in the appended claims.

Claims

1. A semiconductor device, characterized in that, include: A light detector is located in a substrate having a front side and a back side; A vertical transmission gate is located on the front side of the substrate; A first deep trench isolation feature is disposed in the substrate and located on one side of the photodetector; An epitaxial layer is disposed in the substrate above the first deep trench isolation feature and located on a first side of the vertical transmission gate; and A p-type well is disposed in the substrate and located around the epitaxial layer.

2. The semiconductor device as claimed in claim 1, characterized in that, It further includes a floating diffusion region, wherein the floating diffusion region includes an n-type doped region formed in the substrate and located above the epitaxial layer.

3. The semiconductor device as claimed in claim 1, characterized in that, in: The first deep trench isolation feature has a depth of 2.5 micrometers to 3 micrometers; The epitaxial layer has a length of 150 nanometers to 300 nanometers; The first deep trench isolation feature and the epitaxial layer have a critical size of 60 nanometers to 90 nanometers; and The p-type trap has a width that is 0 to 20 nanometers wider than the critical dimension.

4. The semiconductor device as claimed in claim 1, characterized in that, Further includes: A second deep trench isolation feature is disposed in the substrate and located on a second side of the photodetector; A second epitaxial layer is disposed above the second deep trench isolation feature and on a second side of the vertical transmission gate in the substrate; A second p-type well is disposed in the substrate and located around the second epitaxial layer; and An n-type doped region is formed in the substrate and located above the second epitaxial layer.

5. The semiconductor device as claimed in claim 1, characterized in that, Further includes: A second deep trench isolation feature is disposed in the substrate and located on a second side of the photodetector; A shallow trench isolation feature is located above the second deep trench isolation feature and on a second side of the vertical transmission gate in the substrate; and A second p-type well is disposed in the substrate and located around the shallow trench isolation feature.

6. The semiconductor device as claimed in claim 5, characterized in that, in: The first deep trench isolation feature has a depth of 2.5 micrometers to 3 micrometers; The second deep trench isolation feature has a depth of 2.7 micrometers to 2.9 micrometers; The epitaxial layer has a length of 150 nanometers to 300 nanometers; The shallow trench isolation feature has a length of 100 nanometers to 300 nanometers; The first deep trench isolation feature has a critical size of 60 nanometers to 90 nanometers; The second deep trench isolation feature has a second critical size of 110 nanometers to approximately 150 nanometers; The p-type well has a width that is 0 to 20 nanometers wider than the critical dimension; as well as The second p-type well has a width that is 0 to 10 nanometers wider than the second critical dimension.

7. A semiconductor device, characterized in that, include: A substrate having a front side and a back side; A groove is located in the substrate and extends from the front side of the substrate into the interior region of the substrate; A high dielectric constant dielectric layer is located in the groove; An epitaxially grown silicon region is located above the high-dielectric-constant dielectric layer in the groove and on the front side of the substrate; and A complementary metal-oxide-semiconductor image sensor device is located on the front side of the substrate.

8. A pixel array, characterized in that, include: A substrate having a front side and a back side; A front-side deep trench isolation feature is located on the front side of the substrate; An epitaxial layer is located above the front deep trench isolation feature; as well as A first pixel region, including: A first photodetector is located in the substrate and on one side of the front deep trench isolation feature; A first vertical transmission gate is located in the substrate and above the first photodetector; A first floating diffusion region is located in the substrate and above the epitaxial layer; and A first p-type well is located in the substrate and around the epitaxial layer.

9. The pixel array as described in claim 8, characterized in that, Further includes: A second pixel region includes a second photodetector, a second vertical transmission gate, a second floating diffusion region, and a second p-type well located in the substrate. The first pixel region and the second pixel region share a source follower device and a column selection device.

10. The pixel array as described in claim 8, characterized in that, The first pixel region includes multiple sub-pixel regions, and the multiple sub-pixel regions share the first floating diffusion region.

Images