Semiconductor image sensor structure

Abstract

This disclosure relates to a semiconductor image sensor structure. The structure includes image sensing pixels with a critical dimension (CD) and a plurality of image sensing pixels separated by deep trench isolation (DTI) with a high aspect ratio (AR). Compared to the bottom surface profile at the intersection of the DTIs, multiple portions of the DTIs between adjacent image sensing pixels have substantially uniform bottom surface profiles. Furthermore, the bottom surface of the DTI is formed as a doped layer beneath the image sensing pixels to prevent leakage of photoexcited charge carriers between the image sensing pixels.

Description

Technical Field

[0001] This disclosure relates to a semiconductor image sensor structure. Background Technology

[0002] Semiconductor image sensors are configured to sense radiation, such as light. Complementary metal-oxide-semiconductor (CMOS) image sensors and charge-coupled device (CCD) sensors are used in a variety of applications, such as digital cameras and mobile phone cameras. These devices utilize an array of pixels in a substrate (which may include photodiodes and transistors) to sense radiation projected toward the pixels and convert the sensed radiation into electrical signals. Utility Model Content

[0003] Some embodiments disclosed herein provide a semiconductor image sensor structure, including a doped layer disposed on a substrate; a first pixel, a second pixel, a third pixel, and a fourth pixel disposed on the substrate, wherein the doped layer surrounds the lower portion of the first pixel, the lower portion of the second pixel, the lower portion of the third pixel, and the lower portion of the fourth pixel; a first trench and a second trench that intersect and separate the first pixel, the second pixel, the third pixel, and the fourth pixel, wherein the bottom surface of the first trench and the bottom surface of the second trench are lower than the top surface of the doped layer, and the intersection of the first trench and the second trench includes a recess, the bottom surface of the recess being lower than the bottom surface of the first trench and the bottom surface of the second trench, and the edge of the recess being above the bottom surface of the first trench and the bottom surface of the second trench; and a dielectric layer disposed in the first trench and the second trench, having a portion protruding into the doped layer, wherein the portion is located at the intersection of the first trench and the second trench.

[0004] Other embodiments disclosed herein provide a semiconductor image sensor structure, including a doped layer disposed on a substrate; a first pixel, a second pixel, a third pixel, and a fourth pixel disposed on the substrate, wherein the doped layer surrounds the lower portion of the first pixel, the lower portion of the second pixel, the lower portion of the third pixel, and the lower portion of the fourth pixel; a first trench and a second trench that intersect and separate the first pixel, the second pixel, the third pixel, and the fourth pixel, wherein the intersection of the first trench and the second trench includes a recess; and a dielectric layer disposed in the first trench and the second trench, wherein the first trench and the second trench each include a depth greater than the distance between the doped layer and the top surface of the substrate, and wherein the edge of the recess is located above the bottom surface of the first trench and the second trench.

[0005] Further embodiments of this disclosure provide a semiconductor image sensor structure, including a doped layer disposed on a substrate; a first radiation sensing region, a second radiation sensing region, a third radiation sensing region, and a fourth radiation sensing region disposed on the substrate, wherein the doped layer surrounds the lower portions of the first radiation sensing region, the lower portions of the second radiation sensing region, the lower portions of the third radiation sensing region, and the lower portions of the fourth radiation sensing region; a first trench and a second trench that intersect and separate the first radiation sensing region, the second radiation sensing region, the third radiation sensing region, and the fourth radiation sensing region, wherein the first trench and the second trench extend vertically to the top surface of the doped layer; and a dielectric layer that fills the first trench and the second trench and has a portion protruding into the doped layer, the portion being located at the intersection of the first trench and the second trench. Attached Figure Description

[0006] The various embodiments disclosed herein can be best understood by reading in conjunction with the accompanying drawings through the following detailed description. It should be noted that, in accordance with industry standard practice, the various features are not drawn to scale. In fact, for clarity of discussion, the dimensions of the various features may be arbitrarily increased or decreased.

[0007] Figure 1A and Figure 1B This is a horizontal cross-sectional view of a semiconductor image sensor device according to some embodiments;

[0008] Figure 2A and Figure 2B This is a vertical cross-sectional view of a semiconductor image sensor device according to some embodiments;

[0009] Figure 3A and Figure 3B This is a flowchart of a method for configuring a structure for forming a semiconductor image sensor device according to some embodiments;

[0010] Figure 4A This is a top view of an intermediate structure during the manufacturing process of a semiconductor image sensor device, according to some embodiments.

[0011] Figures 4B to 6 This is a vertical cross-sectional view of an intermediate structure during the manufacturing process of a semiconductor image sensor device, according to some embodiments.

[0012] Figure 7A This is a top view of an intermediate structure during the manufacturing process of a semiconductor image sensor device according to some embodiments; and

[0013] Figures 7B to 13 This is a vertical cross-sectional view of an intermediate structure during the manufacturing process of a semiconductor image sensor device, according to some embodiments.

[0014] [Symbol Explanation]

[0015] 100: Image sensor device

[0016] 104,420:Substrate

[0017] 105: Structure

[0018] 112: Doped layer

[0019] 112x, 112y: Partial

[0020] 120,820 pixels

[0021] 120s: Side surface

[0022] 120t: Top surface

[0023] 142, 142x, 142y, 842: DTI / Deep Trench Isolation

[0024] 142c, 742c: Intersection

[0025] 162: Gap filler

[0026] 245c,245x,245y,845c,845x,845y,1045c,1045x,1045y,1245c,1245x,1245y: Bottom surface

[0027] 245xc: Center

[0028] 245xp: Peak

[0029] 264,608: Buffer layer

[0030] 266: Grid Structure

[0031] 268: Filter

[0032] 270: Microlens

[0033] 300: Method

[0034] 310, 320, 330, 332, 334, 336, 338, 340, 350: Step 412: Doped layer

[0035] 420b: First surface

[0036] 420f: Second surface

[0037] 440: Mask

[0038] 450: Dopant

[0039] 502: Interlayer dielectric

[0040] 504: Conductive via

[0041] 506: Wire

[0042] 508: Transistor

[0043] 610: Grain

[0044] 740: Masking layer

[0045] 742: Opening

[0046] 742x, 742y: slots

[0047] 840, 1040, 1240: Etching agent

[0048] 945x: Surface

[0049] 950, 1150: Gas

[0050] 960, 1160: Polymer layer

[0051] 1045xc: Midpoint

[0052] A-A', B-B', C-C', D-D': Lines

[0053] CW,W1: Width

[0054] D,r1,r2,t1,t2: Distance

[0055] Dc, Dt, D8, D10: Depth

[0056] L1: Length

[0057] x, y, z: axes

[0058] z: Direction

[0059] α, β: Angles Detailed Implementation

[0060] The following disclosure provides numerous different embodiments or examples for implementing various features of this disclosure. Specific examples of elements and configurations are described below to simplify this disclosure. Of course, these specific examples are merely illustrative and not intended to be limiting. For example, the formation of a first feature over or on a second feature in the following description may include embodiments where the first and second features are formed in direct contact, and may also include embodiments where an additional feature may be formed between the first and second features so that the first and second features do not need to be in direct contact. Additionally, reference numerals and / or letters may be repeated in various examples in this disclosure. This repetition is for simplicity and clarity and does not in itself indicate a relationship between the various embodiments and / or configurations discussed, nor is it intended to limit the relationship between the various embodiments and / or configurations described.

[0061] Additionally, for ease of description, spatially relative terms (e.g., "below," "under," "lower," "above," "upper," and the like) may be used herein to describe the relationship between one component or feature and another, as illustrated in the accompanying drawings. Besides the orientations depicted in the drawings, the spatially relative terms are also intended to cover different orientations of the device in use or operation. The device may be oriented in other ways (rotated 90 degrees or positioned in other orientations), and thus the spatially relative descriptive terms used herein may be interpreted accordingly.

[0062] The terms “approximately” and “substantially” can mean a given quantity that varies within 5% of that value (e.g., ±1%, ±2%, ±3%, ±4%, ±5%). These values ​​are merely illustrative and are not intended to limit this disclosure. It should be understood that, according to this disclosure, the terms “approximately” and “substantially” can mean a percentage of a given quantity.

[0063] Semiconductor image sensing devices (such as complementary metal-oxide-semiconductor (CMOS)) may include an array of one or more image sensing pixels to generate an image. The image sensing pixels are separated by deep trench isolation (DTI), which is filled with a dielectric material. Each image sensing pixel may include a photodiode to generate charge carriers in response to incident light. These charge carriers can pass through a doped layer beneath the image sensing pixel and are then collected as an electrical signal for processing by electronics. The doped layer may form a depletion region to prevent charge carriers generated by the image sensing pixel from leaking into adjacent image sensing pixels, thereby enabling the resolution of the signal provided by the image sensing pixel.

[0064] With advancements in semiconductor manufacturing technology, the critical dimension (CD) of image sensing pixel arrays can be scaled down, thereby providing improved performance, such as higher resolution, for semiconductor image sensing devices. For instance, by reducing the width of image sensing pixels to the micrometer range and the width of the depth-to-width (DTI) array to the sub-micrometer range, more image sensing pixels can be packaged within the limited sensing area of ​​a semiconductor image sensing device. During the manufacturing process of forming DTIs with narrower and deeper features (corresponding to higher aspect ratios), the etching rate of the bottom surface of the DTI can vary significantly depending on the local geometric details of the DTI. This phenomenon is also known as the "loading effect." Specifically, the bottom surface at the intersection of the DTI can have a larger CD and can be etched deeper than the bottom surface of the portion of the DTI farther from the intersection. As the CD of image sensing pixels shrinks, the effect of the higher etching rate at the bottom surface of the DTI intersection can extend to the DTI portion between adjacent image sensing pixels, resulting in an uneven bottom surface of the DTI. Therefore, some portions of the bottom surface of the DTI may not be etched deep enough into the doped layer, and photoexcited charge carriers between adjacent image sensing pixels may leak in these portions, thereby impairing the resolution of the semiconductor image sensing device.

[0065] To overcome the aforementioned challenges, the embodiments disclosed herein relate to the structure of a semiconductor image sensor device and a method of forming the structure. In some embodiments, the structure may include image sensing pixels having a small CD and separated by a DTI having a high aspect ratio (AR). In some embodiments, portions of the DTI between adjacent image sensing pixels may have a substantially uniform bottom surface profile to prevent photoexcited charge carrier leakage between the image sensing pixels. In some embodiments, the method may include performing an etching process and a coating process to mitigate loading effects. In some embodiments, the etching process and the coating process may be repeated alternately until the bottom surface of the DTI is etched into a doped layer beneath the image sensing pixels.

[0066] Please see Figures 1A to 2B The image sensor device 100 shown. Figure 1A A top view of an image sensor device 100 according to some embodiments is shown. Figure 1A A horizontal cross-sectional view of structure 105 is also shown, which is an enlarged portion of image sensor device 100. Figure 1B Another horizontal cross-sectional view of structure 105 according to some embodiments is also shown. Figure 2A The illustration depicts corresponding to some embodiments. Figure 1A and Figure 1B The vertical cross-sectional view of structure 105 with line A-A' in the middle. Figure 2B The illustration depicts corresponding to some embodiments. Figure 1A and Figure 1B The cross-sectional view of structure 105 along line B-B'. It should be noted that... Figure 1A The horizontal cross-sectional view shown corresponds to Figure 2A and Figure 2B The line C-C' in the middle, and Figure 1B The horizontal cross-sectional view shown corresponds to Figure 2A and Figure 2B The line D-D' in the middle.

[0067] Please see Figures 1A to 2B Structure 105 may include a doped layer 112 disposed on substrate 104 and an array of a plurality of pixels 120, wherein the doped layer 112 surrounds a plurality of lower portions of the array of pixels 120. Substrate 104 may extend along a horizontal direction (e.g., x and / or y axis) and have a top surface perpendicular to a vertical direction (e.g., z axis). Substrate 104 may include a semiconductor material, such as silicon (Si). In some embodiments, substrate 104 may include a crystalline silicon substrate (e.g., a Si wafer). In some embodiments, substrate 104 may include (i) elemental semiconductors, such as silicon or germanium (Ge); (ii) compound semiconductors, including silicon carbide (SiC), gallium arsenide (GaAs), gallium phosphide (GaP), indium phosphide (InP), indium arsenide (InAs), and / or indium antimonide (InSb); (iii) alloy semiconductors, including silicon germanium carbide (SiGeC), silicon germanium (SiGe), gallium arsenide phosphide (GaAsP), indium gallium phosphide (InGaP), indium gallium arsenide (InGaAs), indium gallium arsenide phosphide (InGaAsP), indium aluminum arsenide (InAlAs), and / or aluminum gallium arsenide (AlGaAs); (iv) or combinations thereof. Furthermore, substrate 104 may be doped according to design requirements (e.g., p-type substrate or n-type substrate). In some embodiments, substrate 104 may be undoped. In some embodiments, substrate 104 may be doped with a p-type dopant (e.g., boron (B), indium (In), aluminum (Al), or gallium (Ga)) or an n-type dopant (e.g., phosphorus (P), arsenic (As), or antimony (Sb)). In some embodiments, the crystal orientation of substrate 104 may be (100), (110), or (111). In some embodiments, substrate 104 may include a grain, a buffer layer on the grain, and an interlayer dielectric having conductive vias and / or wires embedded in the interlayer dielectric. In some embodiments, the conductive vias and / or wires may be coupled to external electrical components, such as transistors, resistors, capacitors, and inductors. In some embodiments, electrical components may be included in the interlayer dielectric of substrate 104. In some embodiments, a doped layer 112 may be disposed on the interlayer dielectric.

[0068] Please see Figure 2A and Figure 2B The substrate 104 may include a die 610, a buffer layer 608 disposed on the die 610, and an interlayer dielectric 502 disposed on the buffer layer 608. In some embodiments, the die 610 may be a semiconductor wafer bonded by the buffer layer and the interlayer dielectric 502. The buffer layer 608 may provide mechanical bonding strength and electrical isolation between the interlayer dielectric 502 and the die 610, and may include a dielectric material, such as silicon oxide, silicon nitride, any other suitable dielectric material, and / or combinations thereof. The interlayer dielectric 502 may include silicon oxide, silicon nitride, any other suitable dielectric material, and / or combinations thereof. In some embodiments, the interlayer dielectric 502 may include a transistor 508 electrically coupled to the pixel 120 to process charge signals generated by the pixel 120 according to optical signals. The transistor 508 may include a metal-oxide-semiconductor field-effect transistor (MOS FET), a fin-FET, a gate-all-around field-effect transistor (GAA-FET), and / or combinations thereof. In some embodiments, transistor 508 may include p-type and / or n-type transistors. In some embodiments, transistor 508 includes charge transport transistors, transfer transistors, reset transistors, amplification transistors, selection transistors, source follower transistors, and / or readout transistors. In some embodiments, interlayer dielectric 502 may include multiple interconnect layers that couple transistors 508 to each other and / or to external circuitry. The interconnect layers may include conductive vias 504 and wires 506. Conductive vias 504 and wires 506 may include conductive materials such as copper, aluminum, tungsten, doped polysilicon, any other suitable conductive material, and / or combinations thereof. Other circuitry and devices for detecting and processing photoexcited charge carriers may also be embedded in interlayer dielectric 502 and are not shown for simplicity.

[0069] Please see Figures 1A to 2B The doped layer 112 may extend along the horizontal direction (x-axis and y-axis) between pixels 120 and surround the lower part of pixel 120. For example, the doped layer 112 may include multiple portions 112x extending along the x-axis and multiple portions 112y extending along the y-axis. It is worth noting that, according to Figure 1A and Figure 1B ,because Figure 1A and Figure 1B Line A-A' in the equation does not cross part 112y, therefore Figure 2BThe portion 112y shown is not part of a cross-section but is viewed against the background. The doped layer 112 may be doped with p-type or n-type dopants to form a depletion region beneath the array of pixels 120 to prevent photo-excited charge carriers from leaking between adjacent pixels 120. In some embodiments, the doped layer 112 may comprise the same elemental semiconductor or the same compound semiconductor as the substrate 104. In some embodiments, the doped layer 112 may comprise a semiconductor different from the semiconductor in the substrate 104. In some embodiments, the doped layer 112 may be doped with p-type dopants (e.g., B, Al, Ga, and / or In) or n-type dopants (e.g., P, As, and / or Sb). In some embodiments, the crystal orientation of the doped layer 112 may be (100), (110), or (111). In some embodiments, the doping concentration of the doped layer 112 may be between about 1 × 10⁻⁶. 17 cm -3 Approximately 5×10 18 cm -3 The thickness of the doped layer 112 may be between about 0.3 μm and about 5 μm in some embodiments. In some embodiments, the doped layer 112 may be formed by an ion implantation process. In some embodiments, the doped layer 112 may be formed by a diffusion process.

[0070] Please see Figures 1A to 2B The pixels 120 disposed on the substrate 104 can be separated from each other by a doped layer 112 and a deep trench isolation (DTI) 142. In some embodiments, the array of pixels 120 may include multiple rows and multiple columns of pixels 120. For example, the array of pixels 120 may include 480 rows and 640 columns, such that the image sensor device 100 has a resolution of 480×640. It is worth noting that, according to Figure 1A and Figure 1B ,because Figure 1A and Figure 1B Line A-A' in the middle does not cross pixel 120, therefore Figure 2B The pixel 120 shown is not part of the cross-section but is viewed against the background. In some embodiments, pixel 120 may have the same shape, such as a rectangular shape with a width W1 and a length L1, as shown below. Figure 1A and Figure 1B As shown. In some embodiments, pixel 120 may have a square shape with a width W1 equal to its length L1. In some embodiments, pixel 120 may have other shapes, such as a circle, ellipse, triangle, polygon, or any other suitable shape. In some embodiments, pixel 120 may have different shapes. In some embodiments, the width W1 may be between about 0.5 μm and about 10 μm. In some embodiments, the length L1 may be between about 0.5 μm and about 10 μm.

[0071] Pixel 120 includes a radiation sensing region capable of absorbing incident light and generating photoexcited charge carriers, which can be collected by substrate 104 and further converted into electrical signals and processed by transistor 508 in interlayer dielectric 502. In some embodiments, pixel 120 may include the same elemental semiconductor or the same compound semiconductor as doped layer 112. In some embodiments, each pixel 120 may be doped with both p-type and n-type dopants to form a photodiode structure, such as a PN junction or a PIN junction. In some embodiments, pixel 120 may include a pinned layer photodiode, a photogate, a reset transistor, a source follower transistor, a transfer transistor, other suitable structures, and / or combinations thereof. In some embodiments, pixel 120 may be doped using an ion implantation process. In some embodiments, pixel 120 may be doped using a diffusion process.

[0072] Please see Figures 1A to 2B DTI 142 extends along the horizontal direction (e.g., the x-axis and y-axis). For example, as... Figure 1A , Figure 2A , Figure 2B As shown, DTI 142 may include DTI 142x separating pixels 120 in different columns and DTI 142y separating pixels 120 in different rows. In some embodiments, DTI 142x / 142y may have a width W between about 0.03 μm and about 0.5 μm. In some embodiments, the ratio of width W1 to width W may be between about 2 and about 20. DTI 142 may include a plurality of intersections 142c, where DTI 142x and 142y intersect each other, as shown. Figure 1A As shown. In some embodiments, DTI142 can be formed by etching the material originally located between pixels 120, so that pixels 120 can be isolated.

[0073] In some embodiments, the intersection 142c and DTI 142x / 142y may have different critical dimensions (CD). For example, the CD of DTI 142x / 142y may be a width W, which is smaller than the CD of intersection 142c as measured by the width C of the recess in intersection 142c. In some embodiments, the ratio of width C to width W may be between about 1 and about 3. In some embodiments, because the CDs of intersection 142c and DTI 142x / 142y are different, and the etch rates of intersection 142c and DTI 142x / 142y may be different, the etchant may reach the bottom of intersection 142c more easily than it reaches the bottom of DTI 142x / 142y, resulting in a difference in the depth of intersection 142c compared to the depth of DTI 142x / 142y. This is also known as the “loading effect.” For example, as Figure 2A As shown, the depth Dt near the midpoint of a portion between two adjacent intersections 142c can differ from the depth Dc within the intersection 142c. In some embodiments, depths Dc and Dt can be between about 0.5 μm and about 5 μm. In some embodiments, depth Dc can be greater than depth Dt. For example, depth Dc can be about 0.1 μm to about 0.4 μm deeper than depth Dt. In some embodiments, the aforementioned loading effect becomes more pronounced for trenches with a higher aspect ratio (AR), which can be defined as the ratio of the trench depth to the trench's CD. In some embodiments, the aspect ratio of DTI 142 can be between about 5:1 and about 50:1. For example, the aspect ratio of DTI 142 can be about 5:1, 10:1, 20:1, 30:1, 40:1, and 50:1.

[0074] In some embodiments, the load effect can affect the profile of the bottom surface of the DTI 142. Figure 2A It is according to some embodiments along such Figure 1A and Figure 1B The cross-sectional view of one of the DTI 142x of structure 105 shown by line A-A'. Figure 2A The bottom surface 245x of DTI 142x, the bottom surface 245y of DTI 142y, and the bottom surface 245c of the intersection 142c are shown. Figure 2A As shown, the bottom surface 245c may have a recess. Each bottom surface 245x of the DTI 142x includes a center 245xc, which is the midpoint between two adjacent intersections 142c.

[0075] Forming a substantially uniform bottom surface profile of the DTI is challenging due to loading effects. In some embodiments, due to the uneven profile of the bottom surface of the DTI, some portions below the bottom surface of the DTI may lie above the doped layer 112. Since these portions may not be doped with the appropriate doping distribution as the doped layer 112, leakage channels for photoexcited charge carriers in adjacent pixels 120 can be formed between these portions below the bottom surface of the DTI, thereby impairing the performance of the array of pixels 120 and the image sensor device 100.

[0076] In some embodiments, such as Figure 2A As shown, the loading effect can be mitigated by forming a substantially uniform profile of the bottom surface of DTI 142 between adjacent pixels. In some embodiments, the bottom surface 245c is more susceptible to the higher etch rate at the intersection 142c due to the loading effect. However, using subsequent... Figure 3A and Figure 3B The method 300 controls the bottom surface 245c to extend in a limited manner toward the center 245xc of the DTI 142x, such that the contour of the bottom surface 245x can remain substantially uniform. In some embodiments, the DTI 142x / 142y can extend vertically between pixels 120 to a sufficient depth such that the bottom surfaces 245x, 245y, and 245c reach the doped layer 112, and no portion of the bottom surface of the DTI is above the doped layer 112, thus avoiding the aforementioned leakage problem.

[0077] In some embodiments, bottom surfaces 245x and 245c may be joined at peak 245xp, and the distance r1 between peak 245xp and center 245xc is greater than the distance r2 between peak 245xp and nearest side surface 120s of pixel 120, such as... Figure 2A As shown. The position of peak 245xp can be considered as the boundary or edge between adjacent bottom surfaces 245x and 245c. In some embodiments, the ratio of distance r1 to distance r2 can be greater than 2:1. In some embodiments, peak 245xp is formed because the position of center 245xc is lower than the position of peak 245xp, causing bottom surface 245x to have a concave curvature, and center 245xc can be the lowest point of bottom surface 245x, such as... Figure 2AAs shown. In some embodiments, the vertical distance t1 between the center 245xc and the peak 245xp may be between about 0 nanometers (nm) and about 100 nm. In some embodiments, the distance t1 may be about 0 nm, such that the peak 245xp is not prominent, or the bottom surface 245x is substantially flat. For example, the variation of the bottom surface 245x may be less than 50 nm. In some embodiments, the vertical distance t2 between the minimum value of the center 245xc and the bottom surface 245c may be between about 300 nm and about 700 nm. In some embodiments, the vertical distance t1+t2 between the peak 245xp and the center 245xc may be between about 300 nm and about 800 nm. In some embodiments, the maximum gradient of the bottom surface 245x quantized by angle α may be less than the maximum gradient of the bottom surface 245c quantized by angle β. In some embodiments, angle α may be between about 0° and about 30°. In some embodiments, angle β may be between about 50° and about 90°. Similarly, the profile of the bottom surface 245y can be the same as or similar to the profile of the bottom surface 245x.

[0078] Please see Figures 1A to 2B In some embodiments, structure 105 may further include a gap filler 162 located above the side surfaces 120s and top surfaces 120t of pixel 120 and filling DTI 142. In some embodiments, the gap filler 162 may extend to the bottom surfaces 245x / 245y of DTI 142x / 142y and the bottom surface 245c of the intersection 142c. In some embodiments, due to the recess of the bottom surface 245c, the gap filler 162 may include a portion that is recessed and protrudes into the doped layer 112. In some embodiments, the gap filler 162 may include a dielectric material, such as silicon oxide, silicon nitride, any other suitable dielectric material, and / or combinations thereof. Structure 105 may further include a buffer layer 264 located on the gap filler 162. The buffer layer 264 may include the same or different dielectric material as the gap filler 162. In some embodiments, structure 105 may further include a filter 268 and a microlens 270 located on the buffer layer 264. In some embodiments, each filter 268 and each microlens 270 may be vertically aligned above one of the pixels 120. In some embodiments, adjacent filters 268 may be separated by a plurality of mesh structures 266. In some embodiments, the filter 268 may include a plurality of filters, such as filters configured for red, blue, and / or green light. In some embodiments, the filter 268 may include filters configured for invisible light (e.g., infrared and / or ultraviolet light). In some embodiments, the microlens 270 may be configured to focus incident light onto the pixel 120.

[0079] According to some embodiments, Figure 3A and Figure 3BThe diagram illustrates the configuration in the formation as follows Figures 1A to 2B The flowchart of method 300 with structure 105 shown is provided. This disclosure is not limited to the description of this step and additional steps may be performed. Other steps may be performed between the steps of method 300, and are omitted for clarity. Furthermore, not all steps need to perform the disclosure provided herein. Additionally, some steps may be performed simultaneously or in conjunction with... Figure 3A and Figure 3B The steps are performed in different orders as shown. In some embodiments, one or more other steps may be performed in addition to or instead of the steps currently described. For illustrative purposes, method 300 may also be referred to Figures 4A to 13 The intermediate structure shown is used for illustration. Unless otherwise stated, Figures 1A to 2B The annotations for the components also apply. Figures 4A to 13 .

[0080] Please see Figure 3A Method 300 begins with step 310, forming a doped layer in the substrate, such as... Figures 4A to 6 As shown. Figure 4A This is a top view of the semi-finished structure 105. Figure 4B , Figure 5 , Figure 6 This is a cross-sectional view of the semi-finished structure 105 (along...). Figure 4A (Line A-A'). Figure 4C This is a cross-sectional view of the semi-finished structure 105 (along...). Figure 4A (Line B-B' in the text). The structure 105 of this stage of method 300 may include a substrate 420 having a first surface 420b and a second surface 420f opposite to each other, and a doped layer 412 disposed on the substrate 420. For example, as Figures 4A to 4C As shown, a patterned mask 440 can be formed on the first surface 420b of the substrate 420, and a dopant 450 can be implanted into multiple portions of the patterned first surface 420b exposed by the mask 440 during an ion implantation method to form a doped layer 412, such that a portion of the substrate 420 beneath the first surface 420b can be doped and transformed into the doped layer 412. It should be noted that, according to... Figure 4A , Figure 4B The patterned mask 440 shown is not part of the cross-section but is viewed against the background. In some embodiments, the dopant 450 may include a p-type dopant (e.g., B, Al, Ga, and / or In) or an n-type dopant (e.g., P, As, and / or Sb). For example, the dopant 450 may include B. In some embodiments, the implantation energy of the dopant 450 may be between about 40 keV and about 80 keV to control the thickness of the doped layer 412 between about 0.3 μm and about 5 μm. In some embodiments, the implantation dose of the dopant 450 may be between about 1 × 10⁻⁶.13 cm -2 To approximately 2.5 × 10 15 cm -2 The dopant concentration of the doped layer 412 is controlled between approximately 1 × 10⁻⁶. 17 cm -3 Approximately 5×10 18 cm -3 between.

[0081] In some embodiments, step 310 may further include forming an interlayer dielectric 502 on the doped layer 412 and forming an interconnect layer in the interlayer dielectric 502, such as Figure 5 As shown. A dielectric material is deposited on the doped layer 412 to form an interlayer dielectric 502. In some embodiments, the interlayer dielectric 502 may include silicon oxide, silicon nitride, any other suitable dielectric material, and / or combinations thereof. In some embodiments, a plurality of transistors 508 may be formed in the interlayer dielectric 502 and on the doped layer 412. In some embodiments, a plurality of conductive vias 504 and a plurality of wires 506 may be formed in the interlayer dielectric 502 to electrically couple the transistors 508. The conductive vias 504 and wires 506 may be formed of conductive materials, such as copper, aluminum, tungsten, doped polysilicon, any other suitable conductive material, and / or combinations thereof. Interconnect layers may be electrically coupled to the pixels formed in the steps described later. Other circuitry and devices configured for detecting and processing photoexcited charge carriers may also be embedded in the interlayer dielectric 502 and are not shown for simplicity.

[0082] In some embodiments, step 310 may further include forming a buffer layer 608 on the interlayer dielectric 502 and forming grains 610 on the buffer layer 608, such as Figure 6 As shown. It should be noted that... Figure 6 Structure 105 has a second surface 420f along the z+ direction, and relative to Figure 5 Structure 105 has a second surface 420f that has been flipped up and down along the z-direction. Interlayer dielectric 502, buffer layer 608, and grain 610 together constitute substrate 104, as shown below. Figures 1A to 2BThe buffer layer 608 may be formed by depositing a dielectric material, such as silicon oxide, silicon nitride, any other suitable dielectric material, and / or combinations thereof. The buffer layer 608 may be formed by suitable deposition methods, such as chemical vapor deposition (CVD), plasma-enhanced CVD (PECVD), atomic layer deposition (ALD), physical vapor deposition (PVD), any other suitable process, and / or combinations thereof. The buffer layer 608 may be planarized by a planarization process (e.g., chemical mechanical polishing) to form a smooth surface. In some embodiments, the buffer layer 608 provides electrical isolation between the interlayer dielectric 502 and the die 610. In some embodiments, the die 610 may be bonded to the interlayer dielectric 502 via the buffer layer 608 using a suitable wafer bonding method, such as fusion bonding, anodic bonding, direct bonding, any other suitable bonding process, and / or combinations thereof. The die 610 provides mechanical support to the semi-finished image sensor device, enabling multiple processes to be performed on the second surface 420f. In some embodiments, the die 610 may be formed using a material similar to that of the substrate 420. In some embodiments, the die 610 may comprise a glass substrate.

[0083] Please see Figure 3A Method 300 continues with step 320, and the process of forming a patterned mask layer with cross grooves on the substrate, such as... Figures 7A to 7C As shown. Figure 7A This is a top view of the semi-finished structure 105. Figure 7B This is a cross-sectional view of the semi-finished structure 105 (along...). Figure 7A (Line A-A' in the middle). Figure 7C This is a cross-sectional view of the semi-finished structure 105 (along...). Figure 7A (Line B-B' in the diagram). For example, a mask layer 740 can be formed on the second surface 420f of the substrate 420. The mask layer 740 can be patterned through a plurality of openings 742 to expose a plurality of portions of the second surface 420f, and these portions are etched in a subsequent step to form a DTI. Specifically, the mask layer 740 has a shape similar to that shown in the diagram. Figures 4A to 4C The patterned mask 440 shown has the same pattern, and as Figure 7C As shown, opening 742 is aligned with doped layer 412 so that the DTI formed in subsequent steps can be aligned with doped layer 412. It should be noted that, according to... Figure 7A , Figure 7B The patterned mask 440 shown is not part of the cross-section but is viewed against the background. For example... Figures 7A to 7CAs shown, the opening 742 includes a plurality of slots 742x extending along the x-axis and a plurality of slots 742y extending along the y-axis, the slots 742x and 742y defining DTI 142x and 142y (e.g. Figures 1A to 2B The location is shown. Similarly, the intersection 742c of slots 742x and 742y defines intersection 142c. Therefore, the remaining portion of the second surface 420f covered by the mask layer 740 defines pixel 120.

[0084] Please see Figure 3A Method 300 continues with step 330, and follows the process of forming a DTI in the substrate using a patterned mask layer, such as... Figures 8 to 12 As shown, and Figures 8 to 12 This is a cross-sectional view of the semi-finished structure 105 (corresponding to...) Figure 7A (line A-A'). In some embodiments, step 330 may form a DTI having a substantially uniform bottom surface profile, such as Figure 2A As shown. Step 330 in Figure 3B Further details will be provided in the text.

[0085] Please see Figure 3B Step 330 begins with step 332 and involves etching the substrate exposed through the cross-grooves, as described in the following document. Figure 8 As shown. For example, etchant 840 can be used to etch multiple portions of the substrate 420 exposed through trenches 742x and 742y to form multiple DTIs 842 and multiple pixels 820. It should be noted that, according to Figure 7A , Figure 8 (and subsequently) Figures 9 to 13The pixel 820 shown is not part of the cross-section and is viewed against the background. In some embodiments, the etchant 840 may comprise a reactive plasma from a reactive ion etching process. In some embodiments, the etching may be anisotropic etching, wherein the etching rate along the vertical direction (e.g., the z-axis) is greater than the etching rate along the horizontal direction (e.g., the x-axis or y-axis), such that the etching process toward the bottom surface of DTI 842 is faster than the etching process toward the side surfaces of DTI 842. In some embodiments, an inter-stage voltage may be used to bias the substrate during the etching process. For example, a voltage between about 100V and about 400V may be used to bias the substrate 420. In some embodiments, the etchant's etching power may be between about 500W and about 1500W. In some embodiments, due to the loading effect, the bottom surface 845c corresponding to the intersection 742c can be etched at a higher etch rate than the bottom surface 845x / 845y corresponding to the groove 742x / 742y. Furthermore, because the CD of the intersection 742c is larger, the etchant 840 reaches the bottom surface more easily, thus reaching the bottom surface 845c more easily than the bottom surface 845x / 845y. In some embodiments, due to the loading effect, the bottom surface 845c may have a concave curvature, and the bottom surfaces 845x / 845y may have a convex curvature. In some embodiments, the etching process of step 332 can be stopped before the convex curvature of the bottom surfaces 845x / 845y becomes significant. For example, the etching process of step 332 can be stopped when the depth D8 of the bottom surface 845x reaches a certain value. In some embodiments, the ratio of depth D8 to distance D between the top surface of pixel 820 and doped layer 412 may be between about 0.1 and about 0.5. For example, the ratio of depth D8 to distance D may be between about 0.1 and about 0.2, between about 0.2 and about 0.3, between about 0.3 and about 0.4, and between about 0.4 and about 0.5.

[0086] Please see Figure 3B Step 330 continues to step 334, using a process of coating DTI with a polymer layer, such as... Figure 9 As shown. For example, a polymer layer 960 can be deposited on the bottom surfaces 845x / 845y and 845c and on the side surfaces of DTI 842. In some embodiments, the deposited polymer layer 960 may include a gas 950 for providing the polymer material. In some embodiments, the gas 950 may include a fluorocarbon (C) compound. x F y ), hydrofluorocarbons (C) x H y F z ), sulfur fluoride (S) x F y), hydrogen bromide (H x Br y (or combinations thereof). In some embodiments, gas 950 may include C4F8 with a flow rate between about 10 sccm and about 100 sccm. In some embodiments, gas 950 may include SF6 with a flow rate between about 100 sccm and about 600 sccm. Similar to the loading effect in step 332, because the bottom surface 845c has a larger CD, the bottom surface 845c is more readily contacted with the etchant 840 than the bottom surface 845x / 845y, and the bottom surface 845c in step 334 is also more readily contacted with gas 950 than the bottom surface 845c, thereby causing the deposited polymer layer 960 to have a greater thickness on the bottom surface 845c than on the bottom surface 845x / 845y. For example, as Figure 9 As shown, the thickness t1 of the polymer layer 960 at a first location at the midpoint of the portion of the bottom surface 845x between two adjacent DTIs extending along the y-axis can be less than the thickness t2 of the polymer layer 960 at a second location in the bottom surface 845c, and the thickness of the polymer layer 960 increases monotonically from the first location to the second location. In some embodiments, the non-uniform thickness of the polymer layer 960 on the bottom surface 845x can compensate for or balance the convex curvature of the bottom surface 845x, such that the surface 945x of the polymer layer 960 on the bottom surface 845x can have a smaller convex curvature. In some embodiments, the surface 945x can be substantially flat. In some embodiments, the surface 945x can have a concave curvature. The curvature conditions of the surface 945x can be controlled by controlling the deposition conditions of the polymer layer 960 (e.g., deposition rate and / or deposition time). In some embodiments, by utilizing a larger deposition rate and a longer deposition time, the curvature of the surface 945x can be changed from a convex curvature to a substantially flat concave curvature. In some embodiments, the coating process in step 334 can be stopped when the curvature of surface 945x reaches a condition that compensates for or balances the convex curvature of bottom surface 845x.

[0087] Please see Figure 3B Step 330 continues to step 336, a process of etching the polymer layer and substrate to increase the depth of DTI, such as... Figure 10As shown. For example, etchant 1040 can be applied to etch multiple portions of polymer layer 960 and substrate 420 to increase the depth of DTI 842 and the height of pixel 820. Unless otherwise stated, in some embodiments, etchant 1040 may be the same as or similar to etchant 840, and the description of the etching process in step 332 applies to step 334. During step 334, bottom surfaces 1045x and 1045y of DTI 842 are formed to extend along the x-axis and y-axis, respectively. A bottom surface 1045c is also formed at the intersection of bottom surfaces 1045x and 1045y. In some embodiments, due to the thickness distribution of polymer layer 960 formed in step 334, etchant 1040 in step 336 may etch bottom surfaces 1045x and 1045y to form as shown. Figure 8 The bottom surfaces 845x and 845y shown have a more uniform profile compared to the outlines of the bottom surfaces. For example, despite the loading effect, the etchant 1040 can etch a greater thickness in the substrate 420 after etching a thinner polymer layer 960 layer around the midpoint 1045xc compared to a location farther from the midpoint 1045xc and covered with a thicker polymer layer 960. Overall, the etched bottom surfaces 1045x and 1045y can have a more uniform profile than bottom surfaces 845x and 845y (e.g., ...). Figure 8 (As shown) a more uniform profile. For example, the convex curvature of bottom surfaces 1045x and 1045y may be less than that of bottom surfaces 845x and 845y. In another example, bottom surfaces 1045x and 1045y may be substantially flat. In a third example, bottom surfaces 1045x and 1045y may have concave curvature. In some embodiments, the etching process of step 336 may be stopped when the depth D10 of bottom surface 1045x reaches a certain value. In some embodiments, the ratio between depth D10 and distance D may be between about 0.2 and about 0.7. For example, the ratio between depth D10 and distance D may be between about 0.2 and about 0.3, between about 0.3 and about 0.5, and between about 0.5 and about 0.7.

[0088] Please see Figure 3B Step 330 continues to step 338, determining whether the depth of the DTI is sufficient for the bottom surface of the DTI to reach the doped layer. For example... Figures 1A to 2B If the bottom surface of the DTI is not completely etched into the doped layer, photoexcited charge carriers between pixels may leak and impair the performance of the image sensor device 100. Therefore, if the answer to the question in step 338 is "no", then step 330 is performed by repeating step 334 and coating the DTI with a polymer layer, as described in [reference]. Figure 11For example, a polymer layer 1160 may be deposited on the bottom surfaces 1045x / 1045y and 1045c and on the side surfaces of DTI 842. In some embodiments, the deposited polymer layer 1160 may include a gas 1150 for providing the polymer material. Figure 9 The description of the deposited polymer layer 960 applies to the deposition of polymer layer 1160. Then step 330 continues to step 336, a process of etching the polymer layer and substrate to increase the depth of DTI, as follows. Figure 12 As shown. For example, etchant 1240 can be applied to etch multiple portions of polymer layer 1160 and substrate 420 to increase the depth of DTI 842 and the height of pixel 820. In some embodiments, etchant 1240 can be the same as etchant 1040. In some embodiments, the coating process in step 334 and the etching process in step 336 can be repeated alternately multiple times (e.g., 2 to 5 times) until the answer to the question in step 338 is "yes". If the answer is "yes", then the entire bottom surface 1245x / 1245y and 1245c of DTI 842 has been etched into the doped layer 412, as shown. Figure 12 As shown in step 340, pixel 120 is formed to be unaffected by charge carrier leakage. Step 330 can then be completed by a removal process to remove the mask layer 740.

[0089] Please see Figure 3A Method 300 continues to step 350, a process of filling DTI with dielectric material to form multiple filters and multiple microlenses, such as... Figure 13 As shown. Figure 13 This is a cross-sectional view of structure 105 according to some embodiments. In some embodiments, forming an image sensing pixel may include forming a gap filler 162, a buffer layer 264, a mesh structure 266, a filter 268, and a microlens 270.

[0090] After gap filler 162 is formed over pixel 120 by overlay deposition, a planarization process is performed. Gap filler 162 fills DTI 842. Gap filler 162 can be formed using any suitable dielectric material, such as silicon oxide, silicon nitride, any other suitable dielectric material, and / or combinations thereof. In some embodiments, a pad layer (not shown) is formed between pixel 120 and gap filler 162. The pad layer can be formed using a high-k dielectric material, such as hafnium oxide (HfO2), tantalum pentoxide (Ta2O5), zirconium dioxide (ZrO2), aluminum oxide (Al2O3), other high-k materials, and / or combinations thereof. The material disposed in the gap filler 162 can be deposited using any suitable deposition method, such as atomic layer deposition (ALD), molecular beam epitaxy (MBE), high-density plasma CVD (HDPCVD), metal-organic CVD (MOCVD), remote plasma CVD (RPCVD), plasma-enhanced CVD (PECVD), electroplating, any other suitable method, and / or combinations thereof. After depositing the gap filler material, a planarization process (e.g., chemical mechanical polishing) is performed on the deposited gap filler material to form a flat top surface of the gap filler 162. In some embodiments, the gap filler 162 is deposited in the DTI 842 to prevent crosstalk between pixels 120.

[0091] In some embodiments, a buffer layer 264 may be formed on the top surface of the gap filler 162. After overlay deposition of the buffer material, a planarization process is performed to form the buffer layer 264 and provide a flat top surface for one or more subsequent manufacturing processes. In some embodiments, the buffer layer 264 may be the same dielectric material as the gap filler 162. In some embodiments, the buffer layer 264 may be a different dielectric material from the gap filler 162.

[0092] Mesh structure 266 is formed on buffer layer 264. In some embodiments, mesh structure 266 can be formed by depositing a metal layer on buffer layer 264 and performing a patterning process. Mesh structure 266 can be used to reduce crosstalk between pixels (e.g., between adjacent pixels) and may include a metal mesh configured to reflect light toward corresponding pixel 120. In some embodiments, mesh structure 266 is formed using a metal, such as copper, tungsten, aluminum, any other suitable metal, and / or combinations thereof. In some embodiments, mesh structure 266 is formed using any material with high reflectivity. In some embodiments, mesh structure 266 may have a stacked structure, wherein a plurality of additional dielectric grating structures are formed on mesh structure 266. In some embodiments, each mesh structure 266 may have a height between about 200 nm and about 300 nm (e.g., 200 nm to 300 nm). For example, mesh structure 266 may have a height of about 250 nm.

[0093] Multiple filters 268 may be formed on the buffer layer 264 between the mesh structure 266. Microlenses 270 may be formed above the filters 268 and the mesh structure 266. Each microlens 270 and each filter 268 are formed to be perpendicularly aligned with one of the pixels 120.

[0094] Pixel 120 is configured to sense radiation (or radiated waves), such as incident light projected toward microlens 270. The incident light enters the image sensor device 100 through the back side and can be detected by one or more pixels 120. In some embodiments, in addition to detecting visible light, the image sensor device 100 can also be configured to detect non-visible light due to the increased depth of the trench semiconductor material and reduced crosstalk between pixels.

[0095] The embodiments disclosed herein relate to the structure of a semiconductor image sensor device and a method of forming the structure. In some embodiments, the structure may include a plurality of image sensing pixels having a small critical dimension (CD) and separated by deep trench isolation (DTI) having a high aspect ratio (AR). In some embodiments, multiple portions of the DTI between adjacent image sensing pixels may have a uniform bottom surface profile to prevent photoexcited charge carrier leakage between the image sensing pixels. In some embodiments, the method may include performing an etching process and a coating process to mitigate loading effects. In some embodiments, the etching process and the coating process may be repeated alternately until the bottom surface of the DTI is etched into a doped layer beneath the image sensing pixels.

[0096] In some embodiments, a method of forming a semiconductor image sensor structure includes forming a doped layer in a substrate and forming a mask on the substrate. The mask is patterned such that it forms a first trench and a second trench having intersecting top surfaces of the substrate and exposing them. The method may further include forming a first trench and a second trench in the substrate according to the mask. Forming the first trench and the second trench includes etching the substrate, depositing a polymer layer in the first trench and the second trench, forming a bottom surface of the first trench and the second trench below the top surface of the doped layer, and forming a recess at the intersection of the first trench and the second trench. The bottom surface of the recess is lower than the bottom surface of the first trench and the bottom surface of the second trench. The edge of the recess is higher than the bottom surface of the first trench and the bottom surface of the second trench. In some embodiments, depositing the polymer layer includes: depositing a first portion of the polymer layer at a first deposition rate on the bottom surface of the first trench and the bottom surface of the second trench; and depositing a second portion of the polymer layer in the recess at a second deposition rate greater than the first deposition rate. In some embodiments, depositing the polymer layer includes: depositing a first portion of the polymer layer on the bottom surface of a first trench at a first deposition rate; and depositing a second portion of the polymer layer on the bottom surface of the first trench at a second deposition rate greater than the first deposition rate, wherein the second portion is located between the first portion and the recess. In some embodiments, depositing the polymer layer includes depositing a fluorocarbon compound (C). x F y ), hydrofluorocarbons (C) x H y F z ), sulfur fluoride (S) x F y ), or hydrogen bromide (H x Br y In some embodiments, forming the first trench and the second trench includes forming the first trench and the second trench having an aspect ratio between about 5 and about 50. In some embodiments, forming the first trench and the second trench includes forming the first trench and the second trench with a depth between about 0.5 micrometers and about 5 micrometers. In some embodiments, forming the recess includes forming the recess having a first width; and forming the first trench and the second trench includes forming the first trench and the second trench with a second width, wherein the ratio of the first width to the second width is between about 1 and about 3.

[0097] In some embodiments, a method of forming a semiconductor image sensor structure includes forming a doped layer in a substrate; etching the substrate to form a first trench and a second trench; depositing a polymer layer in the first trench and the second trench; increasing the depth of the first trench and the second trench by etching the polymer layer and a portion of the substrate in the first trench and the second trench until the depth is greater than the distance between the doped layer and the top surface of the substrate; and forming a recess at the intersection of the first trench and the second trench, while increasing the depth of the first trench and the second trench. The edge of the recess is located above the bottom surface of the first trench and the second trench. In some embodiments, the method further includes forming a third trench that intersects the first trench and is parallel to the second trench, and the ratio of the distance between the second trench and the third trench to the width of the second trench is between about 2 and about 10. In some embodiments, the distance between the second trench and the third trench is between about 0.5 micrometers and about 5 micrometers. In some embodiments, the method further includes forming another recess at the intersection of the first trench and the third trench, and the distance between the second recess and the third recess is less than the distance between the second trench and the third trench. In some embodiments, forming a recess includes forming a side surface of the recess, and the angle between the side surface of the recess and the top surface of the substrate is between about 50° and about 90°. In some embodiments, etching the polymer layer includes etching a first portion of the polymer layer in the recess at a first rate, and etching a second portion of the polymer layer in the first trench and the second trench at a second rate less than the first rate. In some embodiments, forming a doped layer includes performing an ion implantation process on the back surface of the substrate.

[0098] In some embodiments, a semiconductor image sensor structure includes a doped layer disposed on a substrate; a first radiation sensing region, a second radiation sensing region, a third radiation sensing region, and a fourth radiation sensing region disposed on the substrate, wherein the doped layer surrounds the lower portions of the first radiation sensing region, the lower portions of the second radiation sensing region, the lower portions of the third radiation sensing region, and the lower portions of the fourth radiation sensing region; and a first trench and a second trench intersecting and separating the first radiation sensing region, the second radiation sensing region, the third radiation sensing region, and the fourth radiation sensing region. The first trench and the second trench extend vertically to the top surface of the doped layer. The structure may further include a recess located at the intersection of the first trench and the second trench. The bottom surface of the recess is located below the bottom surfaces of the first trench and the second trench. The edge of the recess is located above the bottom surfaces of the first trench and the second trench. In some embodiments, the angle between the side surface of this portion of the dielectric layer and the top surface of the substrate is between about 50° and about 90°. In some embodiments, the ratio of the width of the first radiation sensing region to the width of the first trench is between about 2 and about 10. In some embodiments, the vertical difference between the bottom surface of the first trench and the bottom surface of that portion of the dielectric layer is between about 300 nanometers and about 800 nanometers. In some embodiments, the aspect ratios of the first trench and the second trench are between about 10 and about 50. In some embodiments, the variation of the bottom surface of the first trench is less than about 50 nanometers.

[0099] In some embodiments, a semiconductor image sensor structure includes a doped layer disposed on a substrate; a first pixel, a second pixel, a third pixel, and a fourth pixel disposed on the substrate, wherein the doped layer surrounds the lower portion of the first pixel, the lower portion of the second pixel, the lower portion of the third pixel, and the lower portion of the fourth pixel; a first trench and a second trench that intersect and separate the first pixel, the second pixel, the third pixel, and the fourth pixel, wherein the bottom surface of the first trench and the bottom surface of the second trench are lower than the top surface of the doped layer, and the intersection of the first trench and the second trench includes a recess, the bottom surface of the recess being lower than the bottom surfaces of the first trench and the second trench, and the edge of the recess being above the bottom surfaces of the first trench and the second trench; and a dielectric layer disposed in the first trench and the second trench, having a portion protruding into the doped layer, wherein the portion is located at the intersection of the first trench and the second trench. In some embodiments, the first trench and the second trench have an aspect ratio between 5 and 50. In some embodiments, the recess includes a first width; and the first trench and the second trench include trenches having a second width, wherein the ratio of the first width to the second width is between 1 and 3. In some embodiments, the first trench and the second trench each include a depth between 0.5 micrometers and 5 micrometers.

[0100] In some embodiments, a conductor image sensor structure includes a doped layer disposed on a substrate; a first pixel, a second pixel, a third pixel, and a fourth pixel disposed on the substrate, wherein the doped layer surrounds the lower portion of the first pixel, the lower portion of the second pixel, the lower portion of the third pixel, and the lower portion of the fourth pixel; a first trench and a second trench that intersect and separate the first pixel, the second pixel, the third pixel, and the fourth pixel, wherein the intersection of the first trench and the second trench includes a recess; and a dielectric layer disposed in the first trench and the second trench, wherein the first trench and the second trench each include a depth greater than the distance between the doped layer and the top surface of the substrate, and wherein the edge of the recess is located above the bottom surface of the first trench and the second trench. In some embodiments, the semiconductor image sensor structure further includes a third trench that intersects the first trench and is parallel to the second trench, wherein the ratio of the distance between the second trench and the third trench to the width of the second trench is between 2 and 10. In some embodiments, the intersection of the first trench and the third trench includes another recess, wherein the distance between the second recess and the third recess is less than the distance between the second trench and the third trench. In some embodiments, the recess includes a recessed side surface, and wherein the angle between the recessed side surface and the top surface of the substrate is between 50° and 90°.

[0101] It should be understood that the implementation portion, rather than the abstract portion, is intended to be configured to interpret the claims. The abstract portion of this disclosure may illustrate one or more, but not all, possible embodiments of this disclosure as conceived by the author, and therefore is not intended to limit the appended claims in any way.

[0102] The foregoing has outlined features of several embodiments to enable those skilled in the art to better understand the various embodiments disclosed herein. Those skilled in the art should understand that they can simply use this disclosure as a basis for designing or modifying other processes and structures to achieve the same purpose and / or the same advantages as the embodiments described herein. Those skilled in the art should also understand that such equivalent constructions do not depart from the spirit and scope of this disclosure, and that they can make various changes, substitutions, and alterations without departing from the spirit and scope of this disclosure.

Claims

1. A semiconductor image sensor structure, characterized in that, include: A doped layer is disposed on a substrate; A first pixel, a second pixel, a third pixel, and a fourth pixel are disposed on the substrate, wherein the doped layer surrounds a lower portion of the first pixel, a lower portion of the second pixel, a lower portion of the third pixel, and a lower portion of the fourth pixel. A first trench and a second trench intersect each other and separate the first pixel, the second pixel, the third pixel, and the fourth pixel. A bottom surface of the first trench and a bottom surface of the second trench are lower than a top surface of the doped layer. A recess is included at an intersection of the first trench and the second trench. The bottom surface of the recess is lower than the bottom surface of the first trench and the bottom surface of the second trench, and an edge of the recess is higher than the bottom surface of the first trench and the bottom surface of the second trench. as well as A dielectric layer is disposed in the first trench and the second trench, and has a portion protruding into the doped layer, wherein the portion is located at the intersection of the first trench and the second trench.

2. The semiconductor image sensor structure as described in claim 1, characterized in that, The first trench and the second trench each include a depth-to-width ratio between 5 and 50.

3. The semiconductor image sensor structure as described in claim 1, characterized in that: The recess includes a first width; and The first groove and the second groove each include a second width, wherein a ratio of the first width to the second width is between 1 and 3.

4. The semiconductor image sensor structure as described in claim 1, characterized in that, The first trench and the second trench each have a depth between 0.5 micrometers and 5 micrometers.

5. A semiconductor image sensor structure, characterized in that, include: A doped layer is disposed in a substrate; A first pixel, a second pixel, a third pixel, and a fourth pixel are disposed on the substrate, wherein the doped layer surrounds a lower portion of the first pixel, a lower portion of the second pixel, a lower portion of the third pixel, and a lower portion of the fourth pixel. A first trench and a second trench intersect each other and separate the first pixel, the second pixel, the third pixel, and the fourth pixel, wherein an intersection of the first trench and the second trench includes a recess; and A dielectric layer is disposed in the first trench and the second trench, wherein the first trench and the second trench each include a depth, and the depth is greater than a distance between the doped layer and a top surface of the substrate. One edge of the recess is located above the bottom surface of the first groove and the second groove.

6. The semiconductor image sensor structure as described in claim 5, characterized in that, Further includes: A third groove intersects the first groove and is parallel to the second groove, wherein the ratio of a distance between the second groove and the third groove to a width of the second groove is between 2 and 10.

7. The semiconductor image sensor structure as described in claim 6, characterized in that, The intersection of the first groove and the third groove includes another depression, wherein a distance between the second depression and the third depression is less than the distance between the second groove and the third groove.

8. The semiconductor image sensor structure as described in claim 5, characterized in that, The recess includes a side surface of the recess, and an angle between the side surface of the recess and the top surface of the substrate is between 50° and 90°.

9. A semiconductor image sensor structure, characterized in that, include: A doped layer is disposed on a substrate; A first radiation sensing region, a second radiation sensing region, a third radiation sensing region, and a fourth radiation sensing region are disposed on the substrate, wherein the doped layer surrounds a lower portion of the first radiation sensing region, a lower portion of the second radiation sensing region, a lower portion of the third radiation sensing region, and a lower portion of the fourth radiation sensing region. A first trench and a second trench intersect each other and separate the first radiation sensing region, the second radiation sensing region, the third radiation sensing region, and the fourth radiation sensing region, wherein the first trench and the second trench extend vertically to a top surface of the doped layer. as well as A dielectric layer fills the first trench and the second trench, and has a portion protruding into the doped layer, wherein the portion is located at an intersection of the first trench and the second trench.

10. The semiconductor image sensor structure as described in claim 9, characterized in that, The variation on the bottom surface of the first trench is less than 50 nanometers.

Images