A packaging structure and electronic device for a superconducting quantum chip

Abstract

This application provides a packaging structure and electronic device for a superconducting quantum chip, relating to the field of superconducting quantum technology. An electromagnetic shielding sealing ring is formed around the functional circuit region on the superconducting quantum chip, achieving electromagnetic shielding. A surface electromagnetic shielding layer is fabricated on the two side walls of the sealing ring and on the surface facing away from the superconducting quantum chip, improving the bonding strength between the electromagnetic shielding sealing ring and the superconducting quantum chip, and enhancing the reliability of the packaging structure. A sealed cavity encapsulating the functional circuit region is also formed between the superconducting quantum chip, the electromagnetic shielding sealing ring, and the control chip. This not only enables control of the welding spacing between the superconducting quantum chip and the control chip through the electromagnetic shielding sealing ring, but also achieves hermetic encapsulation of the superconducting quantum chip. This prevents oxidation and chemical corrosion of the superconducting material in the superconducting quantum chip at low temperatures, improving the low-temperature performance of the superconducting quantum chip and enhancing its overall performance and reliability.

Description

Technical Field

[0001] This application relates to the field of superconducting quantum technology, and more specifically, to a packaging structure and electronic device for a superconducting quantum chip. Background Technology

[0002] The coherence and gate fidelity of qubits in superconducting quantum chips are highly sensitive to electromagnetic interference (EMI). Therefore, achieving effective electromagnetic shielding is crucial for the performance and reliability of superconducting qubits. Traditional packaging methods for superconducting quantum chips typically use encapsulation boxes and external magnetic shielding barrels from dilution coolers for EMI shielding. While this can reduce external interference to some extent, it cannot effectively shield against EMI within the chip device itself. Utility Model Content

[0003] In view of this, this application provides a packaging structure and electronic device for a superconducting quantum chip, which effectively solves the existing technical problems. It not only realizes the electromagnetic shielding function of the superconducting quantum chip, but also realizes the welding interval control between the superconducting quantum chip and the control chip, and realizes the hermetic packaging of the superconducting quantum chip, thereby improving the performance and reliability of the superconducting quantum chip.

[0004] To achieve the above objectives, the technical solution provided in this application is as follows:

[0005] A packaging structure for a superconducting quantum chip, comprising:

[0006] A superconducting quantum chip, wherein one side surface of the superconducting quantum chip includes a functional circuit region and an edge sealing region surrounding the functional circuit region;

[0007] A control chip is welded and fixed to the superconducting quantum chip.

[0008] An electromagnetic shielding sealing ring is located between the superconducting quantum chip and the control chip. The electromagnetic shielding sealing ring includes a sealing ring located on the edge sealing area and surrounding the functional circuit area, and a surface electromagnetic shielding layer deposited on the exposed surface of the sealing ring. A sealing cavity is formed between the superconducting quantum chip, the electromagnetic shielding sealing ring and the control chip.

[0009] Optionally, the sealing ring is a sealing photoresist ring. Optionally, the packaging structure further includes:

[0010] An electromagnetic shielding connection located in the edge sealing area and penetrating the superconducting quantum chip;

[0011] and a back electromagnetic shielding layer located on the surface of the superconducting quantum chip away from the electromagnetic shielding sealing ring, wherein the electromagnetic shielding sealing ring and the back electromagnetic shielding layer are connected by the electromagnetic shielding connection portion.

[0012] Optionally, the surface electromagnetic shielding layer includes an inner connection portion close to the functional circuit area and an outer connection portion away from the functional circuit area;

[0013] The electromagnetic shielding connection includes a plurality of first electromagnetic shielding connection posts and a plurality of second electromagnetic shielding connection posts. The first electromagnetic shielding connection posts are in contact with the inner connection part, and the second electromagnetic shielding connection posts are in contact with the outer connection part. At least some of the first electromagnetic shielding connection posts and the second electromagnetic shielding connection posts are arranged opposite to each other on both sides of the sealing ring.

[0014] Optionally, the surface electromagnetic shielding layer includes an inner connection portion close to the functional circuit area and an outer connection portion away from the functional circuit area;

[0015] The electromagnetic shielding connection includes a plurality of first electromagnetic shielding connection posts and a plurality of second electromagnetic shielding connection posts. The first electromagnetic shielding connection posts are in contact with the inner connection part, and the second electromagnetic shielding connection posts are in contact with the outer connection part. At least some of the first electromagnetic shielding connection posts and the second electromagnetic shielding connection posts are staggered on both sides of the sealing ring.

[0016] Optionally, the surface electromagnetic shielding layer includes an inner connection portion close to the functional circuit area and an outer connection portion away from the functional circuit area;

[0017] The electromagnetic shielding connection includes at least one of a first electromagnetic shielding connection ring and a second electromagnetic shielding connection ring. Both the first electromagnetic shielding connection ring and the second electromagnetic shielding connection ring surround the functional circuit area. The first electromagnetic shielding connection ring is in contact with the inner connection portion, and the second electromagnetic shielding connection ring is in contact with the outer connection portion.

[0018] Optionally, the electromagnetic shielding connection includes a connection layer and a seed layer surrounding the connection layer in a direction parallel to the plane where the superconducting quantum chip is located.

[0019] Optionally, the packaging structure further includes an insulating layer located between the sidewall of the electromagnetic shielding connection and the superconducting quantum chip.

[0020] Optionally, the sealing cavity is used to fill an inert gas, or the sealing cavity is a vacuum sealing cavity.

[0021] Based on the same inventive concept, this application also provides an electronic device, which includes the above-described packaging structure of the superconducting quantum chip.

[0022] Compared with existing technologies, the technical solution provided in this application has at least the following advantages:

[0023] This application provides a packaging structure for a superconducting quantum chip and an electronic device. The packaging structure includes: a superconducting quantum chip, one side surface of which includes a functional circuit area and an edge sealing area surrounding the functional circuit area; a control chip, which is welded and fixed to the superconducting quantum chip; and an electromagnetic shielding sealing ring, which is located between the superconducting quantum chip and the control chip. The electromagnetic shielding sealing ring includes a sealing ring located on the edge sealing area and surrounding the functional circuit area, and a surface electromagnetic shielding layer deposited on the exposed surface of the sealing ring. A sealed cavity is formed between the superconducting quantum chip, the electromagnetic shielding sealing ring, and the control chip. Solder joints at the functional circuit area and corresponding solder joints of the control chip are welded and fixed and located within the sealed cavity.

[0024] As described above, the technical solution provided in this application forms an electromagnetic shielding sealing ring around the functional circuit area on the superconducting quantum chip, thereby creating an electromagnetic shielding structure around the functional circuit of the superconducting quantum chip and realizing its electromagnetic shielding function. Furthermore, by fabricating a surface electromagnetic shielding layer on both sides of the sealing ring and on the surface facing away from the superconducting quantum chip, the bonding strength between the electromagnetic shielding sealing ring and the superconducting quantum chip is further improved, based on the electromagnetic shielding achieved by the sealing ring, thus enhancing the reliability of the packaging structure. In addition, a sealed cavity encapsulating the functional circuit area is formed between the superconducting quantum chip, the electromagnetic shielding sealing ring, and the control chip. This not only controls the welding spacing between the superconducting quantum chip and the control chip through the electromagnetic shielding sealing ring but also achieves hermetically sealed packaging of the superconducting quantum chip. This prevents oxidation and chemical corrosion of the superconducting material in the superconducting quantum chip at low temperatures, improves the long-term stability of the superconducting quantum chip in the dilution refrigerator, enhances the low-temperature performance of the superconducting quantum chip, and improves its overall performance and reliability. Attached Figure Description

[0025] To more clearly illustrate the technical solutions in the embodiments of this application or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only embodiments of this application. For those skilled in the art, other drawings can be obtained based on the provided drawings without creative effort.

[0026] Figure 1A flowchart illustrating a packaging method for a superconducting quantum chip provided in this application embodiment;

[0027] Figure 2 A schematic diagram of the packaging structure of a superconducting quantum chip provided in an embodiment of this application;

[0028] Figure 3 A flowchart illustrating another packaging method for a superconducting quantum chip provided in this application embodiment;

[0029] Figure 4 A schematic diagram of another packaging structure for a superconducting quantum chip provided in an embodiment of this application;

[0030] Figures 5 to 9 for Figure 3 A structural diagram of the middle part of the steps;

[0031] Figure 10 This is a schematic diagram of the structure of an electromagnetic shielding connection provided in an embodiment of this application;

[0032] Figure 11 A connection structure diagram of an electromagnetic shielding connection part and a surface electromagnetic shielding layer provided in an embodiment of this application;

[0033] Figure 12 A connection structure diagram of another electromagnetic shielding connection part and surface electromagnetic shielding layer provided in an embodiment of this application;

[0034] Figure 13 A connection structure diagram of another electromagnetic shielding connection part and surface electromagnetic shielding layer provided in an embodiment of this application;

[0035] Figure 14 This is a schematic diagram of the packaging structure of another superconducting quantum chip provided in an embodiment of this application.

[0036] Figure label:

[0037] 100 - Superconducting quantum chip; 200 - Control chip; 210 - Shielding part; 310 - Electromagnetic shielding sealing ring; 311 - Sealing ring; 312 - Surface electromagnetic shielding layer; 3121 - Inner connection part; 3122 - Outer connection part; 320 - Electromagnetic shielding connection part; 321 - Seed layer; 322 - Connection layer; 3201 - First electromagnetic shielding connecting post; 3202 - Second electromagnetic shielding connecting post; 3203 - First electromagnetic shielding connecting ring; 3204 - Second electromagnetic shielding connecting ring; 330 - Back electromagnetic shielding layer; 400 - Sealing cavity; 500 - Welding post; A1 - Functional circuit area; A2 - Edge sealing area. Detailed Implementation

[0038] The technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this application, and not all embodiments. Based on the embodiments of this application, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this application.

[0039] As described in the background section, the coherence and gate fidelity of qubits in superconducting quantum chips are highly sensitive to electromagnetic interference (EMI). Therefore, achieving effective electromagnetic shielding is crucial for the performance and reliability of superconducting qubits. Traditional packaging methods for superconducting quantum chips typically use packaging boxes and external magnetic shielding barrels from dilution coolers for EMI shielding. While this can reduce external interference to some extent, it cannot effectively shield against EMI within the chip device itself.

[0040] Based on this, the embodiments of this application provide a packaging method, packaging structure and electronic device for a superconducting quantum chip, which effectively solves the existing technical problems. It not only realizes the electromagnetic shielding function of the superconducting quantum chip, but also realizes the welding interval control between the superconducting quantum chip and the control chip, and realizes the hermetic packaging of the superconducting quantum chip, thereby improving the performance and reliability of the superconducting quantum chip.

[0041] To achieve the above objectives, the technical solutions provided in this application are as follows, in specific combination with... Figures 1 to 14 The technical solutions provided in the embodiments of this application will be described in detail.

[0042] Combination Figure 1 and Figure 2 As shown, Figure 1 A flowchart illustrating a packaging method for a superconducting quantum chip provided in this application embodiment. Figure 2 This is a schematic diagram of a packaging structure for a superconducting quantum chip provided in an embodiment of this application. The packaging method for the superconducting quantum chip includes:

[0043] S1. A superconducting quantum chip 100 and a control chip 200 are provided. One surface of the superconducting quantum chip 100 includes a functional circuit region A1 and an edge sealing region A2 surrounding the functional circuit region A1. That is, after the superconducting quantum chip 100 and the control chip 200 are soldered together, the surface of the superconducting quantum chip 100 facing the control chip 200 includes the functional circuit region A1 and the edge sealing region A2.

[0044] S2. A sealing ring 311 is formed on the edge sealing area A2, surrounding the functional circuit area A1.

[0045] S3. A surface electromagnetic shielding layer 312 is deposited on the exposed surface of the sealing ring 311, wherein the sealing ring 311 and the surface electromagnetic shielding layer 312 are combined to form an electromagnetic shielding sealing ring 310.

[0046] S4. The superconducting quantum chip 100 and the control chip 200 are welded and fixed relative to each other, forming a sealed cavity 400 between the superconducting quantum chip 100, the electromagnetic shielding sealing ring 310, and the control chip 200. The welding of the superconducting quantum chip 100 and the control chip 200 involves welding and fixing the solder joint at the functional circuit region A1 of the superconducting quantum chip 100 to the corresponding solder joint of the control chip 200, placing them within the sealed cavity 400; and welding and fixing the electromagnetic shielding sealing ring 310 of the superconducting quantum chip 100 to the shielding portion 210 of the control chip 200. The solder joint at the functional circuit region A1 is welded and fixed to the corresponding solder joint of the control chip 200, placing them within the sealed cavity 400. Figure 2 The welding post 500 illustrates the welding relationship between the solder joint at functional circuit area A1 and the solder joint of the control chip 200. The welding post 500 is located within the sealed cavity 400. The shielding portion 210 of the control chip 200 includes at least a portion of the ground electrode on the side of the control chip 200 facing the superconducting quantum chip 100, which is welded and fixed to the electromagnetic shielding sealing ring 310.

[0047] In some embodiments, the solder joints of the superconducting quantum chip 100 (i.e., the solder joints at functional circuit region A1) and the solder joints of the control chip 200 provided in this application can be a soldering area used only to illustrate the soldering connection. When soldering the solder joints at functional circuit region A1 and the solder joints of the control chip 200, solder can be placed at the solder joints at functional circuit region A1, or solder can be placed at both the solder joints at functional circuit region A1 and the solder joints of the control chip 200. Then, the solder joints at functional circuit region A1 and the solder joints of the control chip 200 are aligned and soldered to form a solder pillar 500. Alternatively, the solder joints at functional circuit region A1 and the solder joints of the control chip 200 can not only be a soldering area used to illustrate the soldering connection, but also be substantially provided with solder. During the soldering process, the solder joints at functional circuit region A1 and the solder joints of the control chip 200 can be directly soldered to form a solder pillar 500. This application does not impose specific limitations on this. Optionally, the bonding solder can be In (indium), which is soft and can reduce damage to the chip during soldering.

[0048] Understandably, the technical solution provided in this application forms an electromagnetic shielding sealing ring 310 around the functional circuit region A1 on the superconducting quantum chip 100, thereby forming an electromagnetic shielding structure around the functional circuit of the superconducting quantum chip 100 and realizing the electromagnetic shielding function of the superconducting quantum chip 100. Furthermore, a surface electromagnetic shielding layer 312 is fabricated on both sides of the sealing ring 311 and on the surface facing away from the superconducting quantum chip 100. Based on the electromagnetic shielding achieved by the electromagnetic shielding sealing ring 310, the bonding strength between the electromagnetic shielding sealing ring 310 and the superconducting quantum chip 100 is further improved, thereby enhancing the reliability of the packaging structure. Furthermore, a sealed cavity 400 encapsulating the functional circuit area is formed between the superconducting quantum chip 100, the electromagnetic shielding sealing ring 310, and the control chip 200. This not only enables control of the welding interval between the superconducting quantum chip 100 and the control chip 200 through the electromagnetic shielding sealing ring 310, but also achieves hermetic encapsulation of the superconducting quantum chip 100. This prevents oxidation and chemical corrosion of the superconducting material of the superconducting quantum chip 100 in low-temperature environments, improves the long-term stability of the superconducting quantum chip 100 in the dilution refrigerator, enhances the low-temperature performance of the superconducting quantum chip 100, and improves the performance and reliability of the superconducting quantum chip 100.

[0049] Combination Figure 3 and Figure 4 As shown, Figure 3 A flowchart illustrating another packaging method for a superconducting quantum chip provided in this application embodiment. Figure 4 This is a schematic diagram of another packaging structure for a superconducting quantum chip provided in an embodiment of this application. After forming the surface electromagnetic shielding layer 312 in step S3, and before welding and fixing the superconducting quantum chip 100 and the control chip 200 relative to each other in step S4, the packaging method further includes:

[0050] S03. An electromagnetic shielding connection portion 320 is formed at the edge sealing area A2, penetrating the superconducting quantum chip 100.

[0051] S04. A back electromagnetic shielding layer 330 is formed on the surface of the superconducting quantum chip 100 opposite to the electromagnetic shielding sealing ring 310. The electromagnetic shielding sealing ring 310 and the back electromagnetic shielding layer 330 are connected through the electromagnetic shielding connection portion 320. Specifically, the back electromagnetic shielding layer 330 and the electromagnetic shielding sealing ring 310 are formed around the superconducting quantum chip 100, and are connected through the electromagnetic shielding connection portion 320 penetrating the superconducting quantum chip 100. This forms an electromagnetic shielding structure around the functional circuitry of the superconducting quantum chip 100, further improving the electromagnetic shielding function of the packaged superconducting quantum chip 100.

[0052] The following is combined Figures 5 to 13 The encapsulation method provided in the embodiments of this application will be described in more detail. Figures 5 to 9 for Figure 1 A schematic diagram of the corresponding structure for some of the steps.

[0053] As shown in the figure, corresponding to step S2, a sealing ring 311 surrounding the functional circuit area A1 is formed on the edge sealing area A2. In some embodiments, the formation of the sealing ring 311 surrounding the functional circuit area A1 on the edge sealing area A2 provided in this application embodiment includes: forming a sealing ring 311 made of photoresist on the edge sealing area A2 and surrounding the functional circuit area A1, which improves the performance of the electromagnetic shielding sealing ring 310 itself and further improves the reliability of the packaging structure of the superconducting quantum chip 100. The sealing ring 311 provided in this application embodiment can be made of negative photoresist, such as SU-8, AZ5214, etc. Firstly, the sealing ring 311 formed by the photoresist can achieve a sealing function due to its dense cross-linked structure. After UV exposure, photoresist forms a three-dimensional cross-linked network structure (epoxy cross-linking). The resulting sealing ring 311, formed after curing, has extremely low porosity, effectively isolating moisture, oxygen, and contaminants. Therefore, the photoresist-formed sealing ring 311 ensures excellent airtightness of the sealed cavity 400. This prevents oxidation and deterioration of the functional circuitry due to contact with the atmospheric environment during the storage phase after the superconducting quantum chip 100 is packaged, thus avoiding changes in operating parameters, performance degradation, and lifespan reduction of the superconducting quantum chip 100. Simultaneously, the excellent airtightness of the sealed cavity 400 composed of the photoresist-made sealing ring 311 also prevents oxidation and chemical corrosion of the superconducting materials (such as niobium or aluminum) of the superconducting quantum chip 100 at low temperatures, improving the long-term stability of the superconducting quantum chip 100 in dilution refrigerators (mK-level temperatures). Secondly, the photoresist-formed sealing ring 311 exhibits low hygroscopicity and high environmental adaptability. The photoresist has a low moisture absorption rate (less than 0.1%), allowing it to maintain stable mechanical and dielectric properties in humid environments and avoiding performance degradation caused by moisture penetration. Combined with the photoresist's thermal stability (heat resistance temperature greater than 200℃), the sealing ring 311 can withstand thermal cycling shocks, reducing the risk of interface cracking caused by thermal stress. Thirdly, the photoresist-formed sealing ring 311 is compatible with low-temperature processes. The photoresist has a low curing shrinkage rate (less than 5%), and by optimizing the baking process, stress accumulation can be further reduced. This mitigates the difference in thermal expansion coefficients between the photoresist-formed sealing ring 311 and the superconducting quantum chip 100 during chip bonding, preventing seal failure due to temperature changes.

[0054] The process of forming a photoresist-based sealing ring 311 around the functional circuit area A1 on the edge sealing area A2, as provided in this embodiment, specifically includes:

[0055] Step S21: A first photoresist layer is spin-coated onto one side of the functional circuit region A1 of the superconducting quantum chip 100, and then subjected to a first baking. A negative photoresist such as SU-8 or AZ5214 is selected. The spin-coating equipment is used at 1000-5000 rpm for 60-180 seconds, followed by a resting period of 5-10 minutes to eliminate air bubbles, thus forming a first photoresist layer on the surface of the functional circuit region A1 of the superconducting quantum chip 100. The first photoresist layer is then subjected to a first baking, which can be a soft baking process, specifically baking on a hot plate at 75-95°C for 180-300 seconds.

[0056] Step S22: Expose the first photoresist layer and perform a second baking. Use an LED (light-emitting diode) light source, align with a contact mask, or use a laser direct-write device to expose the first photoresist layer. The exposure dose can be 200-500 mJ / cm². 2 The LED light source is ultraviolet light, such as with a wavelength of 365nm. Then, the first photoresist layer is baked a second time. This second baking is a post-baking process and can be done in stages. Specifically, the second baking involves first baking with a hot plate at 65-95℃ for 60-180 seconds, followed by baking with a hot plate at 95-115℃ for 300-600 seconds.

[0057] Step S23: Develop the first photoresist layer using a developing solution to form a photoresist ring. The photoresist ring is located on the edge sealing area A2 and surrounds the functional circuit area A1, and then undergoes a third baking. The superconducting quantum chip 100 with the first photoresist layer is immersed in the developing solution for 90-180 seconds, and then alternately rinsed with isopropanol until no residue remains, completing the development process. The developing solution can be MR-Dev600. Then, the resulting photoresist ring undergoes a third baking, which is a hard baking, i.e., baking at 180-250℃ for 900-1800 seconds. This three-baking method enhances the mechanical strength of the prepared photoresist ring.

[0058] Step S24: Immerse the superconducting quantum chip in an intermediate solvent to replace the residual developer on the superconducting quantum chip. After rinsing the superconducting quantum chip 100, immerse it in the intermediate solvent for 10-15 minutes. The intermediate solvent can be ethanol or acetone, thereby replacing the residual developer. This replacement step can be performed once or repeated multiple times. That is, one replacement of the residual developer takes 10-15 minutes, and this replacement step can be repeated multiple times, such as three times, to ensure complete replacement of the residual developer.

[0059] Step S25: Perform a critical point drying process on the superconducting quantum chip 100 to form the sealing ring 311, thereby removing residual solution from the superconducting quantum chip 100. Specifically, transfer the superconducting quantum chip 100 to a high-pressure drying chamber and slowly inject liquid CO2 (purity not less than 99.99%), immersing the superconducting quantum chip 100 in the liquid CO2. The CO2 flow rate can be controlled at 0.5 L / min to avoid mechanical impact on the superconducting quantum chip 100 and structural damage. This step can be repeated multiple times. The immersion time of the superconducting quantum chip 100 in liquid CO2 can be controlled to 5 minutes each time. Then, the liquid CO2 is removed and re-injected according to the above steps. This step is repeated 5-8 times to ensure that the residual solution concentration is less than 0.1%.

[0060] like Figure 6 As shown, corresponding to step S3, a surface electromagnetic shielding layer 312 is deposited on the exposed surface of the sealing ring 311. The surface electromagnetic shielding layer 312 covers the surface of the sealing ring 311 facing away from the superconducting quantum chip 100, and also covers the sidewalls of the sealing ring 311 near and away from the functional circuit region A1. The sealing ring 311 and the surface electromagnetic shielding layer 312 together form an electromagnetic shielding sealing ring 310. That is, after the sealing ring 311 is prepared, a surface electromagnetic shielding layer 312 needs to be covered on the surface of the sealing ring 311 facing away from the superconducting quantum chip 100 and on its sidewalls. The deposition of the surface electromagnetic shielding layer 312 on the exposed surface of the sealing ring 311, as provided in this embodiment, includes:

[0061] Step S31: A surface mask layer is formed on the side of the superconducting quantum chip 100 where the sealing ring 311 is formed. The surface mask layer exposes the surface and sidewalls of the sealing ring 311. The sidewalls of the sealing ring 311 include the sidewalls near the functional circuit region A1 and the sidewalls away from the functional circuit region A1. Optionally, the surface mask layer provided in this embodiment can be formed using a photolithography process. Specifically, it may include: Step S261: A second photoresist layer is spin-coated on the side of the superconducting quantum chip 100 where the sealing ring 311 is formed, and a first baking is performed. A photoresist such as AZ5214 is selected. The spin-coating equipment rotates at 2000-3000 rpm for 60-180 seconds, and then rests for 5-10 minutes to eliminate air bubbles. Then, a second photoresist layer is spin-coated on the side of the superconducting quantum chip 100 where the electromagnetic shielding sealing ring 310 is formed, and the second photoresist layer covers the electromagnetic shielding sealing ring 310. Then, the second photoresist layer undergoes a first baking process, which can be a soft baking process, specifically baking on a hot plate at 75-95°C for 180-300 seconds. Step S262: The second photoresist layer is exposed and then baked a second time. An LED light source is selected, and the second photoresist layer is exposed using a contact mask or a laser direct-write device. The exposure dose can be 200-500 mJ / cm². 2 The LED light source is ultraviolet light, such as with a wavelength of 365nm. The second photoresist layer is then baked a second time, which is a post-baking process and can be done in stages. Specifically, the second baking involves first baking at 65-95℃ for 60-180 seconds, followed by baking at 95-115℃ for 300-600 seconds. Step S263: The second photoresist layer is developed using a developer to form a surface mask layer. This surface mask layer exposes the surface and sidewalls of the sealing ring 311, and is then baked a third time. The superconducting quantum chip 100 with the second photoresist layer is immersed in the developer for 90-180 seconds, and then alternately rinsed with isopropanol until no residue remains, completing the development process. The developer can be MR-Dev600 developer. The resulting surface mask layer is then baked a third time, which is a hard bake, specifically baking at 180-250℃ for 900-1800 seconds. This three-baking process enhances the mechanical strength of the prepared surface mask layer.

[0062] Step S32: Control the superconducting quantum chip 100 to rotate along its rotation axis perpendicular to its plane, and / or control the superconducting quantum chip 100 to swing in a direction perpendicular to its plane, while simultaneously depositing a surface electromagnetic shielding layer 312 on the exposed surface of the sealing ring 311 based on the surface mask layer. Specifically, after obtaining the superconducting quantum chip 100 carrying the surface mask layer as described above, the corresponding sample of the superconducting quantum chip 100 can first be cleaned with ultrasound, such as by cleaning with acetone and anhydrous ethanol for 15 minutes each, and then dried with nitrogen to ensure that the sample surface is free of particulate contamination. Then, the sample is coated to form the surface electromagnetic shielding layer 312.

[0063] In one embodiment, the coating process can employ electron beam thermal evaporation. Before coating, the evaporation chamber of the coating equipment can be evacuated to reduce gas molecule interference during the preparation of the surface electromagnetic shielding layer 312, ensuring high coating purity. Then, a high-purity metal target (≥99.99%) such as aluminum is placed in a water-cooled copper crucible to avoid contamination. The electron gun voltage is set to 10-15kV, the current to 150-300A, and the focused spot diameter is controlled at 5-10mm on the target surface to achieve localized high-temperature evaporation. The sample is then fixed on a rotatable and / or tiltable tray, and the angle is continuously adjusted at a frequency of 0.1-1Hz using a servo motor. For example, the rotation of the superconducting quantum chip 100 along a plane perpendicular to its location can be controlled. The superconducting quantum chip 100 can be controlled to rotate along an axis perpendicular to its plane (the rotation can be a periodic oscillation from -45° to 45°); or, the superconducting quantum chip 100 can be controlled to rotate along a rotation axis perpendicular to its plane while simultaneously controlling the superconducting quantum chip 100 to oscillate along a direction perpendicular to its plane, thereby compensating for the "shadowing effect" that occurs during coating, ensuring the uniformity of the coating, and improving the thickness uniformity of each region of the surface electromagnetic shielding layer 312; finally, the evaporation rate is adjusted by the electron beam power (e.g., it can be 0.3-0.5 nm / s), and the thickness of the surface electromagnetic shielding layer 312 is monitored in real time by a quartz crystal oscillator, and the electron gun is automatically shut off after the target thickness is reached.

[0064] Alternatively, in another embodiment, the coating process can employ magnetron sputtering evaporation. Before coating, the coating equipment can be evacuated to below 5 × 10⁻³ Pa, and argon gas (99.999% purity) can be introduced as the working gas, maintaining a pressure of 0.5-1.0 Pa. Then, the target material is installed; specifically, niobium, tantalum, titanium nitride, or other targets (purity ≥ 99.99%) can be fixed on the magnetron sputtering cathode, with a target-to-substrate distance set to 50-80 mm. Next, plasma excitation and control of the superconducting quantum chip 100 are performed, i.e., a DC power supply (voltage 300-500V, current 1-3A) is applied to generate high-density plasma, and argon ions bombard the target material. Metal atoms are sputtered; simultaneously, the superconducting quantum chip 100 is controlled to rotate along a spin axis perpendicular to its plane (rotation can be 5-10 rpm); alternatively, the superconducting quantum chip 100 can be controlled to oscillate along a direction perpendicular to its plane (oscillation can be a periodic oscillation from -45° to 45°); alternatively, the superconducting quantum chip 100 can be controlled to rotate along a spin axis perpendicular to its plane while simultaneously oscillating along a direction perpendicular to its plane; finally, the sputtering rate is controlled at 0.2-0.4 nm / s, and monitored online using an optical interferometer or ellipsometer until the thickness of the surface electromagnetic shielding layer 312 reaches the target thickness. Optionally, the thickness of the surface electromagnetic shielding layer 312 provided in this embodiment can be 150-500 nm.

[0065] Step S33: Remove the surface mask layer. Optionally, the surface mask layer can be removed using a lift-off process, wherein the superconducting quantum chip 100 after the surface electromagnetic shielding layer has been deposited is placed in an NMP solution, heated in a water bath to a set temperature (e.g., 80°C) and immersed for 1-2 hours to perform a lift-off operation, then the superconducting quantum chip 100 is immersed in an isopropanol solution for 5-10 minutes, then immersed in ultrapure water for 5-10 minutes, and finally the surface of the superconducting quantum chip 100 is dried with nitrogen gas.

[0066] like Figure 7 As shown, corresponding to step S03, an electromagnetic shielding connection portion 320 penetrating the superconducting quantum chip 100 is formed at the edge sealing region A2. Optionally, the formation of the electromagnetic shielding connection portion 320 penetrating the superconducting quantum chip 100 at the edge sealing region A2 provided in this application embodiment specifically includes:

[0067] Step S031: A protective film layer is formed on the side of the superconducting quantum chip 100 where the electromagnetic shielding sealing ring 310 is formed, and a connection mask layer is formed on the side of the superconducting quantum chip 100 away from the electromagnetic shielding sealing ring 310. In some embodiments, both the protective film layer and the connection mask layer can be formed using photolithography, that is, a third photoresist layer is formed on the side of the superconducting quantum chip 100 where the electromagnetic shielding sealing ring 310 is formed, and the third photoresist layer is a protective film layer covering the electromagnetic shielding sealing ring 310. Furthermore, a fourth photoresist layer is spin-coated on the side of the superconducting quantum chip 100 opposite to the electromagnetic shielding sealing ring 310, and then soft-baked. The fourth photoresist layer can be made of SU-8 series negative photoresist or PMMA positive photoresist. The spin-coating equipment is used at 500-3000 rpm for 30-60 seconds to achieve a thickness of 10-50 micrometers. After resting for 5-10 minutes to eliminate air bubbles, it is then baked on a hot plate at 90-120℃ for 180-300 seconds. The fourth photoresist layer is then exposed using a stepped temperature increase (e.g., at a heating rate of 1℃ / min) to 95℃ for baking. Electron beam or DUV (deep ultraviolet) lithography can be used for exposure, with an electron beam exposure dose of 300-500 μC / cm². 2 The accelerating voltage is 50-100kV; and the DUV lithography exposure wavelength can be 248nm, with an exposure metering of 100-200mJ / cm2. Finally, the fourth photoresist layer is developed using a developer to form a connecting mask layer, and then baked at 150℃ for 30 minutes. When using SU-8 series photoresist, the developer can be PGMEA (propylene glycol methyl ether acetate), and the development time can be 3-5 minutes; when using positive photoresist, the developer can be TMAH (which can be a 2.38% concentration developer), and the development time can be 60-90 seconds.

[0068] Step S032: Based on the connection mask layer, the superconducting quantum chip 100 is etched to form connection holes, which expose the connection portion of the electromagnetic shielding sealing ring 310. The etching of the connection holes can be carried out using different processes depending on the thickness of the superconducting quantum chip 100. For example, when etching shallow holes (depth-to-width ratio can be less than 5:1), reactive ion etching can be used, where the gas can be selected as SF6 (flow rate of 20-50 sccm) and O2 (flow rate of 5-10 sccm), the power is 100-200W, the gas pressure is 5-10 mTorr, and the etching rate is 200-500 nm / min. For deep vias (with an aspect ratio greater than 10:1), deep reactive ion etching (DRIE) can be used, such as the Bosch process. This involves using an etching gas to etch the superconducting quantum chip 100, and a passivating gas to form a polymeric passivation compound on the sidewalls of the etched via. This process is repeated cyclically. The etching gas can be SF6 (flow rate 50 sccm, power 150 W, cycle time 5 s), and the passivating gas can be C4F8 (flow rate 80 sccm, power 200 W, cycle time 3 s). During the via etching process, a laser interferometer or OES (Optical Emission Spectroscopy) can be used to monitor the etching depth in real time.

[0069] Step S033: Deposit the electromagnetic shielding connection portion 320 within the connection hole. The electromagnetic shielding connection portion 320 provided in this embodiment may be a connection portion formed from a single layer of conductive material such as metal or alloy. Alternatively, the electromagnetic shielding connection portion 320 provided in this embodiment may also be composed of at least two stacked layers, such as... Figure 10The illustrated electromagnetic shielding connection 320 may include a seed layer 321 covering the inner wall of the connection hole, and a connection layer 322 filled within the seed layer 321. That is, the deposition of the electromagnetic shielding connection 320 within the connection hole, as provided in this embodiment, includes: forming a seed layer 321 on the inner wall of the connection hole; and filling the connection hole (which is the hole formed by the seed layer 321) with the connection layer 322. The seed layer 321 and the connection layer 322 constitute the electromagnetic shielding connection 320. The seed layer 321 improves the adhesion of the electromagnetic shielding connection 320 within the connection hole. The thickness of the seed layer 321 provided in this embodiment can be 5-100 nm. The seed layer 321 can be formed by magnetron sputtering of Ta or TaN, wherein the magnetron sputtering process parameters include a base vacuum of less than 1e-6 Torr, a sputtering power of 200-400 W, an Ar flow rate of 20-40 sccm, and a sputtering thickness of 5-10 nm; or the seed layer 321 can be formed by DC sputtering of niobium, wherein the sputtering process parameters include a substrate temperature of 400-500 °C and a sputtering thickness of 50-100 nm. The connecting layer 322 provided in this embodiment can be made of niobium or tantalum, etc. The connecting layer 322 can be prepared by niobium or tantalum electroplating, wherein the electrolyte can be an ionic liquid containing NbCl5 or TaCl5, and the current density is 5-20 mA / cm². 2 The temperature is 80-100℃, and the deposition rate is 50-100nm / min; or the connecting layer 322 can be prepared by PVD (Physical Vapor Deposition, magnetron sputtering is physical vapor deposition) deposition process (such as deposition of high-purity niobium), in which the background vacuum is less than 5e-8 Torr, the sputtering power is 300-500W, the substrate temperature is room temperature-200℃, and the deposition film thickness is 1-5μm.

[0070] In some embodiments, the electromagnetic shielding connection portion 320 provided in this application may be composed of a columnar structure, or it may be an annular structure corresponding to the electromagnetic shielding sealing ring; this application does not impose specific limitations on this. When the electromagnetic shielding sealing ring 310 includes a sealing ring 311 and a surface electromagnetic shielding layer 312, the connection portion of the electromagnetic shielding sealing ring 310 is the surface electromagnetic shielding layer 312, more specifically, the surface electromagnetic shielding layer 312 may face the bottom surface of the superconducting quantum chip 100. The electromagnetic shielding sealing ring 310 is connected to the electromagnetic shielding connection portion 320, that is, the electromagnetic shielding sealing ring 310 is connected to the surface electromagnetic shielding layer 312. Figure 11The schematic diagram illustrates the connection structure of the surface electromagnetic shielding layer 312 and the electromagnetic shielding connection portion 320. The surface electromagnetic shielding layer 312 includes an inner connection portion 3121 near the functional circuit area A1 and an outer connection portion 3122 away from the functional circuit area A1. The electromagnetic shielding connection portion 320 includes a plurality of first electromagnetic shielding connection posts 3201 and a plurality of second electromagnetic shielding connection posts 3202. The first electromagnetic shielding connection posts 3201 are in contact with the inner connection portion 3121, and the second electromagnetic shielding connection posts 3202 are in contact with the outer connection portion 3122. At least a portion of the first electromagnetic shielding connection posts 3201 and the second electromagnetic shielding connection posts 3202 are arranged opposite each other on both sides of the sealing ring 311. Alternatively, as shown... Figure 12 The schematic diagram illustrates the connection structure of the surface electromagnetic shielding layer 312 and the electromagnetic shielding connection portion 320. The electromagnetic shielding connection portion 320 includes a plurality of first electromagnetic shielding connection posts 3201 and a plurality of second electromagnetic shielding connection posts 3202. The first electromagnetic shielding connection posts 3201 are in contact with the inner connection portion 3121, and the second electromagnetic shielding connection posts 3202 are in contact with the outer connection portion 3122. At least some of the first electromagnetic shielding connection posts 3201 and the second electromagnetic shielding connection posts 3202 are staggered on both sides of the sealing ring 311. Or as... Figure 13 The schematic diagram shows the connection structure of the surface electromagnetic shielding layer 312 and the electromagnetic shielding connection portion 320. The electromagnetic shielding connection portion 320 includes at least one of a first electromagnetic shielding connection ring 3203 and a second electromagnetic shielding connection ring 3204. Both the first electromagnetic shielding connection ring 3203 and the second electromagnetic shielding connection ring 3204 surround the functional circuit area A1. The first electromagnetic shielding connection ring 3203 is in contact with the inner connection portion 3121, and the second electromagnetic shielding ring 3204 is in contact with the outer connection portion 3122.

[0071] It should be noted that the above Figures 11 to 13The connection methods shown for the surface electromagnetic shielding layer 312 and the electromagnetic shielding connection portion 320 are only a few of the connection methods applicable to this application. This application does not impose specific limitations on these methods, as long as the electromagnetic shielding connection portion 320 connects the electromagnetic shielding sealing ring 310 and the back electromagnetic shielding layer 330 to achieve the shielding effect. Furthermore, the first electromagnetic shielding connection post 3201 and the second electromagnetic shielding connection post 3202 provided in this embodiment can be independent columnar structures formed of electromagnetic shielding material, or they can be columnar structures of the type of seed layer 321 and connecting layer 322. Similarly, the first electromagnetic shielding connection ring 3203 and the second electromagnetic shielding connection ring 3204 can be independent ring structures formed of electromagnetic shielding material, or they can be ring structures of the type of seed layer 321 and connecting layer 322. The specific selection needs to be made according to the actual application.

[0072] Furthermore, before forming the seed layer 321 on the inner wall of the connection hole as provided in the embodiments of this application, the method further includes: forming an insulating layer on the inner wall of the connection hole, wherein the seed layer 321 is formed on the inner wall of the insulating layer, and the insulating layer achieves electrical isolation between the electromagnetic shielding connection 320 and the superconducting quantum chip 100, thereby improving the reliability of the packaging structure.

[0073] Step S034: Remove the connection mask layer, wherein the protective film layer is removed after the back electromagnetic shielding layer 330 is formed.

[0074] like Figure 8 As shown, corresponding to step S04, a back electromagnetic shielding layer 330 is formed on the surface of the superconducting quantum chip 100 facing away from the electromagnetic shielding sealing ring 310. The electromagnetic shielding sealing ring 310 and the back electromagnetic shielding layer 330 are connected through the electromagnetic shielding connection part 320. The back electromagnetic shielding layer 330 can be formed by niobium / tantalum sputtering, and its thickness can be 5-10 micrometers. After sputtering, it can be annealed. The annealing process parameters include a temperature of 400-500℃ and an annealing time of 1-2 hours, thereby improving the superconducting critical temperature. Finally, the protective film can be removed by plasma ashing, with process parameters including a power of 200-300W, an O2 flow rate of 50-100 sccm, and a time of 5-10 minutes; or the protective film can be removed by chemical stripping, i.e., immersion in NMP (N-methylpyrrolidone) solution followed by ultrasonic cleaning (power of 100W, frequency of 40kHz).

[0075] In some embodiments, the surface electromagnetic shielding layer 312, the electromagnetic shielding connection portion 320, and the back electromagnetic shielding layer 330 provided in this application can be made of superconducting material, metal material, or alloy material. The material type needs to be selected specifically according to the actual application, and this application does not impose specific restrictions.

[0076] like Figure 9 As shown, corresponding to step S4, the superconducting quantum chip 100 and the control chip 200 are welded and fixed together, forming a sealed cavity 400 between the superconducting quantum chip 100, the electromagnetic shielding sealing ring 310, and the control chip 200. The welding of the superconducting quantum chip 100 and the control chip 200 can be performed using a flip-chip bonding machine, such as an FC150 flip-chip bonding machine. After placing the superconducting quantum chip 100 and the control chip 200 into the flip-chip bonding machine, a spectroscopic prism microscope can first be inserted between the chips. Then, relevant parameters are adjusted to align the solder joints at the functional circuit area A1 of the superconducting quantum chip 100 and the solder joints of the control chip 200. Then, pressure is applied at room temperature (e.g., 20-50 N / mm²). 2 The solder joints at functional circuit area A1 and control chip 200 are welded together, forming a sealed cavity 400 between the superconducting quantum chip 100, electromagnetic shielding sealing ring 310, and control chip 200. Optionally, the welding of the superconducting quantum chip 100 and control chip 200 can be performed under vacuum conditions. The welding of the superconducting quantum chip 100 and control chip 200 can be performed in an inert gas atmosphere, wherein the sealed cavity 400 is filled with an inert gas, which can suppress oxidation of the functional circuit during the preservation of the packaged structure. The inert gas may include at least one of nitrogen, helium, and argon, and may be a single-element gas or a mixture of multiple elements; this application does not impose specific limitations on this.

[0077] Based on the same inventive concept, this application also provides a packaging structure for a superconducting quantum chip 100, which can be fabricated using the packaging method provided in any of the above embodiments. Figure 2As shown, the packaging structure of the superconducting quantum chip 100 includes: a superconducting quantum chip 100, one side surface of which includes a functional circuit region A1 and an edge sealing region A2 surrounding the functional circuit region A1; a control chip 200, which is welded and fixed to the superconducting quantum chip 100; and an electromagnetic shielding sealing ring 310, which is located between the superconducting quantum chip 100 and the control chip 200, and is correspondingly disposed on the edge sealing region A2 and surrounds the functional circuit region A1. A sealed cavity 400 is formed between the superconducting quantum chip 100, the electromagnetic shielding sealing ring 310, and the control chip 200. The electromagnetic shielding sealing ring 310 includes a sealing ring 311 located on the edge sealing region A2 and surrounding the functional circuit region A1, and a surface electromagnetic shielding layer 312 deposited on the exposed surface of the sealing ring 311. The welding of the superconducting quantum chip 100 and the control chip 200 involves welding and fixing the solder joints at the functional circuit region A1 of the superconducting quantum chip 100 to the corresponding solder joints of the control chip 200, placing them within the sealed cavity 400. It also involves welding and fixing the electromagnetic shielding sealing ring 310 of the superconducting quantum chip 100 to the shielding portion 210 of the control chip 200. The solder joints at the functional circuit region A1 are welded to the corresponding solder joints of the control chip 200 and placed within the sealed cavity 400. Figure 2 The welding post 500 illustrates the welding relationship between the solder joint at functional circuit area A1 and the solder joint of the control chip 200. The welding post 500 is located within the sealed cavity 400. The shielding portion 210 of the control chip 200 includes at least a portion of the ground electrode on the side of the control chip 200 facing the superconducting quantum chip 100, which is welded and fixed to the electromagnetic shielding sealing ring 310.

[0078] In some embodiments, the sealing ring 311 provided in this application can be a sealing photoresist ring. That is, the sealing ring 311 is made of photoresist material, which improves the performance of the electromagnetic shielding sealing ring 310 and further improves the reliability of the packaging structure of the superconducting quantum chip 100.

[0079] like Figure 4As shown in the embodiment of this application, the packaging structure further includes: an electromagnetic shielding connection portion 320 located in the edge sealing region A2 and penetrating the superconducting quantum chip 100, and a back electromagnetic shielding layer 330 located on the surface of the superconducting quantum chip 100 facing away from the electromagnetic shielding sealing ring 310, wherein the electromagnetic shielding sealing ring 310 and the back electromagnetic shielding layer 330 are connected through the electromagnetic shielding connection portion 320. A back electromagnetic shielding layer 330 and an electromagnetic shielding sealing ring 310 are formed around the superconducting quantum chip 100, and the back electromagnetic shielding layer 330 and the electromagnetic shielding sealing ring 310 are connected through the electromagnetic shielding connection portion 320 penetrating the superconducting quantum chip 100, thereby forming an electromagnetic shielding structure around the functional circuitry of the superconducting quantum chip 100, further improving the electromagnetic shielding function of the packaging structure of the superconducting quantum chip 100.

[0080] In some embodiments, the electromagnetic shielding connection portion 320 provided in this application may be composed of a columnar structure, or it may be an annular structure corresponding to the electromagnetic shielding sealing ring; this application does not impose specific limitations on this. When the electromagnetic shielding sealing ring 310 includes a sealing ring 311 and a surface electromagnetic shielding layer 312, the connection portion of the electromagnetic shielding sealing ring 310 is the surface electromagnetic shielding layer 312, more specifically, the surface electromagnetic shielding layer 312 may face the bottom surface of the superconducting quantum chip 100. The electromagnetic shielding sealing ring 310 is connected to the electromagnetic shielding connection portion 320, that is, the electromagnetic shielding sealing ring 310 is connected to the surface electromagnetic shielding layer 312. Figure 14 As shown, the surface electromagnetic shielding layer 312 provided in this embodiment includes an inner connecting portion 3121 near the functional circuit region A1 and an outer connecting portion 3122 away from the functional circuit region A1. Combined with... Figure 11 and Figure 14 As shown, the surface electromagnetic shielding layer 312 provided in this embodiment includes an inner connecting portion 3121 near the functional circuit area A1 and an outer connecting portion 3122 away from the functional circuit area A1; wherein, the electromagnetic shielding connecting portion 320 includes a plurality of first electromagnetic shielding connecting posts 3201 and a plurality of second electromagnetic shielding connecting posts 3202, the first electromagnetic shielding connecting posts 3201 are in contact with the inner connecting portion 3121, and the second electromagnetic shielding connecting posts 3202 are in contact with the outer connecting portion 3122, and at least a portion of the first electromagnetic shielding connecting posts 3201 and the second electromagnetic shielding connecting posts 3202 are disposed opposite to each other on both sides of the sealing ring 311. Or combined with Figure 12 and Figure 14As shown, the electromagnetic shielding connection portion 320 provided in this embodiment includes a plurality of first electromagnetic shielding connection posts 3201 and a plurality of second electromagnetic shielding connection posts 3202. The first electromagnetic shielding connection posts 3201 are in contact with the inner connection portion 3121, and the second electromagnetic shielding connection posts 3202 are in contact with the outer connection portion 3122. At least some of the first electromagnetic shielding connection posts 3201 and the second electromagnetic shielding connection posts 3202 are staggered on both sides of the sealing ring 311. Or combined with Figure 13 and Figure 14 As shown, the electromagnetic shielding connection portion 320 provided in this application embodiment includes at least one of a first electromagnetic shielding connection ring 3203 and a second electromagnetic shielding connection ring 3204. Both the first electromagnetic shielding connection ring 3203 and the second electromagnetic shielding connection ring 3204 surround the functional circuit area A1. The first electromagnetic shielding connection ring 3203 is in contact with the inner connection portion 3121, and the second electromagnetic shielding connection ring 3204 is in contact with the outer connection portion 3122.

[0081] Combination Figure 10 As shown, the electromagnetic shielding connection portion 320 provided in this embodiment includes a connection layer 322 and a seed layer 321 surrounding the connection layer 322 in a direction parallel to the plane of the superconducting quantum chip 100. The seed layer 321 can improve the adhesion of the electromagnetic shielding connection portion 320 in the connection hole. Optionally, the packaging structure provided in this embodiment further includes an insulating layer located between the sidewall of the electromagnetic shielding connection portion 320 and the superconducting quantum chip 100. The insulating layer achieves electrical isolation between the electromagnetic shielding connection portion 320 and the superconducting quantum chip 100, improving the reliability of the packaging structure.

[0082] In some embodiments, the sealing cavity 400 provided in this application is used to fill an inert gas, or the sealing cavity 400 is a vacuum sealing cavity, wherein the sealing cavity 400 is filled with an inert gas, which can suppress oxidation of functional circuits during the preservation of the packaged structure and improve the reliability of the packaged structure. Optionally, the inert gas provided in this application may include at least one of nitrogen, helium and argon, which may be a single-element gas or a mixture of multiple elements, and this application does not impose specific limitations on this.

[0083] Based on the same inventive concept, this application also provides an electronic device, which includes the packaging structure of the superconducting quantum chip of any of the above embodiments. Optionally, the electronic device can be a quantum computer, etc., and this application does not impose specific limitations on it.

[0084] In summary, this application provides a packaging method, packaging structure, and electronic device for a superconducting quantum chip. The packaging structure includes: a superconducting quantum chip, one side surface of which includes a functional circuit region and an edge sealing region surrounding the functional circuit region; a control chip, which is welded and fixed to the superconducting quantum chip; and an electromagnetic shielding sealing ring, which is located between the superconducting quantum chip and the control chip. The electromagnetic shielding sealing ring includes a sealing ring located on the edge sealing region and surrounding the functional circuit region, and a surface electromagnetic shielding layer deposited on the exposed surface of the sealing ring. A sealed cavity is formed between the superconducting quantum chip, the electromagnetic shielding sealing ring, and the control chip.

[0085] As described above, the technical solution provided in this application forms an electromagnetic shielding sealing ring around the functional circuit area on the superconducting quantum chip, thereby creating an electromagnetic shielding structure around the functional circuit of the superconducting quantum chip and realizing its electromagnetic shielding function. Furthermore, by fabricating a surface electromagnetic shielding layer on both sides of the sealing ring and on the surface facing away from the superconducting quantum chip, the bonding strength between the electromagnetic shielding sealing ring and the superconducting quantum chip is further improved, based on the electromagnetic shielding achieved by the sealing ring, thus enhancing the reliability of the packaging structure. In addition, a sealed cavity encapsulating the functional circuit area is formed between the superconducting quantum chip, the electromagnetic shielding sealing ring, and the control chip. This not only controls the welding spacing between the superconducting quantum chip and the control chip through the electromagnetic shielding sealing ring but also achieves hermetically sealed packaging of the superconducting quantum chip. This prevents oxidation and chemical corrosion of the superconducting material in the superconducting quantum chip at low temperatures, improves the long-term stability of the superconducting quantum chip in the dilution refrigerator, enhances the low-temperature performance of the superconducting quantum chip, and improves its overall performance and reliability.

[0086] In the description of the embodiments of this application, it should be understood that the terms "center", "longitudinal", "lateral", "length", "width", "thickness", "upper", "lower", "front", "rear", "left", "right", "vertical", "horizontal", "top", "bottom", "inner", "outer", "clockwise", "counterclockwise", "axial", "radial", "circumferential" and other terms indicating the orientation or positional relationship are based on the orientation or positional relationship shown in the drawings, and are only for the convenience of describing the embodiments of this application and simplifying the description, and are not intended to indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation, and therefore should not be construed as a limitation of this application.

[0087] Furthermore, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of technical features indicated. Therefore, a feature defined as "first" or "second" may explicitly or implicitly include at least one of that feature. In the description of embodiments of this application, "multiple" means at least two, such as two, three, etc., unless otherwise explicitly specified.

[0088] In the embodiments of this application, unless otherwise explicitly specified and limited, terms such as "installation," "connection," "linking," and "fixing" should be interpreted broadly. For example, they can refer to a fixed connection, a detachable connection, or an integral part; they can refer to a mechanical connection, an electrical connection, or a connection that allows communication between them; they can refer to a direct connection or an indirect connection through an intermediate medium; they can refer to the internal communication of two components or the interaction between two components, unless otherwise explicitly limited. Those skilled in the art can understand the specific meaning of the above terms in this application according to the specific circumstances.

[0089] In the embodiments of this application, unless otherwise expressly specified and limited, "above" or "below" the second feature can mean that the first feature is in direct contact with the second feature, or that the first feature is in indirect contact with the second feature through an intermediate medium. Furthermore, "above," "on top of," and "over" the second feature can mean that the first feature is directly above or diagonally above the second feature, or simply that the first feature is at a higher horizontal level than the second feature. "Below," "below," and "under" the second feature can mean that the first feature is directly below or diagonally below the second feature, or simply that the first feature is at a lower horizontal level than the second feature.

[0090] In the embodiments of this application, the terms "one embodiment," "some embodiments," "example," "specific example," or "some examples," etc., refer to specific features, structures, materials, or characteristics described in connection with that embodiment or example, which are included in at least one embodiment or example of this application. In this specification, the illustrative expressions of the above terms do not necessarily refer to the same embodiment or example. Moreover, the specific features, structures, materials, or characteristics described may be combined in any suitable manner in one or more embodiments or examples. Furthermore, without contradiction, those skilled in the art can combine and integrate the different embodiments or examples described in this specification, as well as the features of different embodiments or examples.

[0091] Although embodiments of this application have been shown and described above, it is understood that the above embodiments are exemplary and should not be construed as limiting this application. Those skilled in the art can make changes, modifications, substitutions and variations to the above embodiments within the scope of this application.

Claims

1. A packaging structure of a superconducting quantum chip, characterized by, include: A superconducting quantum chip, wherein one side surface of the superconducting quantum chip includes a functional circuit region and an edge sealing region surrounding the functional circuit region; A control chip is welded and fixed to the superconducting quantum chip. An electromagnetic shielding sealing ring is located between the superconducting quantum chip and the control chip. The electromagnetic shielding sealing ring includes a sealing ring located on the edge sealing area and surrounding the functional circuit area, and a surface electromagnetic shielding layer deposited on the exposed surface of the sealing ring. A sealed cavity is formed between the superconducting quantum chip, the electromagnetic shielding sealing ring, and the control chip. The solder joints at the functional circuit area and the corresponding solder joints of the control chip are welded and fixed and located within the sealed cavity.

2. The packaging structure of a superconducting quantum chip according to claim 1, wherein, The sealing ring is a sealing photoresist ring.

3. The packaging structure of a superconducting quantum chip according to claim 1, wherein, The packaging structure further includes: An electromagnetic shielding connection located in the edge sealing area and penetrating the superconducting quantum chip; and a back electromagnetic shielding layer located on the surface of the superconducting quantum chip away from the electromagnetic shielding sealing ring, wherein the electromagnetic shielding sealing ring and the back electromagnetic shielding layer are connected by the electromagnetic shielding connection portion.

4. The packaging structure of a superconducting quantum chip according to claim 3, wherein The surface electromagnetic shielding layer includes an inner connection portion close to the functional circuit area and an outer connection portion away from the functional circuit area; The electromagnetic shielding connection includes a plurality of first electromagnetic shielding connection posts and a plurality of second electromagnetic shielding connection posts. The first electromagnetic shielding connection posts are in contact with the inner connection part, and the second electromagnetic shielding connection posts are in contact with the outer connection part. At least some of the first electromagnetic shielding connection posts and the second electromagnetic shielding connection posts are arranged opposite to each other on both sides of the sealing ring.

5. The packaging structure of a superconducting quantum chip according to claim 3, wherein The surface electromagnetic shielding layer includes an inner connection portion close to the functional circuit area and an outer connection portion away from the functional circuit area; The electromagnetic shielding connection includes a plurality of first electromagnetic shielding connection posts and a plurality of second electromagnetic shielding connection posts. The first electromagnetic shielding connection posts are in contact with the inner connection part, and the second electromagnetic shielding connection posts are in contact with the outer connection part. At least some of the first electromagnetic shielding connection posts and the second electromagnetic shielding connection posts are staggered on both sides of the sealing ring.

6. The packaging structure of a superconducting quantum chip according to claim 3, wherein The surface electromagnetic shielding layer includes an inner connection portion close to the functional circuit area and an outer connection portion away from the functional circuit area; The electromagnetic shielding connection includes at least one of a first electromagnetic shielding connection ring and a second electromagnetic shielding connection ring. Both the first electromagnetic shielding connection ring and the second electromagnetic shielding connection ring surround the functional circuit area. The first electromagnetic shielding connection ring is in contact with the inner connection portion, and the second electromagnetic shielding connection ring is in contact with the outer connection portion.

7. The packaging structure of a superconducting quantum chip according to claim 3, wherein The electromagnetic shielding connection includes a connection layer and a seed layer surrounding the connection layer in a direction parallel to the plane where the superconducting quantum chip is located.

8. The packaging structure of a superconducting quantum chip according to claim 3, wherein, The packaging structure further includes an insulating layer located between the sidewall of the electromagnetic shielding connection and the superconducting quantum chip.

9. The packaging structure of a superconducting quantum chip according to claim 1, wherein, The sealed cavity is used to fill inert gas, or the sealed cavity is a vacuum sealed cavity.

10. An electronic device, comprising: The electronic device includes the packaging structure of the superconducting quantum chip according to any one of claims 1-9.

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