Semiconductor device

Abstract

A semiconductor device is provided, comprising: a first transistor, a second transistor, a first dielectric structure, a second dielectric structure, and source / drain contacts. The first transistor includes a first gate structure and a first source / drain component. The first gate structure is located on a first channel region. The first source / drain component is coupled to the first channel region. The second transistor includes a second gate structure and a second source / drain component. The second gate structure is located on a second channel region. The second source / drain component is coupled to the second channel region. The first dielectric structure extends from a lower portion of the first source / drain component to a lower portion of the second source / drain component. The second dielectric structure is located above the first dielectric structure and has a different composition than the first dielectric structure. The source / drain contacts are electrically coupled to the first source / drain component and the second source / drain component and are located on the second dielectric structure.

Description

Technical Field

[0001] This utility model relates to semiconductor technology, and more particularly to semiconductor devices. Background Technology

[0002] The semiconductor integrated circuit (IC) industry has experienced rapid growth. Technological advancements in IC materials and design have led to generation after generation of ICs, each with smaller and more complex circuits than the previous one. During the evolution of ICs, functional density (i.e., the number of interconnects per unit wafer area) typically increases while geometry (i.e., the smallest element (or line) that can be manufactured using a process) decreases. This miniaturization process usually contributes to increased production efficiency and reduced associated costs.

[0003] As integrated circuit (IC) technology advances towards smaller technology nodes, parasitic capacitances associated with source / drain contacts can significantly impact the overall performance of IC devices. While existing source / drain contacts are generally sufficient for their intended purpose, they are not satisfactory in all aspects. Utility Model Content

[0004] This invention provides a semiconductor device, comprising: a first transistor including: a first gate structure located on a first channel region; and a first source / drain component coupled to the first channel region; a second transistor including: a second gate structure located on a second channel region; and a second source / drain component coupled to the second channel region; a first dielectric structure extending from the lower portion of the first source / drain component to the lower portion of the second source / drain component; a second dielectric structure located above the first dielectric structure and having a composition different from the first dielectric structure; and a source / drain contact electrically coupled to the first source / drain component and the second source / drain component and located on the second dielectric structure.

[0005] In some embodiments, the semiconductor device further includes: a first silicide layer on the first source / drain component; and a second silicide layer on the second source / drain component, wherein the second dielectric structure includes a first dielectric layer and a second dielectric layer located above the first dielectric layer, and the first dielectric layer extends from the first silicide layer to the second silicide layer.

[0006] In some embodiments, the source / drain contact has an upper portion and a lower portion, the upper portion being located above the top surface of the first silicide layer and the second silicide layer, and the lower portion being located between the second dielectric structure and the upper portion.

[0007] In some embodiments, in a cross-sectional view, the upper portion of the source / drain contact has a rectangular profile, and the lower portion of the source / drain contact has a trapezoidal profile.

[0008] In some embodiments, the upper portion of the source / drain contact has a first height and the lower portion of the source / drain contact has a second height, the ratio of the second height to the first height being less than 0.6.

[0009] In some embodiments, the ratio of the second height to the first height is between 0.1 and 0.6.

[0010] In some embodiments, the bottom surface of the source / drain contact is lower than the top surface of the first source / drain component.

[0011] In some embodiments, the first channel region includes multiple nanostructures.

[0012] In some embodiments, the first gate structure fits the first channel region.

[0013] In some embodiments, a top surface of the first dielectric structure is lower than a top surface of the first source / drain component. Attached Figure Description

[0014] The various embodiments of this utility model can be best understood from the following detailed description in conjunction with the accompanying drawings. It should be noted that, in accordance with industry standard practice, the various components are not drawn to scale. In fact, for clarity of discussion, the dimensions of various components may be arbitrarily enlarged or reduced.

[0015] Figure 1 A flowchart illustrating a method for forming a semiconductor structure according to one or more aspects of the present invention is shown.

[0016] Figure 2 Examples of various embodiments according to the present invention are shown. Figure 1 A partial top view of an exemplary structure that undergoes various operational stages in the method.

[0017] Figure 3A , Figure 4A , Figure 5A , Figure 6A , Figure 7A , Figure 8A , Figure 9A , Figure 10A , Figure 11A , Figure 12A , Figure 13A , Figure 14A , Figure 15A , Figure 16A as well as Figure 17A ( Figures 3A-17A)Example in Figure 1 During each manufacturing stage of the method Figure 2 The diagram shows a partial cross-sectional view of the structure cut by section line A-A'.

[0018] Figure 3B , Figure 4B , Figure 5B , Figure 6B , Figure 7B , Figure 8B , Figure 9B , Figure 10B , Figure 11B , Figure 12B , Figure 13B , Figure 14B , Figure 15B , Figure 16B and Figure 17B ( Figures 3B-17B )Example in Figure 1 During each manufacturing stage of the method Figure 2 The diagram shows a partial cross-sectional view of the structure cut by section line B-B'.

[0019] The reference numerals in the attached figures are explained as follows:

[0020] 10: First Zone

[0021] 20: Second Zone

[0022] 100: Method

[0023] 102: Block

[0024] 104: Block

[0025] 106: Block

[0026] 108: Block

[0027] 110: Block

[0028] 112: Block

[0029] 114: Block

[0030] 116: Block

[0031] 118: Block

[0032] 120: Block

[0033] 122: Block

[0034] 124: Block

[0035] 126: Block

[0036] 200: Semiconductor structure / structure

[0037] 202: Substrate

[0038] 202t: Top

[0039] 204A: Fin-shaped active area

[0040] 204B: Fin-shaped active area

[0041] 204C: Fin-shaped active area

[0042] 204D: Fin-shaped active area

[0043] 204SD: Source / Drain Region

[0044] 205: Isolation component

[0045] 205h: Horizontal section

[0046] 205v: Vertical section

[0047] 208: Channel Layer

[0048] 210: Dummy Gate Stack

[0049] 210a: Dummy gate dielectric layer

[0050] 210b: Dummy gate electrode layer

[0051] 210c: Hard masking layer at the top of the gate

[0052] 211: Dummy gate dielectric layer

[0053] 212: Dummy gate electrode

[0054] 212a: Gate spacer

[0055] 212b: Fin sidewall spacers

[0056] 214: Source / Drain Opening

[0057] 222N: Source / Drain Component

[0058] 222P: Source / Drain Component

[0059] 226: Contact etch stop layer (CESL) 228: Interlayer dielectric (ILD) layer

[0060] 230: Metal gate structure

[0061] 236: Etching Stop Layer

[0062] 238: Second ILD layer

[0063] 238s: Top surface

[0064] 240: Patterned Mask

[0065] 242: Etching process

[0066] 244: Opening

[0067] 244L: Lower part

[0068] 244U: Upper part

[0069] 246: Dielectric Liner

[0070] 248: Dielectric material layer

[0071] 248a: First level section

[0072] 248b: Vertical section

[0073] 248c: Second level section

[0074] 248s: Top surface

[0075] 248s': Top surface

[0076] 248s”: Top surface

[0077] 248s1: Section

[0078] 248s2: Section

[0079] 252: First step 254: Second step 256: Dielectric structure

[0080] 258: Dielectric barrier layer

[0081] 260a: Silicide layer

[0082] 260b: Silicate layer

[0083] 262: Source / Drain Contacts

[0084] 262L: Lower part

[0085] 262U: Upper part

[0086] 264: Inner spacer component

[0087] H1: Height

[0088] H2: Height

[0089] X: X direction

[0090] Y: Y direction

[0091] Z: Z direction

[0092] A-A': section line

[0093] B-B': Section line Detailed Implementation

[0094] Numerous embodiments or examples are disclosed below for implementing different elements of the provided subject matter. Specific examples of each element and its configuration are described below to simplify the illustration of embodiments of the present invention. Of course, the above are merely examples and are not intended to limit the embodiments of the present invention. For example, if the description refers to a first element forming above a second element, it may include embodiments where the first and second elements are in direct contact, or embodiments where an additional element is formed between the first and second elements such that they are not in direct contact. Furthermore, the present invention may repeat reference values ​​and / or letters in various examples. Such repetition is for the purpose of brevity and clarity, and is not intended to indicate a relationship between the different embodiments and / or configurations discussed.

[0095] Furthermore, spatially relative terms may be used, such as "below," "below," "lower," "above," "higher," etc., to facilitate the description of the relationship between one or more features or components in the diagram. Spatially relative terms are used to include different orientations of the device in use or operation, as well as the orientations described in the diagram. When the device is turned to different orientations (rotated 90 degrees or other orientations), the spatially relative adjectives used will also be interpreted according to the orientation after the turn.

[0096] Furthermore, when using terms such as "approximately" or "about," to describe a number or range of numbers, this terminology is intended to cover a reasonable range of numbers that takes into account the inherent variations in the manufacturing process as understood by those skilled in the art. For example, based on known manufacturing tolerances for manufacturing components having the number as a related part, the number or range of numbers covers a reasonable range that includes the number, such as within + / - 10% of the number. For example, those skilled in the art know that the manufacturing tolerance associated with a deposited material layer is + / - 15%, and a material layer with a thickness of "approximately 5 nanometers" can cover a size range of 4.25 nanometers to 5.75 nanometers.

[0097] As integrated circuit (IC) technology evolves towards smaller technology nodes, multi-gate devices have been introduced to improve gate control by increasing gate-channel coupling, reducing off-state current, and minimizing short-channel effects (SCEs). Multi-gate devices typically refer to devices with a gate structure or a portion thereof positioned above more than one side of the channel region. FinFETs and gate-all-around (GAA) transistors are examples of multi-gate devices, and they have become popular and promising candidates for high-performance and low-leakage applications. FinFETs have elevated channels that are surrounded by gates on more than one side (e.g., the gate surrounds the top and sidewalls of a semiconductor material "fin" extending from the substrate). GAA transistors have a gate structure that can extend partially or completely around the channel region to provide access to the channel region on two or more sides. The channel region of a GAA transistor can be formed from nanowires, nanosheets, other nanostructures, and / or other suitable structures. The shape of the channel region also gives GAA transistors alternative names, such as nanosheet transistors or nanowire transistors.

[0098] This invention provides a method for reducing parasitic capacitance between a source / drain contact and its adjacent source / drain components. In an exemplary method, after forming a source / drain contact opening, the lower portion of the source / drain opening is refilled with a dielectric structure, and then the source / drain contact opening is formed on the dielectric structure and in the source / drain contact. Forming a dielectric structure in the source / drain contact opening reduces the depth of the source / drain contact and reduces the overlap area between the source / drain contact and its adjacent source / drain components. Therefore, the parasitic capacitance of the semiconductor structure can be reduced, and the performance of the semiconductor structure can be improved.

[0099] The various aspects of this utility model will now be described in more detail with reference to the accompanying drawings. In this regard, Figure 1 This is a flowchart illustrating a method 100 for forming a semiconductor structure according to an embodiment of the present invention. The following is in conjunction with... Figure 2 , Figures 3A-17A and Figures 3B-17B To describe method 100, Figure 2 , Figures 3A-17A and Figures 3B-17BThis is a partial top view / sectional view of structure 200 at different manufacturing stages according to an embodiment of method 100. Method 100 is merely exemplary and is not intended to limit the invention to the content explicitly illustrated herein. Additional steps may be provided before, during, and after method 100, and some described steps may be replaced, deleted, or moved for additional embodiments of the method. For brevity, not all steps are described in detail herein. To avoid ambiguity, Figure 2 and Figures 3A-17B The X, Y, and Z directions are perpendicular to each other and are used consistently throughout this utility model. Throughout this utility model, unless otherwise stated, similar element symbols denote similar parts.

[0100] refer to Figure 1 , Figure 2 and Figures 3A-3B Method 100 includes block 102, wherein a structure 200 including a first region 10 and a second region 20 is received. Figure 2 The various aspects that need to be experienced according to this utility model are described. Figure 1 A partial top view of the structure of each operational stage in the method, 200. Figure 3A Examples are shown along such Figure 2 The diagram shows a partial cross-sectional view of structure 200 taken along section line A-A', and... Figure 3B Examples are shown along such Figure 2 The diagram shows a partial cross-sectional view of structure 200 taken along section line B-B'. (See diagram for reference.) Figures 3A-3BAs shown, structure 200 includes a substrate 202. The substrate 202 can be an elemental (single-element) semiconductor, such as silicon (Si) or germanium (Ge) in a crystal structure; a compound semiconductor, such as silicon carbide (SiC), gallium arsenide (GaAs), gallium phosphide (GaP), indium phosphide (InP), indium arsenide (InAs), and / or indium antimonide (InSb); or an alloy semiconductor, such as silicon germanium (SiGe), gallium arsenide phosphide (GaAsP), aluminum indium arsenide (AlInAs), aluminum gallium arsenide (AlGaAs), gallium indium arsenide (GaInAs), gallium gallium phosphide (AlGaInP), and / or gallium phosphide indium arsenide (GaInAsP). In one embodiment, the substrate 202 is a silicon (Si) substrate. The composition of the substrate 202 can be homogeneous or can include various layers, some of which can be selectively etched to form fin-shaped active regions (e.g., fin-shaped active regions 204A-204D). These layers can have similar or different compositions, and in various embodiments, some substrate layers have non-uniform compositions to induce device strain and thus modulate device performance. Examples of layered substrates include silicon-on-insulator (SOI) substrates 202. In some such examples, the layers of substrate 202 may include insulators, such as semiconductor oxides, semiconductor nitrides, semiconductor oxide nitrides, semiconductor carbides, and / or other suitable insulating materials. Doped regions, such as wells, may be formed in substrate 202. Figure 2 In the illustrated embodiment, a portion of the substrate 202 in the first region 10 is doped with an n-type dopant and may be referred to as an n-type well (not shown), and a portion of the substrate 202 in the second region 20 is doped with a p-type dopant and may be referred to as a p-type well (not shown). The n-type dopant may include phosphorus (P) or arsenic (As). The p-type dopant may include boron (B), boron difluoride (BF2), or indium (In). The n-type well and p-type well can be formed using ion implantation or thermal diffusion and may be considered as part of the substrate 202. As will be further described below, the first region 10 is a p-type field-effect transistor (PFET) region for forming a PFET, and the second region 20 is an n-type field-effect transistor (NFET) region for forming an NFET.

[0101] Still refer to Figure 2 and Figures 3A-3BStructure 200 includes a plurality of fin-shaped active regions (e.g., fin-shaped active regions 204A, 204B, 204C, 204D) protruding from substrate 202. In the illustrated embodiment, first region 10 includes fin-shaped active regions 204A and 204B extending vertically from substrate 202, and second region 20 includes fin-shaped active regions 204C and 204D extending vertically from substrate 202. Figure 2 and Figures 3A-3B The number of finned active regions depicted is merely an example; structure 200 may include any suitable number of finned active regions. Each finned active region 204A-204D extends longitudinally along the X direction and is divided into a channel region 204C that overlaps with the dummy gate stack 210 (described below) and a source / drain region 204SD that does not overlap with the dummy gate stack 210. Depending on the context, the source / drain region 204SD may refer individually or collectively to either the source region or the drain region. Each channel region 204C is disposed along the X direction between the two source / drain regions 204SD.

[0102] For an embodiment where structure 200 is to be fabricated to include a FinFET, each fin active region 204A-204D can be formed by the top 202t of substrate 202. Figure 3B As shown. For an embodiment where structure 200 will be fabricated to include a GAA transistor, each finned active region 204A-204D may comprise a vertically stacked (not shown) alternating semiconductor layers and a portion of substrate 202. The vertical stack includes a plurality of channel layers 208 interleaved with a plurality of sacrificial layers (not shown). Figure 17A (as shown in the figure). Each channel layer 208 may include a semiconductor material such as silicon, germanium, silicon carbide, silicon germanium, GeSn, SiGeSn, SiGeCSn, other suitable semiconductor materials, or combinations thereof, while each sacrificial layer has a different composition than the channel layer 208. In one embodiment, each channel layer 208 includes silicon (Si), and each sacrificial layer includes silicon germanium (SiGe).

[0103] Structure 200 also includes an isolation component 205 formed around the finned active regions to isolate two adjacent finned active regions. The isolation component 205 may include a shallow trench isolation (STI) component 205. In an exemplary process, a dielectric material for the isolation component 205 is first deposited over structure 200 to fill the trenches between the finned active regions 204A-204D. In some embodiments, the dielectric material may include silicon oxide, silicon oxynitride, fluorine-doped silicate glass (FSG), a low-k dielectric, combinations thereof, and / or other suitable materials. In various examples, the dielectric material may be deposited using chemical vapor deposition (CVD), flowable chemical vapor deposition (FCVD), spin coating, and / or other suitable processes. The deposited dielectric material is then thinned and planarized using a process such as chemical mechanical polishing (CMP) until the top surfaces of the finned active regions 204A-204D are exposed. The planarized dielectric material is further etched or etched back using dry etching, wet etching, and / or combinations thereof to form the STI component 205. The upper portions of the finned active regions 204A-204D rise above the STI component 205, while the lower portions of the finned active regions 204A-204D remain covered or buried within the STI component 205. The deposited dielectric material can be a single-layer or multi-layer structure. In this embodiment, at least one STI component 205 includes a horizontal portion 205h extending between two adjacent finned active regions (e.g., finned active regions 204B and 204C) and two vertical portions 205v extending along the bottom sidewall surfaces of the two adjacent finned active regions.

[0104] Structure 200 also includes dummy gate stacks 210. Each dummy gate stack 210 includes a dummy gate dielectric layer 210a, a dummy gate electrode layer 210b above the dummy gate dielectric layer 210a, and a gate top hard mask layer 210c above the dummy gate electrode layer 210b. The dummy gate dielectric layer 210a may include silicon oxide. The dummy gate electrode layer 210b may include polysilicon. The gate top hard mask layer 210c may include silicon oxide, silicon nitride, and / or other suitable materials. The dummy gate stacks 210 can be formed using appropriate deposition processes, photolithography, and etching processes. In this embodiment, a gate replacement process (or gate-last process) is used, wherein the dummy gate stacks 210 serve as functional gate structures (e.g., Figures 7A-7B The gate structure 230 shown has placeholders. Other processes and configurations are also possible. Figure 2 Three dummy gate stacks 210 are illustrated, but structure 200 may include any appropriate number of dummy gate stacks 210.

[0105] Structure 200 also includes gate spacers 212a extending along the sidewall surfaces of the dummy gate stack 210. Each gate spacer 212a may be a single-layer or multi-layer structure. In exemplary fabrication processes, the spacer layer is conformally deposited over structure 200 by atomic layer deposition (ALD), chemical vapor deposition (CVD), or any other suitable deposition process. The term “conformal” may be used herein to describe layers having a substantially uniform thickness over various regions of structure 200. The spacer layer may include silicon oxide, silicon nitride, silicon oxycarbide, silicon carbonitride, silicon carbonitride, metal nitride, other suitable dielectric materials, or combinations thereof. An etching process is performed to remove the portion of the spacer layer above the top surface of structure 200 to form the gate spacers 212a extending along the sidewalls of the dummy gate stack 210. The deposition and etching of the spacer layer also form fin sidewall spacers 212b that extend along the lower part of the sidewalls of the fin active regions 204A-204D and are disposed on the vertical portion 205v of the STI component 205.

[0106] refer to Figure 1 and Figures 4A-4BMethod 100 includes a block 104 forming a source / drain opening 214. The source / drain regions 204SD of the finned active regions 204A-204D are etched to form the source / drain opening 214. In some embodiments, the source / drain regions 204SD of the finned active regions 204A-204D are anisotropically etched by plasma etching using a suitable etchant, such as a fluorinated etchant, an oxygen-containing etchant, a hydrogen-containing etchant, a fluorinated etchant (e.g., CF4, SF6, CH2F2, CHF3 and / or C2F6), a chlorinated etchant (e.g., Cl2, CHCl3, CCl4 and / or BCl3), a bromine-containing etchant (e.g., HBr and / or CHBr3), an iodine-containing etchant, other suitable etchants, and / or combinations thereof.

[0107] In an embodiment where structure 200 is to be fabricated as including a GAA transistor, after forming the source / drain opening 214, the vertically stacked sacrificial layers are selectively etched laterally to form inner spacer recesses. Then, inner spacer members 264 (e.g., ...) are formed in the inner spacer recesses. Figure 17A (As shown). The inner spacer may comprise any suitable dielectric material, such as SiN, SiO and / or SiO2, SiCN, SiOC, SiON, SiOCN, low-k dielectric materials, other suitable dielectric materials, or combinations thereof. The inner spacer 264 may each be configured as a single-layer or multi-layer structure comprising combinations of the dielectric materials provided herein. In some embodiments, the inner spacer 264 has a composition different from that of the gate spacer 212a.

[0108] Now for reference Figure 1 and Figures 5A-5BMethod 100 includes block 106, wherein source / drain components (e.g., 222P and 222N) are formed in source / drain openings 214. In the illustrated embodiment, source / drain components 222P and 222N are formed in source / drain openings 214 in a first region 10 and a second region 20, respectively. Depending on the context, the source / drain components may individually or collectively refer to a source or a drain. Source / drain component 222P is coupled to a channel region 204C in the first region 10. Source / drain component 222N is coupled to a channel region 204C in the second region 20. Both source / drain components 222N and 222P can be epitaxially and selectively formed from the exposed sidewalls of channel layer 208 using epitaxial processes such as vapor-phase epitaxy (VPE), ultra-high vacuum chemical vapor deposition (UHV-CVD), molecular beam epitaxy (MBE), and / or other suitable processes.

[0109] Exemplary N-type source / drain component 222N may include silicon, phosphorus-doped silicon, arsenic-doped silicon, antimony-doped silicon, or other suitable materials, and may be in-situ doped during epitaxial processing by introducing an N-type dopant such as phosphorus, arsenic, or antimony, or ex-situ doped using a junction implantation process. Exemplary P-type source / drain component 222P may include germanium, arsenic-doped silicon germanium, boron-doped silicon germanium, or other suitable materials, and may be in-situ doped during epitaxial processing by introducing a P-type dopant such as boron or gallium, or ex-situ doped using a junction implantation process. In some embodiments, each of the N-type source / drain component 222N and the P-type source / drain component 222P may include multiple semiconductor layers with different doping concentrations. The N-type source / drain component 222N and the P-type source / drain component 222P may be formed in any suitable order.

[0110] Now for reference Figure 1 and Figures 6A-6BMethod 100 includes block 108, wherein a first interlayer dielectric (ILD) layer 228 is formed over substrate 202. A contact etch stop layer (CESL) 226 and the first interlayer dielectric (ILD) layer 228 are deposited over structure 200. CESL 226 may include silicon nitride, silicon oxynitride, and / or other suitable materials, and may be formed by ALD, plasma-enhanced chemical vapor deposition (PECVD), and / or other suitable deposition or oxidation processes. After depositing CESL 226, the first ILD layer 228 is deposited on structure 200 by PECVD or other suitable deposition techniques. The first ILD layer 228 may include materials such as tetraethylorthosilicate (TEOS) oxide, undoped silicate glass, or silicon oxide-doped materials such as borophosphosilicate glass (BPSG), fused silica glass (FSG), fused silica glass (PSG), boron-doped silicon glass (BSG), and / or other suitable dielectric materials. A planarization process, such as chemical mechanical polishing (CMP), may be performed on structure 200 to remove excess material and expose the top surface of the dummy gate electrode layer 210b in the dummy gate stack 210.

[0111] Now for reference Figure 1 and Figures 7A-7BMethod 100 includes block 110, wherein a dummy gate stack 210 is replaced by a metal gate structure 230. After exposing the top surface of the dummy gate electrode layer 210b in the dummy gate stack 210, an etching process is performed to selectively remove the dummy gate electrode layer 212 and the dummy gate dielectric layer 211 of the dummy gate stack 210 without substantially removing the gate spacer 212a, to form a gate trench. The metal gate structure 230 is then formed in the gate trenches in the first region 10 and the second region 20. The formation step of the metal gate structure 230 includes forming an interface layer over a substrate 202. The interface layer may include silicon oxide or other suitable materials and may be formed using suitable methods, such as atomic layer deposition (ALD), chemical vapor deposition (CVD), thermal oxidation, or other suitable methods. In one embodiment, the interface layer is formed by thermal oxidation. After forming the interface layer, a dielectric layer is formed over the structure 200 and in the gate trench. In an embodiment, the dielectric layer is conformally deposited over the structure 200. The term "conformally" may be used herein to describe layers having substantially uniform thickness across various regions. In some embodiments, the dielectric layer is a high-k dielectric layer because its dielectric constant is greater than that of silicon dioxide (~3.9). In some embodiments, the dielectric layer may comprise titanium oxide (TiO2), tantalum oxide (Ta2O5), hafnium silicon oxide (HfSiO4), zirconium oxide (ZrO2), zirconium oxide (ZrSiO2), aluminum oxide (Al2O3), zirconium oxide (ZrO), yttrium oxide (Y2O3), SrTiO3 (STO), BaTiO3 (BTO), BaZrO, lanthanum hafnium oxide (HfLaO), aluminum silicon oxide (AlSiO), hafnium tantalum oxide (HfTaO), hafnium titanium oxide (HfTiO), (Ba,Sr)TiO3 (BST), silicon nitride (SiN), silicon oxynitride (SiON), combinations thereof, or other suitable materials. The dielectric layer and the interface layer can be collectively referred to as the gate dielectric layer.

[0112] The formation step of the metal gate structure 230 also includes forming a gate electrode over the gate dielectric layer. The gate electrode may be a multilayer structure including at least one work function layer and a metal filling layer. For example, the at least one work function layer may include titanium nitride (TiN), titanium aluminum (TiAl), titanium aluminum nitride (TiAlN), tantalum nitride (TaN), tantalum aluminum (TaAl), tantalum aluminum nitride (TaAlN), tantalum aluminum carbide (TaAlC), tantalum carbonitride (TaCN), or tantalum carbide (TaC). The metal gate structure 230 formed in the first region 10 may include at least one P-type work function layer. The metal gate structure 230 formed in the second region 20 may include at least one N-type work function layer. The metal filling layer may include aluminum (Al), tungsten (W), nickel (Ni), titanium (Ti), ruthenium (Ru), cobalt (Co), platinum (Pt), silicon tantalum nitride (TaSiN), copper (Cu), other refractory metals, or other suitable metallic materials or combinations thereof. In various embodiments, the gate electrode can be formed by atomic layer deposition (ALD), physical vapor deposition (PVD), chemical vapor deposition (CVD), electron beam evaporation, or other suitable processes. In various embodiments, planarization processes such as chemical mechanical polishing (CMP) can be performed to remove excess material above the first ILD layer 228 to provide a substantially flat top surface and facilitate the execution of subsequent processes.

[0113] For an embodiment where structure 200 is to be fabricated to form a GAA transistor, method 100 further removes a sacrificial layer from the vertical stack during a sheet (or wire) forming process prior to forming the metal gate structure 230, thereby removing the sacrificial layer from the vertical stack in the channel layer 208 (e.g., Figure 17A An opening (not shown) is formed between the channel layer 208 and the wafer fabrication process. In this embodiment, the wafer fabrication process selectively removes the sacrificial layer without removing or substantially not removing the channel layer 208. The metal gate structure 230 is also further configured to surround the channel layer 208.

[0114] Now for reference Figure 1 and Figures 8A-8BMethod 100 includes block 112, wherein a second interlayer dielectric (ILD) layer 238 is formed over substrate 202. After forming the metal gate structure 230, an etch stop layer 236 is formed over the first interlayer dielectric (ILD) layer 228. The etch stop layer 236 may include silicon nitride, silicon oxynitride, and / or other suitable materials, and may be formed by ALD, plasma-enhanced chemical vapor deposition (PECVD) processes, and / or other suitable deposition or oxidation processes. The formation of the etch stop layer 236 may facilitate the formation of gate vias over the metal gate structure 230 during subsequent manufacturing processes. The second ILD layer 238 is deposited over the etch stop layer 236 by a PECVD process or other suitable deposition technique. The second ILD layer 238 may include materials such as tetraethylorthosilicate (TEOS) oxide, undoped silicate glass or silicon oxide such as borophosphosilicate glass (BPSG), fused silica glass (FSG), fused silica glass (PSG), boron doped silicon glass (BSG), and / or other suitable dielectric materials.

[0115] Now for reference Figure 1 and Figures 9A-9BMethod 100 includes block 114, in which openings 244 are formed to expose source / drain components 222P and 222N. In this illustrated embodiment, a patterned mask 240 is formed over structure 200. The patterned mask 240 may include silicon nitride, silicon oxynitride, silicon carbonitride, or other suitable dielectric materials. In an exemplary process for forming the patterned mask 240, a hard mask layer may be deposited using chemical vapor deposition (CVD), atomic layer deposition (ALD), or other suitable deposition techniques. A photoresist layer may then be deposited on the hard mask layer using spin coating, CVD, or other similar processes. The photoresist layer is baked in a pre-exposure baking process, exposed to radiation sources reflected from or transmitted through the patterned mask, baked in a post-exposure baking process, and developed in a developing process. Because the photoresist layer is selected to be sensitive to radiation, the exposed (or unexposed) portion of the photoresist layer undergoes a chemical change during the subsequent development process, becoming soluble in the developer solution. The patterned photoresist layer has a pattern corresponding to the pattern of the photomask. When the patterned photoresist layer is used as an etching mask, the hard mask layer is etched to form the patterned mask 240. In this illustrated embodiment, the patterned mask 240 includes an opening disposed directly above the source / drain components 222P and 222N, and a portion of the dielectric layer is laterally disposed between the source / drain components 222P and 222N.

[0116] When patterned mask 240 is used as an etching mask, an etching process 242 is performed to remove portions of the dielectric layer (e.g., CESL 226, first ILD layer 228, etch stop layer 236, and second ILD layer 238) to form an opening 244. The etching process 242 can be a dry etching process, which includes using argon (Ar), fluorinated etchants (e.g., SF6, NF3, CH2F2, CHF3, C4F8, and / or C2F6), chlorinated etchants (e.g., Cl2, CHCl3, CCl4, and / or BCl3), bromine etchants (e.g., HBr and / or CHBr3), iodine etchants, or combinations thereof. The opening 244 exposes source / drain components 222P and 222N. In this illustrated embodiment, the top and sidewall surfaces of source / drain components 222P and 222N are at least partially exposed. In other words, etching process 242 removes not only a portion of the dielectric layer (e.g., CESL 226, first ILD layer 228, etch stop layer 236, and second ILD layer 238) disposed on the source / drain component 222P and above the source, but also a portion of the dielectric layer (e.g., CESL 226 and first ILD layer 228) disposed between the source / drain component 222P and the source / drain component 222N. Etching process 242 can etch the first ILD layer 228 and the second ILD layer 238 faster than etching CESL 226 and etch stop layer 236. Thus, as... Figure 9B As shown, when etching process 242 is completed, opening 244 includes a portion 244L laterally disposed between source / drain components 222P and 222N and extending from the sidewall of source / drain component 222P to the lower portion 244L of source / drain component 222P. The lower portion 244L is disposed directly above STI component 205 and exposes the top surfaces of the first ILD layer 228 and CESL 226 on STI component 205. Opening 244 further includes an upper portion 244U that exposes the top surfaces of source / drain components 222P and source / drain components 222N.

[0117] Now for reference Figure 1 and Figures 10A-10BMethod 100 includes block 116, in which a dielectric substrate 246 is formed over substrate 202 and in opening 244. In one embodiment, the dielectric substrate 246 is conformally deposited to have a substantially uniform thickness over the top surface of structure 200 (e.g., substantially the same thickness on the top and sidewall surfaces of structure 200) and partially fills opening 244. In this illustrated embodiment, the dielectric substrate 246 extends along the exposed surfaces of source / drain components 222P and 222N, as well as the top surface of CESL 226 and a portion of the first ILD layer 228 disposed directly above STI component 205. The dielectric substrate 246 may be formed by performing a deposition process such as CVD, PECVD, ALD, or other suitable deposition process. In this embodiment, the dielectric substrate 246 is selected to have different elements from the source / drain components 222N and 222P, CESL 226, first ILD layer 228, etch stop layer 236, and second ILD layer 238 and dielectric material layer 248 (e.g., Figure 11A The composition (shown) is designed to ensure that the dielectric substrate 246 has etch selectivity relative to these material layers. In one embodiment, the dielectric substrate 246 may comprise silicon oxycarbide (SiOC). In another embodiment, the dielectric substrate 246 may comprise silicon oxycarbonitrile (SiOCN).

[0118] Now for reference Figure 1 and Figures 11A-11B Method 100 includes block 118, wherein a dielectric material layer 248 is formed over substrate 202 to partially fill opening 244. The dielectric material layer 248 can be deposited using chemical vapor deposition (CVD), physical vapor deposition (PVD), or other suitable processes. In one embodiment, the dielectric material layer 248 is deposited using a physical vapor deposition (PVD) process. Due to the characteristics of the PVD process, the portion of the dielectric material layer 248 formed on the top or flat surface is thicker than the portion formed on the side surfaces. More specifically, as... Figure 11BAs shown, the dielectric material layer 248 includes a first horizontal portion 248a formed above the top surface of the patterned mask 240, a vertical portion 248b extending along the exposed sidewall surface of the opening 244, and a second horizontal portion 248c formed in the opening 244 and located directly above the first ILD layer 228 and the source / drain components 222P and 222N. In one embodiment, the thickness of the second horizontal portion 248c of the dielectric material layer 248 is greater than the thickness of the first horizontal portion 248a of the dielectric material layer 248, and the thickness of the first horizontal portion 248a of the dielectric material layer 248 is greater than the thickness of the second horizontal portion 248c of the dielectric material layer 248. In one embodiment, a portion of the second horizontal portion 248c of the dielectric material layer 248 formed directly above the source / drain components 222P / 222N is thicker than the first horizontal portion 248a of the dielectric material layer 248. In the illustrated embodiment, the second horizontal portion 248c of the dielectric material layer 248 has a non-planar top surface 248s. The top surface 248s can bend inwards most at its midpoint. More specifically, the top surface 248s consists of two segments with different concave curvatures. The left segment exhibits a concave-down, decreasing profile, while the right segment exhibits a concave, increasing profile. Furthermore, the interfaces between the left and right segments of the top surface 238s contribute to the overall unique shape of the top surface 248s.

[0119] In this embodiment, the dielectric layer 248 is selected to have a composition different from that of the source / drain components 222N and 222P and the dielectric substrate 246 to ensure that the dielectric layer 248 has etch selectivity relative to these material layers. In one embodiment, the dielectric layer 248 may comprise silicon oxycarbide (SiOC). In another embodiment, the dielectric layer 248 may comprise silicon oxycarbonitrile (SiOCN). For embodiments where both the dielectric substrate 246 and the dielectric layer 248 comprise the same material (e.g., SiOC or SiOCN), the carbon concentration and / or nitrogen concentration in the dielectric layer 248 differs from the carbon concentration and / or nitrogen concentration in the dielectric substrate 246, such that subsequent etching processes (e.g., ...) Figure 12B The etchant in step 252) etches the dielectric substrate 246 and the dielectric material layer 248 at different etch rates.

[0120] Now for reference Figure 1 , Figures 12A-12B and Figures 13A-13BMethod 100 includes block 120, wherein a dielectric substrate 246 and a dielectric material layer 248 are etched back to form a dielectric structure 256 that partially fills the lower portion 244L of the opening 244. In this illustrative embodiment, the formation steps of the dielectric structure 256 include performing an etching process including a first step 252 (which may be referred to as "first etching process 252") and a second step 254 (which may be referred to as "second etching process 254"). Reference Figures 12A-12B In the first step 252 of the etching process, the dielectric substrate 246 and the dielectric material layer 248 are selectively etched, while the CESL 226, the first ILD layer 228, the etch stop layer 236, and the second ILD layer 238 are not substantially etched. For example, the upper portions of the first horizontal portion 248a, the vertical portion 248b, and the second horizontal portion 248c of the dielectric material layer 248 are removed. The removal of these portions of the dielectric material layer 248 exposes the portions of the dielectric substrate 246 previously covered by these portions of the dielectric material layer 248. The first horizontal and vertical portions of the dielectric substrate 246, which are covered by the first horizontal portion 248a and the vertical portion 248b of the dielectric material layer 248, are exposed earlier than the second horizontal portion of the dielectric substrate 246 covered by the second horizontal portion 248c of the dielectric material layer 248. In this embodiment, the first step 252 of the etching process also etches the dielectric substrate 246 and the dielectric material layer 248 at different rates. More specifically, the first step 252 of the etching process etches the dielectric substrate 246 at a rate higher than that for etching the dielectric material layer 248, such that after the first step 252 of the etching process is completed, at least a portion of the dielectric material layer 248 remains in the lower portion 244L of the opening 244. In this illustrated embodiment, due to the thickness relationship of the different portions of the dielectric material layer 248 and the selection of the etchant in the first step 252 of the etching process, when the first step 252 of the etching process is completed, the recessed dielectric substrate 246 covers the top surfaces of the source / drain components 222P and 222N and extends along the sidewalls and bottom surfaces of the recessed dielectric material layer 248. The recessed dielectric material layer 248 is spaced apart from the sidewall surfaces of the source / drain components 222P and 222N by the recessed dielectric substrate 246. The recessed dielectric layer 248 has a top surface 248s', which has a profile substantially similar to that of the top surface 248s. The top surface 248s' may be lower than the topmost surface of the recessed dielectric substrate 246. The profiles of the recessed dielectric substrate 246 and the recessed dielectric layer 248 can be controlled by the duration of the first step 252 of the etching process. The etchant for the first step 252 of the etching process may include a fluorinated etchant (e.g., CF4, SF6, CH2F2, CHF3 and / or C2F6) or other suitable materials.

[0121] refer to Figures 13A-13BIn the second step 254 of the etching process, the dielectric substrate 246 is selectively etched, while the source / drain components 222P and 222N are not substantially etched. In this embodiment, when the second step 254 of the etching process is completed, the top surface and part of the sidewall surface of the source / drain components 222P and 222N are exposed by removing a portion of the dielectric substrate 246. The second step 254 of the etching process also slightly etches the dielectric material layer 248. The recessed dielectric material layer 248 has a top surface 248s”, which has a contour substantially similar to that of the top surface 248s. More specifically, the top surface 248s” has two segments 248s1 and 248s2 with different concave curvatures. The left segment 248s1 has a concave, decreasing profile, while the right segment 248s2 has a concave, increasing profile. Furthermore, the junction between the left segment 248s1 and the right segment 248s2 of the top surface 248s” contributes to the overall unique shape of the top surface 248s. The second step 254 of the etching process for etching the dielectric substrate 246 can be a dry etching process, which includes using argon (Ar), fluorinated etchants (e.g., SF6, NF3, CH2F2, CHF3, C4F8 and / or C2F6), oxygen-containing etchants, chlorine-containing etchants (… For example, Cl2, CHCl3, CCl4 and / or BCl3), bromine-containing etchants (e.g., HBr and / or CHBr3), iodine-containing etchants, or combinations thereof. In one embodiment, the etchant in the second step 254 of the etching process is different from the etchant in the first step 252 of the etching process. During the second step 254 of the etching process, the etch rate difference between the dielectric substrate 246 and the dielectric material layer 248 is smaller than the etch rate difference between the dielectric substrate 246 and the dielectric material layer 248 during the first step 254. After the second step 254 of the etching process, the combination of the recessed dielectric substrate 246 and the recessed dielectric material layer 248 may be referred to as dielectric structure 256. Figure 13B As shown, the dielectric structure 256 at least partially fills the lower portion 244L of the opening 244. Forming this dielectric structure 256 in the lower portion 244L of the opening 244 reduces the amount of source / drain contacts 262 laterally disposed between the source / drain components 222P and 222N. Figures 16A-16B The volume of a portion of the semiconductor structure 200 (as shown in the diagram) is reduced, and thus the depth of the source / drain contact 262 is reduced. Therefore, the resulting semiconductor structure 200 will have reduced parasitic capacitance compared to a semiconductor structure without dielectric structure 256.

[0122] Now for reference Figure 1 and Figures 14A-14BMethod 100 includes block 122, wherein a dielectric barrier layer 258 is formed in the upper portion 244U of opening 244. After forming dielectric structure 256, in this embodiment, in order to enhance source / drain contacts 262 (such as...), Figures 16A-16B To isolate the opening 200 from its adjacent gate structure 230, a dielectric barrier layer 258 is formed along the sidewall surface of the upper portion 244U of the opening 244. In an exemplary fabrication process, the dielectric layer is conformally deposited over the structure 200 and in the opening 244, and is subsequently etched back to retain only the portion extending along the sidewall surface of the opening 244, thereby forming the dielectric barrier layer 258. In some embodiments, the dielectric barrier layer 258 may comprise silicon nitride, silicon oxide, or other suitable materials.

[0123] refer to Figure 1 , Figures 15A-15B and Figures 16A-16B Method 100 includes block 124, in which silicide layers 260a-260b and source / drain contacts 262 are formed in opening 244. (See reference) Figures 15A-15B After forming the dielectric barrier layer 258, silicide layers 260a-260b and source / drain contacts 262 are formed in the opening 244. To form the silicide layers 260a-260b, a metal precursor (e.g., titanium, tantalum, nickel, cobalt, or tungsten) is deposited over the structure 200, including on the exposed surfaces of the n-type source / drain components 222N and the p-type source / drain components 222P. An annealing process is then performed to induce silicification in a second region 20 between the metal precursor and the exposed semiconductor surfaces and to induce germinidation in the first region 10. In some embodiments, unreacted metal precursor is selectively removed after the formation of the silicide layers 260a-260b. In embodiments where the metal precursor includes nickel, nickel can react with silicon-germanium in the p-type source / drain component 222P to form a silicide layer 260a and can react with silicon in the n-type source / drain component 222N to form a silicide layer 260a. Therefore, silicide layer 260a can include nickel silicide, nickel germanide, and nickel silicide, and silicide layer 260b can include nickel silicide. In this illustrated embodiment, silicide layer 260a is in direct contact with the top and sidewall surfaces of the source / drain component 222P and the dielectric substrate 246 at one end of the dielectric structure 256, and silicide layer 260b is in direct contact with the top and sidewall surfaces of the source / drain component 222N and the dielectric substrate 246 at the other end of the dielectric structure 256.

[0124] refer to Figures 16A-16BA conductive layer is then deposited over structure 200, including in opening 244 and on dielectric structure 256 and silicide layers 260a-260b. The conductive layer may include aluminum (Al), copper (Cu), tungsten (W), cobalt (Co), ruthenium (Ru), or molybdenum (Mo) or other suitable materials and may be formed by any suitable deposition process (e.g., CVD). A planarization process, such as chemical mechanical polishing (CMP), may then be performed to remove excess portions of the conductive layer to form source / drain contacts 262. Although not shown, in some embodiments, source / drain contacts 262 may also include a conductive barrier layer (e.g., TiN, TaN) extending along the sidewalls and bottom surface of the conductive layer. Source / drain contacts 262 follow the shape of opening 244, which is partially filled by dielectric structure 256, dielectric barrier layer 258, and silicide layers 260a-260b. In other words, the bottom surface of the source / drain contact 262 has a surface that is parallel to the top surface 248 (e.g., ...). Figure 13B The outline shown is essentially the same.

[0125] The source / drain contact 262 includes an upper portion 262U above the top surface of the silicide layers 260a-260b and a lower portion 262L disposed between the dielectric structure 256 and the upper portion 262U. The upper portion 262U is similar to a rectangle, and the lower portion 262L is similar to a trapezoid with a unique bottom surface (i.e., top surface 248s"). The lower portion 262L is formed in and above the lower portion 244L of the opening 244, and is therefore laterally disposed between the source / drain components 222P and 222N. The upper portion 262U has a height H1, and the lower portion 262L has a height H2. In one embodiment, the ratio of height H2 to height H1 is less than about 0.6. If this ratio is greater than 0.6, the lower portion 262L of the source / drain contact 262... This may not provide the benefit of reducing the parasitic capacitance between the source / drain contact 262 and the adjacent source / drain components 222N and 222P. In some embodiments, the ratio of height H2 to height H1 is between about 0.1 and about 0.6. In another embodiment, height H2 is substantially equal to 0. That is, the entire source / drain contact 262 is disposed above the source / drain components 222P and 222N. In one embodiment, height H2 may be between about 2 nm and about 8 nm, and height H1 may be between about 10 nm and about 20 nm.

[0126] refer to Figure 1Method 100 includes block 126, in which subsequent processes are performed. After forming silicide layers 260a-260b and source / drain contacts 262, further processes are performed to complete the fabrication of semiconductor structure 200. For example, additional components such as gate vias and interconnect structures may be formed above and / or below structure 200. In some embodiments, the interconnect structure may include multiple intermetallic dielectric (IMD) layers and multiple metal lines or contact vias in each IMD layer. In some cases, the IMD layers and the first IMD layer 228 may have similar compositions. The metal lines and contact vias in each IMD layer may be formed of metal, such as aluminum, tungsten, ruthenium, or copper. In some embodiments, the metal lines and contact vias may be lined with a barrier layer to prevent or reduce electromigration.

[0127] In the above embodiments, the semiconductor structure 200 is implemented using a FinFET. In some other embodiments, the semiconductor structure 200 can be implemented using a GAA transistor. For example, Figures 17A-17B An embodiment is illustrated where the finned active regions 204A-204B include a channel layer 208, wherein the gate structure 230 engages with the channel layer 208 to form a GAA transistor.

[0128] While not intended to be limiting, one or more embodiments of this invention provide numerous benefits for semiconductor structures and their formation. For example, forming a dielectric structure to fill the lower portion of the source / drain contact opening results in a source / drain contact with a higher bottom surface. This advantageously reduces parasitic capacitance between the source / drain contact and its adjacent source / drain components, thereby improving device performance.

[0129] This invention provides many different embodiments. This document discloses semiconductor structures and methods for manufacturing the same. In one exemplary embodiment, this invention relates to a method. This method includes a receiving structure comprising a first source / drain component above a source / drain region of a first finned active region projecting from a substrate, a second source / drain component above a source / drain region of a second finned active region, an isolation component disposed between the first and second finned active regions, and a multilayer dielectric structure above the isolation component and the first and second source / drain components. This method further includes forming an opening extending into the multilayer dielectric structure, wherein the lower portion of the opening exposes the sidewall surfaces of the first and second source / drain components, forming a dielectric component in the lower portion of the opening, and forming source / drain contacts on the dielectric component.

[0130] In some embodiments, the steps of forming the dielectric component may include depositing a dielectric substrate over a substrate and in an opening, forming a dielectric material layer over the dielectric substrate, and performing an etching process to etch back the dielectric substrate and the dielectric material layer. In some embodiments, performing the etching process may include using an etchant that etches the dielectric substrate at a first etch rate and etches the dielectric material layer at a second etch rate different from the first etch rate. In some embodiments, the dielectric substrate and the dielectric material layer may comprise silicon carbonitride and have different nitrogen concentrations. In some embodiments, the dielectric material layer may be spaced apart from a first source / drain component and a second source / drain component by means of the dielectric substrate. In some embodiments, the top surface spans of the dielectric component are a first width, and the bottom surface spans of the dielectric component are a second width smaller than the first width. In some embodiments, this method may further include forming a silicide layer over the dielectric component and in the opening after forming the dielectric component. In some embodiments, the method may further include forming a dielectric barrier layer extending along the sidewall surface of the opening after forming the dielectric component, wherein the source / drain contacts are spaced apart from the multilayer dielectric structure by the dielectric barrier. In some embodiments, the first source / drain component is an n-type source / drain component, and the second source / drain component is a p-type source / drain component.

[0131] In another exemplary embodiment, the present invention relates to a method. This method includes forming a dielectric structure over a substrate, the dielectric structure including a first portion disposed between a first source / drain component and a second source / drain component adjacent to the first source / drain component, and a second portion above the first portion. The method further includes replacing a portion of the first portion of the dielectric structure with a dielectric component having a composition different from that of the dielectric structure, and replacing a portion of the second portion of the dielectric structure with source / drain contacts electrically coupled to the dielectric structure.

[0132] In some embodiments, the dielectric structure may include an etch stop layer conformally extending along the top and sidewall surfaces of the first source / drain component and the second source / drain component, and an interlayer dielectric layer on the etch stop layer. In some embodiments, the dielectric component may include a dielectric fill layer and a dielectric liner extending along the sidewalls and bottom surface of the dielectric fill layer. In some embodiments, the dielectric fill layer may include silicon carbide or silicon carbonitride, and the dielectric liner may include silicon carbide or silicon carbonitride. In some embodiments, the step of replacing a portion of the first portion of the dielectric structure with a dielectric component may include forming a patterned mask over the dielectric structure, removing a portion of the first portion and a portion of the second portion of the dielectric structure to form an opening exposing the top and sidewall surfaces of the first source / drain component and the second source / drain component, and forming the dielectric component in the lower portion of the opening. In some embodiments, the step of replacing a portion of the second part of the dielectric structure with source / drain contacts may include, after forming the opening and the dielectric component, forming a dielectric barrier layer in the opening, forming a silicide layer over the first and second source / drain components, and forming source / drain contacts in the opening and over the dielectric component. In some embodiments, the top surface of the dielectric component is lower than the top surface of the first source / drain component.

[0133] In another exemplary embodiment, the present invention relates to a semiconductor structure. The semiconductor structure includes a first transistor, the first transistor including a first gate structure located above a first channel region and a first source / drain component coupled to the first channel region; a second transistor, the second transistor including a second gate structure located above a second channel region and a second source / drain component coupled to the second channel region; the semiconductor structure further includes a first dielectric structure extending from the lower portion of the first source / drain component to the lower portion of the second source / drain component; a second dielectric structure located above the first dielectric structure and having a composition different from the first dielectric structure; and source / drain contacts electrically coupled to the first and second source / drain components and located on the second dielectric structure.

[0134] In some embodiments, the semiconductor structure may further include a first silicide layer on the first source / drain component and a second silicide layer on the second source / drain component, wherein the second dielectric structure may include a first dielectric layer and a second dielectric layer located above the first dielectric layer, and the first dielectric layer extends from the first silicide layer to the second silicide layer. In some embodiments, the bottom surface of the source / drain contact may be lower than the top surface of the first source / drain component. In some embodiments, the first channel region may include multiple nanostructures.

[0135] The components of several embodiments are outlined above to facilitate a better understanding of the present invention by those skilled in the art. Those skilled in the art should understand that they can design or modify other processes and structures based on the embodiments of the present invention to achieve the same purpose and / or advantages as the embodiments described herein. Those skilled in the art should also understand that such equivalent processes and structures do not depart from the spirit and scope of the present invention, and that they can make various changes, substitutions, and replacements without departing from the spirit and scope of the present invention.

Claims

1. A semiconductor device, characterized by comprising: include: A first transistor, comprising: A first gate structure is located on a first channel region; and A first source / drain component is coupled to the first channel region; A second transistor, comprising: A second gate structure is located on a second channel region; and A second source / drain component is coupled to the second channel region; A first dielectric structure extends from a lower portion of the first source / drain component to a lower portion of the second source / drain component; A second dielectric structure, located above the first dielectric structure and having a composition different from that of the first dielectric structure; and A source / drain contact is electrically coupled to the first source / drain component and the second source / drain component and is located on the second dielectric structure.

2. The semiconductor device according to claim 1, wherein Including: A first silicide layer is located on the first source / drain component; and A second silicide layer is located on the second source / drain component. The second dielectric structure includes a first dielectric layer and a second dielectric layer located above the first dielectric layer, wherein the first dielectric layer extends from the first silicide layer to the second silicide layer.

3. The semiconductor device according to claim 2, wherein The source / drain contact has an upper portion and a lower portion, the upper portion being located above the top surface of the first silicide layer and the second silicide layer, and the lower portion being located between the second dielectric structure and the upper portion.

4. The semiconductor device according to claim 3, wherein In a cross-sectional view, the upper part of the source / drain contact has a rectangular profile, and the lower part of the source / drain contact has a trapezoidal profile.

5. The semiconductor device according to claim 3, wherein The upper part of the source / drain contact has a first height and the lower part of the source / drain contact has a second height, the ratio of the second height to the first height being less than 0.

6.

6. The semiconductor device according to claim 5, wherein The ratio of the second height to the first height is between 0.1 and 0.

6.

7. The semiconductor device according to claim 1, wherein The bottom surface of the source / drain contact is lower than the top surface of the first source / drain component.

8. The semiconductor device according to claim 1, wherein The first channel region includes multiple nanostructures.

9. The semiconductor device according to claim 1, wherein The first gate structure fits the first channel region.

10. The semiconductor device according to claim 1 or 3, wherein The top surface of the first dielectric structure is lower than the top surface of the first source / drain component.

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