Monolithic integrated dc motor driver chip based on ldmos devices

Abstract

The utility model relates to a kind of monolithic integrated direct current motor drive chip based on LDMOS device.It includes at least one drive channel, wherein, for any drive channel, including the H bridge topology circuit and channel main circuit of the DC motor to be driven control adaptive connection;The H bridge topology circuit includes two bridge arm units, and H bridge topology circuit is connected with the DC motor to be driven control by bridge arm unit;For any bridge arm unit, including a N-type LDMOS switch tube and a P-type LDMOS switch tube, wherein, N-type LDMOS switch tube, P-type LDMOS switch tube is prepared on the same substrate, when H bridge topology circuit is driven to control DC motor, N-type LDMOS switch tube and P-type LDMOS switch tube in the same bridge arm unit are configured to be in complementary conduction state.Effectively realize the drive control to DC motor, high integration, and can reduce the conduction loss and dynamic loss when driving control.

Description

Technical Field

[0001] This utility model relates to a driver chip, and more particularly to a monolithic integrated DC motor driver chip based on LDMOS devices. Background Technology

[0002] As a typical application of the integration of power electronics and integrated circuit technology, the core function of DC motor driver chips is to achieve precise control of motor speed, direction, and torque. Currently, the mainstream solution is based on the H-bridge topology circuit architecture. That is, the H-bridge topology circuit is integrated into the DC motor driver chip, and the duty cycle of the voltage output of the H-bridge topology circuit is adjusted through PWM (Pulse Width Modulation) technology, thereby controlling the power output of the DC motor to achieve control of motor speed, direction, and torque.

[0003] In the prior art, H-bridge topology circuits are mostly constructed using power switching devices, which are mostly VDMOS (Vertical Double-diffused Metal-Oxide-Semiconductor), IGBT (Insulated Gate Bipolar Transistor), or SiC MOSFET (SiC Metal-Oxide-Semiconductor Field-Effect Transistor). Specifically, when controlling a DC motor through an H-bridge topology circuit, semiconductor process miniaturization technology can be combined to reduce the conduction loss and switching noise of the power switching devices.

[0004] As application scenarios place increasing demands on the performance of DC motor driver chips (such as high switching frequency, high integration, and low power consumption), the existing methods of DC motor driver chips for driving DC motors are gradually revealing their limitations. Specifically, VDMOS devices have large parasitic capacitance due to their vertical structure, which limits their efficiency in high-frequency scenarios; IGBT devices have insufficient switching speed due to tail current phenomenon; and although SiC MOSFET devices have high-frequency characteristics, their high cost limits their widespread adoption.

[0005] In addition, the power switching devices in the H-bridge topology circuit are mostly discrete devices. The use of discrete devices will result in the H-bridge topology circuit occupying a large area, making it difficult to achieve high power density monolithic integration, which in turn leads to the large size of the DC motor drive chip and the complexity of the peripheral circuit. Summary of the Invention

[0006] The purpose of this invention is to overcome the shortcomings of the existing technology and provide a monolithic integrated DC motor driver chip based on LDMOS devices, which can effectively realize the drive control of DC motors, has high integration, and can reduce conduction loss and dynamic loss during drive control.

[0007] According to the technical solution provided by this utility model, a monolithic integrated DC motor driver chip based on LDMOS devices is provided. The DC motor driver chip includes at least one drive channel capable of driving and controlling a DC motor.

[0008] For any driving channel, there is an H-bridge topology circuit adapted to and connected to the DC motor to be driven and controlled, and a channel main circuit adapted to and connected to the H-bridge topology circuit.

[0009] The H-bridge topology circuit includes two bridge arm units, and the H-bridge topology circuit is adapted to be connected to the DC motor to be driven and controlled through the bridge arm units.

[0010] Each bridge arm unit includes an N-type LDMOS switch and a P-type LDMOS switch adapted and connected to the N-type LDMOS switch, wherein,

[0011] N-type LDMOS switches and P-type LDMOS switches are fabricated on the same substrate.

[0012] When driving and controlling a DC motor via an H-bridge topology circuit, the N-type LDMOS switches and P-type LDMOS switches within the same bridge arm unit are configured to be in a complementary conduction state.

[0013] Both the N-type LDMOS switch and the P-type LDMOS switch are fabricated on at least the P+ substrate, and the N-type LDMOS switch is isolated from the P-type LDMOS switch through the P+ substrate.

[0014] For any bridge arm unit, the source terminal of the P-type LDMOS switch in the bridge arm unit is connected to the drive power supply voltage, the drain terminal of the N-type LDMOS switch, the drain terminal of the P-type LDMOS switch and the DC motor adapter are connected, and the source terminal of the N-type LDMOS switch is grounded.

[0015] The gate terminals of both the N-type LDMOS and P-type LDMOS switches are adapted and connected to the main channel circuit.

[0016] The P-type LDMOS switch includes an N-type epitaxial layer fabricated on a P+ substrate;

[0017] On the cross-section of the P-type LDMOS switch, a P-type drain region is formed on the N-type epitaxial layer, and a P-type switch source-drain region is formed on both sides of the P-type drain region.

[0018] For any P-type switch, the source and drain regions include an N-type well region, a P+ source region, and an N-type deep doped region. The P+ source region is distributed within the N-type well region and the N-type deep doped region. The N-type well region is in contact with the N-type deep doped region, and the junction depth of the N-type deep doped region is greater than that of the N-type well region.

[0019] The N-type well region is in contact with the P-type drain region, and the P+ source region and the N-type deeply doped region are isolated from the P-type drain region through the N-type well region;

[0020] The P-type drain region makes ohmic contact with the drain metal of the P-type switch, the N-type well region and the P-type drain region make ohmic contact with the gate metal of the P-type switch, and the N-type deeply doped region and the P+ source region make ohmic contact with the source metal of the P-type switch.

[0021] The N-type LDMOS switch includes a P-type epitaxial layer fabricated on a P+ substrate;

[0022] On the cross-section of the P-type LDMOS switch, an N-type drain region is formed on the P-type epitaxial layer, and an N-type switch source-drain region is formed on both sides of the N-type drain region.

[0023] For any N-type switch, the source and drain regions include a P-type well region, an N+ source region, and a P-type deep doped region. The N+ source region is distributed within the P-type well region and the P-type deep doped region. The P-type well region is in contact with the P-type deep doped region, and the junction depth of the P-type deep doped region is greater than that of the P-type well region.

[0024] The P-type well region is in contact with the N-type drain region, and the N+ source region and the deeply doped P-type region are isolated from the N-type drain region through the P-type well region;

[0025] The N-type drain region makes ohmic contact with the drain metal of the P-type switch, the P-type well region and the N-type drain region make ohmic contact with the gate metal of the P-type switch, and the P-type deeply doped region and the N+ source region make ohmic contact with the source metal of the P-type switch.

[0026] The channel main circuit includes at least a gate drive circuit unit, a logic circuit, and a level conversion circuit unit, wherein...

[0027] The gate drive circuit unit includes two gate drive circuits. Each gate drive circuit is connected to the gate terminal of an N-type LDMOS switch and the gate terminal of a P-type LDMOS switch in a bridge arm unit, so as to drive the switching state of the connected N-type LDMOS switch and P-type LDMOS switch using the gate drive circuit.

[0028] The gate drive circuits in the gate drive circuit unit are all connected to the logic circuit, and the logic circuit is also adapted to be connected to the level conversion circuit in the level conversion circuit unit.

[0029] The level conversion circuit unit includes at least two level conversion circuits, so as to receive a corresponding drive control sub-signal through one level conversion circuit, convert the drive control sub-signal into a valid drive control logic signal through the level conversion circuit, and load the drive control logic signal into the logic circuit.

[0030] For any level conversion circuit, the input terminal of the level conversion circuit is also connected to a conversion protection circuit, wherein,

[0031] The conversion protection circuit includes a first conversion protection diode, a second conversion protection diode, and a conversion protection resistor. The anode of the first conversion protection diode and the cathode of the second conversion protection diode are both connected to the input terminal of the level conversion circuit. The cathode of the first conversion protection diode is connected to the level conversion power supply, and the anode of the second conversion protection diode is grounded.

[0032] The two ends of the switching protection resistor are connected in parallel with the second switching protection diode.

[0033] For any level-shifting circuit, including NMOS transistors NM2, NMOS transistors NM3, NMOS transistors NM4, and PMOS transistor PM1, where,

[0034] The gate terminals of NMOS transistors NM2, NMOS transistor NMO3, and NMOS transistor NM4 are all connected to drive control sub-signals.

[0035] The drain terminals of NMOS transistor NM2 and NMOS transistor NM3 are connected to one end of resistor R1, the gate terminal of PMOS transistor PM1, and the gate terminal of NMOS transistor NM6. The other end of resistor R1, the source terminal of PMOS transistor PM1, and the substrate of PMOS transistor PM1 are all connected to a level conversion power supply.

[0036] The source terminal of NMOS transistor NM2 is connected to the drain terminal of NMOS transistor NM4, the source terminal of NMOS transistor NM3 is connected to the drain terminal of NMOS transistor NM5, the gate terminal of NMOS transistor NM5 is connected to the drain terminal of PMOS transistor PM1 and the drain terminal of NMOS transistor NM6, and the drain terminal of PMOS transistor PM1 and the drain terminal of NMOS transistor NM6 are connected to each other to form a level conversion output terminal.

[0037] The substrates of NMOS transistor NM2, NMOS transistor NM4, the source terminal of NMOS transistor NM4, the substrates of NMOS transistor NM3, NMOS transistor NM5, the source terminal of NMOS transistor NM5, the substrate of NMOS transistor NM6, and the source terminal of NMOS transistor NM6 are all grounded.

[0038] The main circuit of the channel also includes an over-temperature protection circuit, which is connected to the logic circuit.

[0039] The over-temperature protection circuit includes a temperature protection comparison unit, a temperature sensing circuit, and a reference voltage circuit connected together. The temperature sensing circuit and the reference voltage circuit are respectively connected to the corresponding comparison input terminals of the temperature protection comparison unit, and the output terminal of the temperature protection comparison unit is connected to the logic circuit.

[0040] The reference voltage circuit includes a basic reference voltage circuit and a voltage selection circuit adapted and connected to the basic reference voltage circuit, wherein...

[0041] The output of the voltage selection circuit is connected to the temperature protection comparison unit. The voltage selection circuit is also connected to the logic circuit. The logic circuit selects the corresponding over-temperature protection reference voltage through the voltage selection circuit and applies the selected over-temperature protection reference voltage to the corresponding comparison input of the temperature protection comparison unit. The temperature protection comparison unit then compares the over-temperature protection reference voltage with the temperature sensing voltage generated by the temperature sensing circuit.

[0042] The voltage selection circuit includes at least one voltage selection unit, wherein...

[0043] Each voltage selection unit includes two voltage selection branches, wherein each voltage selection branch includes one selection branch PMOS transistor and one selection branch NMOS transistor.

[0044] For any voltage selection unit, the gate terminals of the PMOS transistor in the selection branch and the NMOS transistor in the selection branch of one voltage selection branch are connected to a voltage selection control signal generated by the logic circuit, and the gate terminals of the PMOS transistor in the selection branch and the NMOS transistor in the selection branch of another voltage selection branch are connected to another voltage selection control signal generated by the logic circuit.

[0045] The basic circuit for reference voltage must provide at least two different over-temperature protection reference voltages;

[0046] Within each voltage selection unit, the source terminal of the PMOS transistor in one voltage selection branch is connected to the source terminal of the NMOS transistor in another voltage selection branch, and both are connected to an over-temperature protection reference voltage provided by the reference voltage basic circuit.

[0047] Within each voltage selection unit, the drain terminals of all selection branch PMOS transistors and all selection branch NMOS transistors are interconnected, forming a voltage selection output terminal. The selected over-temperature protection reference voltage is then applied to the corresponding comparison input terminal of the temperature protection comparison unit through the voltage selection output terminal.

[0048] Within each voltage selection unit, the substrates of all selection branch PMOS transistors are connected to the over-temperature protection power supply voltage, and the substrates of all selection branch NMOS transistors are grounded.

[0049] Advantages of this invention: The DC motor driver chip includes at least one driving channel, which includes an H-bridge topology circuit and a channel main circuit. Each bridge arm unit in the H-bridge topology circuit includes an N-type LDMOS switch and a P-type LDMOS switch fabricated on the same substrate, thereby reducing the area of ​​the H-bridge topology circuit and improving the integration of the DC motor driver chip.

[0050] Furthermore, since N-type LDMOS and P-type LDMOS switches have low on-resistance and high switching frequency characteristics, H-bridge topology circuits can significantly reduce conduction losses and dynamic losses when controlling DC motor drives. Attached Figure Description

[0051] Figure 1 This is a structural block diagram of one embodiment of the DC motor drive chip of this utility model.

[0052] Figure 2 This is an equivalent schematic diagram of an embodiment of the H-bridge topology circuit of this utility model connected to a DC motor.

[0053] Figure 3 This is an equivalent schematic diagram of an embodiment of the present invention that uses an H-bridge topology circuit to drive a DC motor in forward rotation mode.

[0054] Figure 4 This is an equivalent schematic diagram of an embodiment of the present invention that uses an H-bridge topology circuit to drive a DC motor in reverse mode.

[0055] Figure 5 This is an equivalent schematic diagram of an embodiment of the present invention that uses an H-bridge topology circuit to drive a DC motor into standby mode.

[0056] Figure 6 This is an equivalent schematic diagram of an embodiment of the present invention that uses an H-bridge topology circuit to drive a DC motor into braking mode.

[0057] Figure 7 for Figure 5 This is an equivalent schematic diagram of an embodiment of the present invention that uses an H-bridge topology circuit to drive a DC motor into standby mode.

[0058] Figure 8 This is a schematic diagram of an embodiment of the present invention in which N-type LDMOS switching transistors and P-type LDMOS switching transistors are fabricated on the same substrate.

[0059] Figure 9 This is a circuit diagram of one embodiment of the level conversion circuit of this utility model.

[0060] Figure 10 This is a circuit diagram of one embodiment of the over-temperature protection circuit of this utility model.

[0061] Explanation of reference numerals in the attached figures: 1-First power supply terminal of the first driving channel; 2-First signal terminal of the first driving channel; 3-Second signal terminal of the second driving channel; 4-Second power supply terminal of the first driving channel; 5-First power supply terminal of the second driving channel; 6-First signal terminal of the second driving channel; 7-Second signal terminal of the second driving channel; 8-Second power supply terminal of the second driving channel; 9-Second driving connection terminal of the second channel; 10-Second ground terminal of the second channel; 11-First driving connection terminal of the second channel; 12-Second driving connection terminal of the first channel; 13-First ground terminal of the first channel; 14-First driving connection terminal of the first channel; 100-P+ substrate; 1 01 - Spacer region, 102 - P-type epitaxial layer, 103 - N-type epitaxial layer, 104 - N-type drain region, 105 - P-type drain region, 106 - P-type deep doped region, 107 - P-well region, 108 - N+ ohmic contact region, 109 - P-type switch drain metal, 110 - P-type switch source metal, 111 - P-type switch gate metal, 112 - N+ source region, 113 - N-type deep doped region, 114 - N-well region, 115 - P+ source region, 116 - N-type switch gate metal, 117 - P+ ohmic contact region, 118 - N-type switch drain metal, 119 - N-type switch source metal. Detailed Implementation

[0062] The present invention will be further described below with reference to the specific accompanying drawings and embodiments.

[0063] To effectively control DC motor drives, improve the integration of DC motor driver chips, and reduce conduction and dynamic losses during drive control, this invention provides a monolithic integrated DC motor driver chip based on LDMOS devices. Specifically, the DC motor driver chip includes at least one drive channel for controlling the DC motor drive.

[0064] For any driving channel, there is an H-bridge topology circuit adapted to and connected to the DC motor to be driven and controlled, and a channel main circuit adapted to and connected to the H-bridge topology circuit.

[0065] The H-bridge topology circuit includes two bridge arm units, and the H-bridge topology circuit is adapted to be connected to the DC motor to be driven and controlled through the bridge arm units.

[0066] Each bridge arm unit includes an N-type LDMOS switch and a P-type LDMOS switch adapted and connected to the N-type LDMOS switch, wherein,

[0067] N-type LDMOS switches and P-type LDMOS switches are fabricated on the same substrate.

[0068] When driving and controlling a DC motor via an H-bridge topology circuit, the N-type LDMOS switches and P-type LDMOS switches within the same bridge arm unit are configured to be in a complementary conduction state.

[0069] It should be noted that the DC motor driver chip of this utility model can realize the drive control of the DC motor. After the DC motor is driven and controlled, the working mode of the DC motor can generally include driving the DC motor in forward rotation mode, driving the main motor in reverse rotation mode, driving the DC motor in standby mode, and / or driving the DC motor in braking mode. Specifically, forward rotation mode means that the DC motor is in a forward rotation state, reverse rotation mode means that the DC motor is in a reverse rotation state, standby mode means that the DC motor is in a non-working state, and braking mode means that the DC motor is in a braking state, which can make the speed of the DC motor eventually approach 0.

[0070] To enable the drive control of DC motors, a DC motor driver chip must have at least one drive channel. This means that one drive channel can drive and control one DC motor. Therefore, when a DC motor driver chip includes multiple drive channels, it can simultaneously drive and control multiple DC motors. The number of drive channels within the DC motor driver chip can be selected as needed to meet the specific application requirements. Figure 1 The image shows an embodiment of a DC motor driver chip that includes two drive channels, from which it can be seen that... Figure 1 The DC motor driver chip in the chip can simultaneously drive and control two DC motors. Generally, the drive channels within the DC motor driver chip can use the same form; however, different forms can also be used, depending on the needs. The following explanation assumes that the drive channels use the same form.

[0071] Specifically, each drive channel should include at least an H-bridge topology circuit and a channel main circuit adapted and connected to the H-bridge topology circuit. As can be seen from the above description, the drive control form of each drive channel for the DC motor can be consistent with the prior art. Each drive channel is adapted and connected to the DC motor to be driven and controlled through the H-bridge topology circuit. The drive control of the DC motor can be realized through the cooperation of the H-bridge topology circuit and the channel main circuit, thereby effectively realizing the drive control of the DC motor.

[0072] It should be noted that the H-bridge topology circuit of this utility model can adopt the same form as the prior art. For example, the H-bridge topology circuit may include two bridge arm units. One bridge arm unit forms one bridge arm in the H-bridge topology circuit. The two bridge arm units can be adapted and connected to form the H-bridge topology circuit. The situation of forming the H-bridge topology circuit can be referred to the corresponding description below.

[0073] In order to improve the integration of DC motor driver chips and reduce conduction and dynamic losses during drive control, in one embodiment of this invention, each bridge arm unit includes an N-type LDMOS switch and a P-type LDMOS switch. That is, a bridge arm unit can be formed by adapting and connecting the N-type LDMOS switch and the P-type LDMOS switch. For any bridge arm unit, the source terminal of the P-type LDMOS switch in the bridge arm unit is connected to the drive power supply voltage, and the drain terminal of the N-type LDMOS switch, the drain terminal of the P-type LDMOS switch and the DC motor adapter are connected, while the source terminal of the N-type LDMOS switch is grounded.

[0074] Furthermore, by fabricating N-type LDMOS switches and P-type LDMOS switches on the same substrate, the area of ​​the H-bridge topology circuit can be reduced, and the integration density of the DC motor driver chip can be improved. Specifically, N-type LDMOS switches and P-type LDMOS switches can be fabricated on at least the P+ substrate, and the N-type LDMOS switches are isolated from the P-type LDMOS switches through the P+ substrate, so that the N-type LDMOS switches and P-type LDMOS switches are independent of each other.

[0075] As explained above, the N-type LDMOS switch is an LDMOS transistor with an N-type conductive channel, which is the NMOS transistor in the conventional sense, and the P-type LDMOS switch is an LDMOS transistor with a P-type conductive channel, which is the PMOS transistor in the conventional sense. Since the on-resistance of the N-type LDMOS switch is typically about 0.1045Ω, and the on-resistance of the P-type LDMOS switch is about 0.25Ω, and both N-type and P-type LDMOS switches have high switching frequency characteristics, the H-bridge topology circuit of this invention can significantly reduce conduction losses and dynamic losses when used for DC motor drive control.

[0076] It should be understood that when driving and controlling a DC motor through an H-bridge topology circuit, if the DC motor needs to be in different operating modes, the corresponding switching states of the N-type LDMOS and P-type LDMOS switches in different bridge arm units within the H-bridge topology circuit should be configured. Specifically, the gate terminals of both the N-type and P-type LDMOS switches are adapted and connected to the main channel circuit so that the main channel circuit can load corresponding PWM signals into the H-bridge topology circuit, thereby using the PWM signals to regulate the corresponding switching states of the N-type and P-type LDMOS switches. Furthermore, the N-type and P-type LDMOS switches within the same bridge arm unit are configured to be in a complementary conduction state. Specifically, a complementary conduction state means that the N-type and P-type LDMOS switches within the same bridge arm unit will not be in a conducting state simultaneously.

[0077] Figure 2 The image shows an embodiment of connecting an H-bridge topology circuit with a DC motor to form an equivalent circuit. Figure 2 In the diagram, L represents the equivalent inductance of the DC motor. P-type LDMOS switch Q1 and N-type LDMOS switch Q3 form one bridge arm unit, and P-type LDMOS switch Q2 and N-type LDMOS switch Q4 form another bridge arm unit. Figure 2 The text shows the use of... Figure 1 A schematic diagram showing the drive channel at the top driving the DC motor. (From...) Figure 1 and Figure 2 It can be seen that the source terminals of both the P-type LDMOS switch Q1 and the P-type LDMOS switch Q2 are connected to the power supply V. dd Power supply V dd It can be provided by the second power supply terminal 4 of the first drive channel. The source terminals of N-type LDMOS switch Q3 and N-type LDMOS switch Q4 are grounded. The drain terminals of N-type LDMOS switch Q3 and P-type LDMOS switch Q1 are connected to the first control terminal of the DC motor. The drain terminals of N-type LDMOS switch Q4 and P-type LDMOS switch Q2 are connected to the second control terminal of the DC motor.

[0078] Figure 3 The figure illustrates an embodiment of controlling a DC motor in forward rotation mode using an H-bridge topology circuit. In the figure, P-type LDMOS switch Q1 and N-type LDMOS switch Q4 are both in the on state, while N-type LDMOS switch Q3 and P-type LDMOS switch Q2 are both in the off state. At this time, half-bridge output terminal A in the H-bridge topology circuit is at a high level, half-bridge output terminal B is at a low level, and the load current flows from half-bridge output terminal A to half-bridge output terminal B, and then flows to GND. At this time, the motor is in forward rotation mode.

[0079] Specifically, half-bridge output terminal A is the node formed by connecting the drain terminals of P-type LDMOS switch Q1 and N-type LDMOS switch Q3, and half-bridge output terminal B is the node formed by connecting the drain terminals of P-type LDMOS switch Q2 and N-type LDMOS switch Q4. The following explanations of half-bridge output terminal A and half-bridge output terminal B have the same meaning.

[0080] Figure 4 The figure illustrates an embodiment of controlling a DC motor in reverse mode using an H-bridge topology. In the figure, P-type LDMOS switch Q2 and N-type LDMOS switch Q3 are both on, while N-type LDMOS switch Q1 and P-type LDMOS switch Q4 are both off. At this time, the half-bridge output terminal A is low, the bridge output terminal B is high, and the load current flows from the power supply V. dd The current flows from half-bridge output B to half-bridge output A, and then to GND. At this point, the motor is in reverse rotation mode. It should be noted that in reverse rotation mode, the direction of rotation of the motor shaft inside the DC motor is opposite to the corresponding direction of rotation in forward rotation mode.

[0081] Figure 5 The figure illustrates an embodiment of controlling a DC motor in standby mode using an H-bridge topology circuit. In the figure, the P-type LDMOS switch Q2 and the N-type LDMOS switch Q3 are both in the off state, and the N-type LDMOS switch Q1 and the P-type LDMOS switch Q4 are also in the off state. At this time, the half-bridge output terminals A and B are in the floating state. Since there is no voltage difference between the half-bridge output terminals A and B, the DC motor does not work.

[0082] Figure 6 The figure illustrates an embodiment of controlling a DC motor in braking mode using an H-bridge topology circuit. In the figure, P-type LDMOS switches Q1 and Q2 are both off, while N-type LDMOS switches Q3 and Q4 are both on. At this time, both half-bridge output terminals A and B are connected to GND and are at a low level. The levels of half-bridge output terminals A and B are equal, and the DC motor does not work. However, since the DC motor was in forward or reverse mode before braking mode, the circuit formed by the on-state of N-type LDMOS switches Q3 and Q4 generates a back electromotive force to decelerate the DC motor until it stops.

[0083] As explained above, a DC motor can be equivalent to an inductor. Therefore, in the operation of the H-bridge topology circuit, the high switching frequency of the LDMOS switch can be combined with the continuous current of the inductor. Furthermore, by adjusting the PWM, the average value of the output current can be adjusted, optimizing system efficiency and achieving more precise control. In addition, the inductor smooths the current ripple through the energy storage-release process, reducing the current surge of the LDMOS switch during switching and extending device lifespan. Figure 7 As shown. Although the inductor generates a large back electromotive force during current commutation, the high voltage rating of the LDMOS switch can just compensate for this drawback.

[0084] Furthermore, since the body diode of the LDMOS switch itself can prevent the flow of reverse current, there is almost no reverse current when the LDMOS switch is turned off, which reduces the power consumption of the DC motor driver chip in standby mode. In addition, it can also improve the reliability and dynamic response capability of DC motor drive control.

[0085] When using Figure 1 When the drive conduction at the bottom of the DC motor driver chip controls the DC motor drive, please refer to the corresponding instructions above. As shown in the diagram, Figure 1 In this circuit, the P-type LDMOS switch Q5 and the N-type LDMOS switch Q7 form one bridge arm unit, and the P-type LDMOS switch Q6 and the N-type LDMOS switch Q8 form another bridge arm unit. The two bridge arm units form an H-bridge topology circuit, and the drive control method for the connected DC motor can be referred to the above description, which will not be repeated here.

[0086] In one embodiment of the present invention, the P-type LDMOS switch includes an N-type epitaxial layer 103 fabricated on a P+ substrate 100;

[0087] On the cross-section of the P-type LDMOS switch, a P-type drain region 105 is provided on the N-type epitaxial layer 103, and a P-type switch source-drain region is provided on both sides of the P-type drain region 105.

[0088] For any P-type switch, the source and drain regions include an N-type well region 114, a P+ source region 115, and an N-type deep doped region 113. The P+ source region 115 is distributed within the N-type well region 114 and the N-type deep doped region 113. The N-type well region 114 is in contact with the N-type deep doped region 113, and the junction depth of the N-type deep doped region 113 is greater than the junction depth of the N-type well region 114.

[0089] The N-type well region 114 is in contact with the P-type drain region 105, and the P+ source region 115 and the N-type deeply doped region 113 are isolated from the P-type drain region 105 through the N-type well region 114.

[0090] The P-type drain region 105 is in contact with the drain metal 118 ohms of the P-type switch, the N-type well region 114 and the P-type drain region 105 are in contact with the gate metal 116 ohms of the P-type switch, and the N-type deeply doped region 113 and the P+ source region 115 are in contact with the source metal 119 ohms of the P-type switch.

[0091] Figure 8 The figure shows an embodiment in which a P-type LDMOS switch and an N-type LDMOS switch are fabricated simultaneously on the same P+ substrate 100. As can be seen from the figure, in order to fabricate a P-type LDMOS switch, an N-type epitaxial layer 103 should be fabricated on the P+ substrate 100. Generally, the depth of the N-type epitaxial layer 103 is less than the thickness of the P+ substrate 100.

[0092] A P-type drain region 105 is provided within the N-type epitaxial layer 103. A P+ ohmic contact region 117 can be provided within the P-type drain region 105. The doping concentration of the P+ ohmic contact region 117 is greater than that of the P-type drain region 105. The reliability of the ohmic contact between the P-type drain region 105 and the drain metal 118 of the P-type switch can be improved through the P+ ohmic contact region 117.

[0093] Figure 8 In the N-well region 114, the P-type drain region 105 is in contact, and the maximum junction depth of the N-well region 114 is greater than the junction depth of the P-type drain region 105. The maximum junction depth of the N-type deep doped region 113 is greater than the junction depth of the N-well region 114. The junction depth of the P+ source region 115 is less than the junction depth of the N-type well region 114 and the N-type deep doped region 113.

[0094] The drain electrode of the P-type LDMOS switch can be formed through the drain metal 118 of the P-type switch, the gate electrode of the P-type LDMOS switch can be formed through the gate metal 116 of the P-type switch, and the source electrode of the P-type LDMOS switch can be formed through the source metal 119 of the P-type switch.

[0095] In one embodiment of the present invention, the N-type LDMOS switch includes a P-type epitaxial layer 102 fabricated on a P+ substrate 100;

[0096] On the cross-section of the P-type LDMOS switch, an N-type drain region 104 is provided on the P-type epitaxial layer 102, and an N-type switch source-drain region is provided on both sides of the N-type drain region 104.

[0097] For any N-type switch, the source and drain regions include a P-type well region 107, an N+ source region 112, and a P-type deep-doped region 106. The N+ source region 113 is distributed within the P-type well region 107 and the P-type deep-doped region 106. The P-type well region 107 is in contact with the P-type deep-doped region 106, and the junction depth of the P-type deep-doped region 106 is greater than the junction depth of the P-type well region 107.

[0098] The P-type well region 107 is in contact with the N-type drain region 104, and the N+ source region 112 and the P-type deeply doped region 106 are isolated from the N-type drain region 104 through the P-type well region 107.

[0099] The N-type drain region 104 is in ohmic contact with the drain metal 109 of the P-type switch, the P-type well region 107 and the N-type drain region 104 are in ohmic contact with the gate metal 111 of the P-type switch, and the P-type deep doped region 106 and the N+ source region 112 are in ohmic contact with the source metal 110 of the P-type switch.

[0100] Figure 8 The figure illustrates an embodiment of an N-type LDMOS switch. As shown in the figure, the N-type LDMOS switch can adopt the same structural form as the P-type LDMOS switch; the difference lies in the type of conductive channel formed. Figure 8 In this process, a gap region 101 is formed between the N-type LDMOS switch and the P-type LDMOS switch, and the gap region 101 can be used to separate the N-type LDMOS switch and the P-type LDMOS switch.

[0101] For the N-type LDMOS switch, please refer to the description of the P-type LDMOS switch above. As can be seen from the above description, an N+ ohm contact region 108 can be provided in the N-type drain region 104, and the N+ ohm contact region 108 can make ohmic contact with the drain metal 109 of the P-type switch.

[0102] It should be noted that when N-type LDMOS switches and P-type LDMOS switches adopt the above-mentioned forms, the specific working principle can be consistent with the existing technology, and will not be elaborated here.

[0103] In one embodiment of this utility model, the channel main circuit includes at least a gate drive circuit unit, a logic circuit, and a level conversion circuit unit, wherein...

[0104] The gate drive circuit unit includes two gate drive circuits. Each gate drive circuit is connected to the gate terminal of an N-type LDMOS switch and the gate terminal of a P-type LDMOS switch in a bridge arm unit, so as to drive the switching state of the connected N-type LDMOS switch and P-type LDMOS switch using the gate drive circuit.

[0105] The gate drive circuits in the gate drive circuit unit are all connected to the logic circuit, and the logic circuit is also adapted to be connected to the level conversion circuit in the level conversion circuit unit.

[0106] Figure 1The diagram illustrates one embodiment of the channel main circuit. As shown, the gate drive circuit includes two gate drive circuits, each connected to a corresponding bridge arm unit within the H-bridge topology. Specifically, each gate drive circuit is connected to the gate terminals of the N-type LDMOS and P-type LDMOS switches within its corresponding bridge arm unit. As explained above, the method of driving and controlling a DC motor using this invention is consistent with existing methods. Therefore, the gate drive circuit, logic circuit, and level conversion circuit can adopt commonly used forms, specifically designed to load corresponding PWM signals to the gate terminals of the N-type and P-type LDMOS switches through the gate drive circuit.

[0107] In one embodiment of this utility model, the level conversion circuit unit includes at least two level conversion circuits, so as to receive a corresponding drive control sub-signal through one level conversion circuit, and convert the drive control sub-signal into a valid drive control logic signal through the level conversion circuit, and load the drive control logic signal into the logic circuit.

[0108] For any level conversion circuit, the input terminal of the level conversion circuit is also connected to a conversion protection circuit, wherein,

[0109] The conversion protection circuit includes a first conversion protection diode, a second conversion protection diode, and a conversion protection resistor. The anode of the first conversion protection diode and the cathode of the second conversion protection diode are both connected to the input terminal of the level conversion circuit. The cathode of the first conversion protection diode is connected to the level conversion power supply, and the anode of the second conversion protection diode is grounded.

[0110] The two ends of the switching protection resistor are connected in parallel with the second switching protection diode.

[0111] As can be seen from the above explanation, Figure 1 An embodiment with two drive channels is shown in the figure. Figure 1 In the upper driving channel, there are two level conversion circuits, namely level conversion circuit VZ1 and level conversion circuit VZ2. In level conversion circuit VZ1, diode D1 forms the first conversion protection diode in the corresponding conversion protection circuit, diode D2 forms the second conversion protection diode in the corresponding conversion protection circuit, and resistor R10 forms the corresponding conversion protection resistor. In level conversion circuit VZ2, diode D3 forms the first conversion protection diode in the corresponding conversion protection circuit, D4 forms the second conversion protection diode in the corresponding conversion protection circuit, and resistor R20 forms the corresponding conversion protection resistor.

[0112] Figure 1In this configuration, the anode of diode D1 is connected to the first signal terminal 2 of the first driving channel, and the cathode of diode D1 is connected to the first power supply terminal 1 of the first driving channel, through which power supply VCC1 can be provided. The source terminal of the P-type LDMOS switch is connected to the second power supply terminal 4 of the first driving channel, through which power supply VDD1 can be provided. The anode of diode D3 is connected to the second signal terminal 3 of the first driving channel, through which corresponding drive control sub-signals can be received respectively. The drain terminals of P-type LDMOS switch Q1 and N-type LDMOS switch Q3 are connected to the first driving connection terminal 14 of the first channel, and the drain terminals of P-type LDMOS switch Q2 and N-type LDMOS switch Q4 are connected to the second driving connection terminal 13 of the first channel. The source terminals of N-type LDMOS switch Q3 and N-type LDMOS switch Q4 are connected to the ground terminal 13 of the first channel.

[0113] As explained above, seven terminals should be provided on the DC motor driver chip for each drive channel. Therefore, for Figure 1 The drive channel below should also include seven terminals. Specifically, the seven terminals are: 5. First power supply terminal of the second drive channel; 6. First signal terminal of the second drive channel; 7. Second signal terminal of the second drive channel; 8. Second power supply terminal of the second drive channel; 9. Second drive connection terminal of the second channel; 10. Ground terminal of the second channel; and 11. The configuration of the seven terminals can be found in the reference section. Figure 1 And the corresponding explanations mentioned above will not be repeated here. Of course, Figure 1 For details on the main circuit of the middle and lower channels, please refer to the following: Figure 1 And the corresponding explanations mentioned above.

[0114] In one embodiment of this utility model, any level conversion circuit includes NMOS transistors NM2, NMOS transistors NM3, NMOS transistors NM4, and PMOS transistor PM1, wherein...

[0115] The gate terminals of NMOS transistors NM2, NMOS transistor NMO3, and NMOS transistor NM4 are all connected to drive control sub-signals.

[0116] The drain terminals of NMOS transistor NM2 and NMOS transistor NM3 are connected to one end of resistor R1, the gate terminal of PMOS transistor PM1, and the gate terminal of NMOS transistor NM6. The other end of resistor R1, the source terminal of PMOS transistor PM1, and the substrate of PMOS transistor PM1 are all connected to a level conversion power supply.

[0117] The source terminal of NMOS transistor NM2 is connected to the drain terminal of NMOS transistor NM4, the source terminal of NMOS transistor NM3 is connected to the drain terminal of NMOS transistor NM5, the gate terminal of NMOS transistor NM5 is connected to the drain terminal of PMOS transistor PM1 and the drain terminal of NMOS transistor NM6, and the drain terminal of PMOS transistor PM1 and the drain terminal of NMOS transistor NM6 are connected to each other to form a level conversion output terminal.

[0118] The substrates of NMOS transistor NM2, NMOS transistor NM4, the source terminal of NMOS transistor NM4, the substrates of NMOS transistor NM3, NMOS transistor NM5, the source terminal of NMOS transistor NM5, the substrate of NMOS transistor NM6, and the source terminal of NMOS transistor NM6 are all grounded.

[0119] Figure 9 The diagram shows a schematic representation of one embodiment of a level conversion circuit. Figure 9 VIN in the diagram is a drive control sub-signal, which is also the input terminal of the level conversion circuit formed by receiving VIN. Figure 9 VZH in the diagram is the output terminal of the level conversion circuit, which is connected to the logic circuit through the VZH terminal.

[0120] right Figure 9 The level shifting circuit shown turns on NMOS transistors NM2 and NM4 when the drive control sub-signal VIN is active. Subsequently, the gate of PMOS transistor PM1 is pulled low, turning it on. After PM1 is turned on, the output of the level shifting circuit is connected to the power supply VCC and maintains a high-level output. Simultaneously, NMOS transistor NM6 is on, while the gates of PMOS transistors PM1 and NMOS transistor NM6 remain low. During this process, voltage division is achieved through resistor R1.

[0121] When the drive control sub-signal VIN is in an inactive state, NMOS transistors NM2, NMOS transistors NM4, and NMOS transistors NM3 are all in the off state. The voltage division of resistor R1 decreases, which leads to an increase in the gate voltage of PMOS transistor PM1 and the gate voltage of NMOS transistor NM6. At this time, NMOS transistor NM6 is turned on, and the output of the level conversion circuit is grounded, that is, the output of the level conversion circuit is at a low level.

[0122] Specifically, when the drive control sub-signal VIN is in an invalid state, it is at a 0 level. Therefore, the validity or invalidity of the drive control sub-signal VIN can be determined based on its status. As explained above, the level conversion circuit mainly converts the received valid drive control sub-signal VIN to a high level to meet the subsequent processing requirements of the logic circuit.

[0123] Figure 9 This also includes NMOS transistor NM1, where both the gate and source terminals of NMOS transistor NM1 are grounded, and the drain terminal of NMOS transistor NM1 receives the drive control signal VIN. Therefore, NMOS transistor NM1 is used as a diode to prevent reverse power connection. From the above explanation, it can be seen that the power supply VCC is the level conversion power supply, and VCC should be related to the drive channel where the level conversion circuit is located. Figure 1 In the above driving channel, when the level conversion circuit is the above driving channel, the power supply VCC should be provided by the first power supply terminal 1 of the first driving channel.

[0124] In one embodiment of this utility model, the main channel circuit further includes an over-temperature protection circuit for over-temperature protection, which is connected to the logic circuit.

[0125] The over-temperature protection circuit includes a temperature protection comparison unit, a temperature sensing circuit, and a reference voltage circuit connected together. The temperature sensing circuit and the reference voltage circuit are respectively connected to the corresponding comparison input terminals of the temperature protection comparison unit, and the output terminal of the temperature protection comparison unit is connected to the logic circuit.

[0126] Figure 1 In the embodiment of the channel main circuit shown, an over-temperature protection circuit is provided in each channel main circuit. The over-temperature protection circuit is connected to the logic circuit. The over-temperature protection circuit can be used to realize over-temperature protection in the DC motor drive control.

[0127] To achieve over-temperature protection, an over-temperature protection circuit typically includes a temperature sensing circuit, a temperature protection comparison unit, and a reference voltage circuit. The temperature sensing circuit acquires the current temperature status, the reference voltage circuit provides a voltage that does not change with temperature, and the temperature protection comparison unit compares these values ​​to determine if an over-temperature condition has occurred. When an over-temperature condition occurs, the logic circuit executes over-temperature protection. The method of executing over-temperature protection can be consistent with existing methods, such as cutting off / stopping the drive control of a DC motor.

[0128] Figure 10The figure illustrates one embodiment of a temperature sensing circuit and a temperature protection comparator unit. As shown in the figure, the temperature sensing circuit may include a PNP transistor T1, wherein the base and collector terminals of the PNP transistor T1 are both grounded, and the emitter terminal of the PNP transistor T1 is connected to a comparator input terminal of the temperature protection comparator unit. Figure 10 In the diagram, the emitter terminal of the PNP transistor T1 is connected to the comparator input IN+.

[0129] Figure 10 An embodiment of the temperature protection comparator unit is also shown. Figure 10 In this temperature protection comparator unit, PMOS transistors PM5 and PM6 are used. PM5 and PM6 form a differential PMOS pair. One comparator input is formed using the gate terminal of PM5, and the other comparator input is formed using the gate terminal of PM6. Figure 10 In this configuration, the gate terminal of PMOS transistor PM6 forms the comparator input IN-, and the gate terminal of PMOS transistor PM5 forms the comparator input IN+.

[0130] Figure 10 In this circuit, the substrates of PMOS transistors PM5 and PM6 are connected to the power supply VCC. The source terminals of PMOS transistors PM5 and PM6 are connected to the drain terminal of PMOS transistor PM3. The gate terminal of PMOS transistor PM3 is connected to the drain terminal of PMOS transistor PM2, the gate terminal of PMOS transistor PM2, and the gate terminal of PMOS transistor PM4. The source terminal of PMOS transistor PM2, the substrate of PMOS transistor PM2, the substrate of PMOS transistor PM3, the source terminal of PMOS transistor PM4, and the substrate of PMOS transistor PM4 are all connected to the power supply VCC. The details of the power supply VCC can be found in the corresponding description of the level conversion circuit above, and will not be repeated here.

[0131] The drain terminal of PMOS transistor PM5 is connected to the drain terminal of NMOS transistor NM7, the gate terminal of NMOS transistor NM7, and the gate terminal of NMOS transistor NM8. The substrate, source terminal, substrate, and source terminal of NMOS transistor NM7 are all grounded. The drain terminal of NMOS transistor NM8 is connected to the source terminal of PMOS transistor PM6 and the gate terminal of NMOS transistor NM9. The source terminal and substrate of NMOS transistor NM9 are all grounded.

[0132] The drain terminals of NMOS transistor NM9 and PMOS transistor PM4 are connected to form the output terminal of the temperature protection comparator. Figure 10In this context, OUT is the output terminal of the temperature protection comparator. It can be understood that the output terminal of the temperature protection comparator is also the output terminal of the over-temperature protection circuit. Therefore, the output terminal of the temperature protection comparator should be connected to the logic circuit.

[0133] In one embodiment of this utility model, the reference voltage circuit includes a basic reference voltage circuit and a voltage selection circuit adapted and connected to the basic reference voltage circuit, wherein...

[0134] The output of the voltage selection circuit is connected to the temperature protection comparison unit. The voltage selection circuit is also connected to the logic circuit. The logic circuit selects the corresponding over-temperature protection reference voltage through the voltage selection circuit and applies the selected over-temperature protection reference voltage to the corresponding comparison input of the temperature protection comparison unit. The temperature protection comparison unit then compares the over-temperature protection reference voltage with the temperature sensing voltage generated by the temperature sensing circuit.

[0135] To provide corresponding over-temperature protection reference voltages under different conditions, the reference voltage circuit may include a basic reference voltage circuit and a voltage selection circuit. The basic reference voltage circuit can provide multiple over-temperature protection reference voltages, and the voltage selection circuit can select the appropriate over-temperature protection reference voltage as needed. The selected over-temperature protection reference voltage is then applied to the comparison input terminal of the temperature protection comparator unit. Figure 10 The comparison input IN- in the middle.

[0136] Figure 10 The figure illustrates one embodiment of a basic reference voltage circuit. The circuit includes resistors R2, R3, and R4 connected in series. One end of resistor R2 is connected to the reference voltage Vref, and the other end of R2 is connected to one end of resistor R4 via resistor R3. The other end of resistor R4 is grounded. Therefore, the basic reference voltage circuit can be a resistive voltage divider network. The reference voltage Vref is generally provided by a bandgap reference, and the reference voltage Vref does not change with temperature. Figure 10 In the circuit, the over-temperature protection reference voltage Vref1 can be obtained at the node formed by connecting resistors R2 and R3, and the over-temperature protection reference voltage Vref2 can be obtained at the node formed by connecting resistors R3 and R4. Therefore, given the reference voltage Vref and the resistors R2 to R4, the over-temperature protection reference voltages Vref1 and Vref2 can be determined. Of course, other forms of the basic reference voltage circuit can also be used, depending on whether they can provide the required over-temperature protection reference voltage. Examples will not be provided here.

[0137] In one embodiment of this utility model, the voltage selection circuit includes at least one voltage selection unit, wherein...

[0138] Each voltage selection unit includes two voltage selection branches, wherein each voltage selection branch includes one selection branch PMOS transistor and one selection branch NMOS transistor.

[0139] For any voltage selection unit, the gate terminals of the PMOS transistor in the selection branch and the NMOS transistor in the selection branch of one voltage selection branch are connected to a voltage selection control signal generated by the logic circuit, and the gate terminals of the PMOS transistor in the selection branch and the NMOS transistor in the selection branch of another voltage selection branch are connected to another voltage selection control signal generated by the logic circuit.

[0140] The basic circuit for reference voltage must provide at least two different over-temperature protection reference voltages;

[0141] Within each voltage selection unit, the source terminal of the PMOS transistor in one voltage selection branch is connected to the source terminal of the NMOS transistor in another voltage selection branch, and both are connected to an over-temperature protection reference voltage provided by the reference voltage basic circuit.

[0142] Within each voltage selection unit, the drain terminals of all selection branch PMOS transistors and all selection branch NMOS transistors are interconnected, forming a voltage selection output terminal. The selected over-temperature protection reference voltage is then applied to the corresponding comparison input terminal of the temperature protection comparison unit through the voltage selection output terminal.

[0143] Within each voltage selection unit, the substrates of all selection branch PMOS transistors are connected to the over-temperature protection power supply voltage, and the substrates of all selection branch NMOS transistors are grounded.

[0144] As explained above, the voltage selection circuit is used to select the over-temperature protection reference voltage, such as... Figure 10 In the embodiments described, either the over-temperature protection reference voltage Vref1 or the over-temperature protection reference voltage Vref2 can be selectively applied to the comparator input IN-. Figure 10 The figure also illustrates one embodiment of the voltage selection unit. In this embodiment, PMOS transistor PM7 and NMOS transistor NM10 form a voltage selection branch, where PM7 acts as the selection branch PMOS transistor and NM10 acts as the selection branch NMOS transistor. Similarly, PMOS transistor PM8 and NMOS transistor NM11 form another voltage selection branch, where PM8 acts as the selection branch PMOS transistor and NM11 acts as the selection branch NMOS transistor. Figure 10 In the circuit, the source terminal of NMOS transistor NM11 is connected to resistors R2 and R3, and the source terminal of NMOS transistor NM10 is connected to resistors R3 and R.

[0145] Figure 10 In the above, SA and SB are voltage selection control signals generated by the logic circuit. When the voltage selection control signal SA is high and the voltage selection control signal SB is low, the over-temperature protection reference voltage Vref2 can be loaded to the comparator input IN- through PMOS transistor PM8 and NMOS transistor NM10. Similarly, when the voltage selection control signal SA is low and the voltage selection control signal SB is high, the over-temperature protection reference voltage Vref1 can be loaded to the comparator input IN- through PMOS transistor PM7 and NMOS transistor NM11.

[0146] As explained above, based on different DC motors and the over-temperature protection requirements of the DC motors, the logic circuit can generate corresponding voltage selection control signals SA and SB, thereby selecting the corresponding over-temperature protection reference voltage. Of course, the voltage selection circuit can also adopt other forms, depending on whether it can achieve the selection of the over-temperature protection reference voltage; these will not be elaborated upon here.

[0147] Depend on Figure 10 It can be seen that a temperature-sensing voltage V can be generated through the PNP transistor R1. BE V BE It has a negative temperature coefficient, which decreases as temperature increases. Since the over-temperature protection reference voltage is generated by dividing the reference voltage Vref through resistors, the over-temperature protection reference voltage does not change with temperature. However, as temperature rises, the sensing voltage V... BE It continuously decreases, while when the temperature sensing voltage V BE When the voltage is lower than the over-temperature protection reference voltage, the output of the temperature protection comparator will change. The logic circuit will then execute over-temperature protection based on the change in the output of the temperature protection comparator. For details on the execution of over-temperature protection, please refer to the relevant descriptions above.

Claims

1. A monolithic integrated DC motor driver chip based on LDMOS devices, characterized in that, The DC motor driver chip includes at least one drive channel capable of controlling the DC motor drive, wherein, For any driving channel, there is an H-bridge topology circuit adapted to and connected to the DC motor to be driven and controlled, and a channel main circuit adapted to and connected to the H-bridge topology circuit. The H-bridge topology circuit includes two bridge arm units, and the H-bridge topology circuit is adapted to be connected to the DC motor to be driven and controlled through the bridge arm units. Each bridge arm unit includes an N-type LDMOS switch and a P-type LDMOS switch adapted and connected to the N-type LDMOS switch, wherein, N-type LDMOS switches and P-type LDMOS switches are fabricated on the same substrate. When driving and controlling a DC motor via an H-bridge topology circuit, the N-type LDMOS switches and P-type LDMOS switches within the same bridge arm unit are configured to be in a complementary conduction state.

2. The monolithically integrated DC motor driver chip based on LDMOS devices according to claim 1, characterized in that: Both the N-type LDMOS switch and the P-type LDMOS switch are fabricated on at least the P+ substrate, and the N-type LDMOS switch is isolated from the P-type LDMOS switch through the P+ substrate. For any bridge arm unit, the source terminal of the P-type LDMOS switch in the bridge arm unit is connected to the drive power supply voltage, the drain terminal of the N-type LDMOS switch, the drain terminal of the P-type LDMOS switch and the DC motor adapter are connected, and the source terminal of the N-type LDMOS switch is grounded. The gate terminals of both the N-type LDMOS and P-type LDMOS switches are adapted and connected to the main channel circuit.

3. The monolithic integrated DC motor driver chip based on LDMOS devices according to claim 2, characterized in that, The P-type LDMOS switch includes an N-type epitaxial layer fabricated on a P+ substrate; On the cross-section of the P-type LDMOS switch, a P-type drain region is formed on the N-type epitaxial layer, and a P-type switch source-drain region is formed on both sides of the P-type drain region. For any P-type switch, the source and drain regions include an N-type well region, a P+ source region, and an N-type deep doped region. The P+ source region is distributed within the N-type well region and the N-type deep doped region. The N-type well region is in contact with the N-type deep doped region, and the junction depth of the N-type deep doped region is greater than that of the N-type well region. The N-type well region is in contact with the P-type drain region, and the P+ source region and the N-type deeply doped region are isolated from the P-type drain region through the N-type well region; The P-type drain region makes ohmic contact with the drain metal of the P-type switch, the N-type well region and the P-type drain region make ohmic contact with the gate metal of the P-type switch, and the N-type deeply doped region and the P+ source region make ohmic contact with the source metal of the P-type switch.

4. The monolithically integrated DC motor driver chip based on LDMOS devices according to claim 3, characterized in that, The N-type LDMOS switch includes a P-type epitaxial layer fabricated on a P+ substrate; On the cross-section of the P-type LDMOS switch, an N-type drain region is formed on the P-type epitaxial layer, and an N-type switch source-drain region is formed on both sides of the N-type drain region. For any N-type switch, the source and drain regions include a P-type well region, an N+ source region, and a P-type deep doped region. The N+ source region is distributed within the P-type well region and the P-type deep doped region. The P-type well region is in contact with the P-type deep doped region, and the junction depth of the P-type deep doped region is greater than that of the P-type well region. The P-type well region is in contact with the N-type drain region, and the N+ source region and the deeply doped P-type region are isolated from the N-type drain region through the P-type well region; The N-type drain region makes ohmic contact with the drain metal of the P-type switch, the P-type well region and the N-type drain region make ohmic contact with the gate metal of the P-type switch, and the P-type deeply doped region and the N+ source region make ohmic contact with the source metal of the P-type switch.

5. The monolithic integrated DC motor driver chip based on LDMOS devices according to any one of claims 1 to 4, characterized in that: The channel main circuit includes at least a gate drive circuit unit, a logic circuit, and a level conversion circuit unit, wherein... The gate drive circuit unit includes two gate drive circuits. Each gate drive circuit is connected to the gate terminal of an N-type LDMOS switch and the gate terminal of a P-type LDMOS switch in a bridge arm unit, so as to drive the switching state of the connected N-type LDMOS switch and P-type LDMOS switch using the gate drive circuit. The gate drive circuits in the gate drive circuit unit are all connected to the logic circuit, and the logic circuit is also adapted to be connected to the level conversion circuit in the level conversion circuit unit.

6. The monolithically integrated DC motor driver chip based on LDMOS devices according to claim 5, characterized in that: The level conversion circuit unit includes at least two level conversion circuits, so as to receive a corresponding drive control sub-signal through one level conversion circuit, convert the drive control sub-signal into a valid drive control logic signal through the level conversion circuit, and load the drive control logic signal into the logic circuit. For any level conversion circuit, the input terminal of the level conversion circuit is also connected to a conversion protection circuit, wherein, The conversion protection circuit includes a first conversion protection diode, a second conversion protection diode, and a conversion protection resistor. The anode of the first conversion protection diode and the cathode of the second conversion protection diode are both connected to the input terminal of the level conversion circuit. The cathode of the first conversion protection diode is connected to the level conversion power supply, and the anode of the second conversion protection diode is grounded. The two ends of the switching protection resistor are connected in parallel with the second switching protection diode.

7. The monolithic integrated DC motor driver chip based on LDMOS devices according to claim 6, characterized in that: For any level-shifting circuit, including NMOS transistors NM2, NMOS transistors NM3, NMOS transistors NM4, and PMOS transistor PM1, where, The gate terminals of NMOS transistors NM2, NMOS transistor NMO3, and NMOS transistor NM4 are all connected to drive control sub-signals. The drain terminals of NMOS transistor NM2 and NMOS transistor NM3 are connected to one end of resistor R1, the gate terminal of PMOS transistor PM1, and the gate terminal of NMOS transistor NM6. The other end of resistor R1, the source terminal of PMOS transistor PM1, and the substrate of PMOS transistor PM1 are all connected to a level conversion power supply. The source terminal of NMOS transistor NM2 is connected to the drain terminal of NMOS transistor NM4, the source terminal of NMOS transistor NM3 is connected to the drain terminal of NMOS transistor NM5, the gate terminal of NMOS transistor NM5 is connected to the drain terminal of PMOS transistor PM1 and the drain terminal of NMOS transistor NM6, and the drain terminal of PMOS transistor PM1 and the drain terminal of NMOS transistor NM6 are connected to each other to form a level conversion output terminal. The substrates of NMOS transistor NM2, NMOS transistor NM4, the source terminal of NMOS transistor NM4, the substrates of NMOS transistor NM3, NMOS transistor NM5, the source terminal of NMOS transistor NM5, the substrate of NMOS transistor NM6, and the source terminal of NMOS transistor NM6 are all grounded.

8. The monolithically integrated DC motor driver chip based on LDMOS devices according to claim 5, characterized in that: The main circuit of the channel also includes an over-temperature protection circuit, which is connected to the logic circuit. The over-temperature protection circuit includes a temperature protection comparison unit, a temperature sensing circuit, and a reference voltage circuit connected together. The temperature sensing circuit and the reference voltage circuit are respectively connected to the corresponding comparison input terminals of the temperature protection comparison unit, and the output terminal of the temperature protection comparison unit is connected to the logic circuit.

9. The monolithic integrated DC motor driver chip based on LDMOS devices according to claim 8, characterized in that: The reference voltage circuit includes a basic reference voltage circuit and a voltage selection circuit adapted and connected to the basic reference voltage circuit, wherein... The output of the voltage selection circuit is connected to the temperature protection comparison unit. The voltage selection circuit is also connected to the logic circuit. The logic circuit selects the corresponding over-temperature protection reference voltage through the voltage selection circuit and applies the selected over-temperature protection reference voltage to the corresponding comparison input of the temperature protection comparison unit. The temperature protection comparison unit then compares the over-temperature protection reference voltage with the temperature sensing voltage generated by the temperature sensing circuit.

10. The monolithic integrated DC motor driver chip based on LDMOS devices according to claim 9, characterized in that: The voltage selection circuit includes at least one voltage selection unit, wherein... Each voltage selection unit includes two voltage selection branches, wherein each voltage selection branch includes one selection branch PMOS transistor and one selection branch NMOS transistor. For any voltage selection unit, the gate terminals of the PMOS transistor in the selection branch and the NMOS transistor in the selection branch of one voltage selection branch are connected to a voltage selection control signal generated by the logic circuit, and the gate terminals of the PMOS transistor in the selection branch and the NMOS transistor in the selection branch of another voltage selection branch are connected to another voltage selection control signal generated by the logic circuit. The basic circuit for reference voltage must provide at least two different over-temperature protection reference voltages; Within each voltage selection unit, the source terminal of the PMOS transistor in one voltage selection branch is connected to the source terminal of the NMOS transistor in another voltage selection branch, and both are connected to an over-temperature protection reference voltage provided by the reference voltage basic circuit. Within each voltage selection unit, the drain terminals of all selection branch PMOS transistors and all selection branch NMOS transistors are interconnected, forming a voltage selection output terminal. The selected over-temperature protection reference voltage is then applied to the corresponding comparison input terminal of the temperature protection comparison unit through the voltage selection output terminal. Within each voltage selection unit, the substrates of all selection branch PMOS transistors are connected to the over-temperature protection power supply voltage, and the substrates of all selection branch NMOS transistors are grounded.

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