An embedded power module

Abstract

The utility model provides a kind of embedded power module, it includes: the multilayer circuit layer of stacked arrangement, power chip and substrate;Between multilayer circuit layer, between circuit layer and power chip, between circuit layer and substrate are connected by filling copper blind hole;Copper foil layer is sintered on power chip, and the filling copper blind hole between circuit layer and power chip is connected on copper foil layer.The utility model realizes the leadless 3D packaging of power chip by above vertical blind hole design, and the size of ceramic substrate is reduced to realize the reduction of power module volume;Meanwhile, the mutual coupling of parasitic inductance is realized by the laminated placement of drive circuit, so that the parasitic inductance of drive circuit is further reduced;By sintering copper foil layer on power chip, copper metallization treatment of chip is not needed, time is saved, risk and cost are lower and process compatibility is better.The module is also integrated with gate resistance inside, which can effectively control the switching speed of power chip and reduce the probability of false turn-on or false turn-off.

Description

Technical Field

[0001] This utility model relates to the field of power module integrated design technology, and in particular to an embedded power module. Background Technology

[0002] At the same power level, compared with traditional Si-based devices, SiC devices have a switching frequency that is at least 5-10 times higher, a device size that is only 1 / 6 to 1 / 4 of the former, and a current density per unit area that is 4-6 times higher. However, most of the modular packaging for SiC devices today follows the technical route of traditional Si-based power module packaging, which prevents SiC devices from fully realizing their superior performance.

[0003] Traditional silicon-based power modules mostly employ a ceramic substrate and wire bonding to achieve two-dimensional planar packaging of the chip. The upper surface of the ceramic substrate is divided into several areas by insulating trenches, reserving connection space and circuitry for components such as the chip, bonding wires, gate resistors, and terminals. The middle ceramic layer provides electrical insulation, while the lower surface handles heat dissipation. Wire bonding connects the top of the chip to the ceramic substrate to interconnect the chip's top electrodes. This packaging solution, due to its low cost and mature technology, has been widely adopted in the market.

[0004] Traditional power modules have the following technical problems:

[0005] 1. Large Parasitic Parameters: In traditional power modules, electrical interconnections at the top of the chip are mainly achieved through bonding wires. Longer bonding wires introduce larger parasitic parameters. Furthermore, the relatively limited two-dimensional planar packaging of traditional power modules results in a narrow and congested current path on the substrate. Combined with the mutual inductance between adjacent circuits, the parasitic parameters within the module will further increase. Excessive parasitic parameters will limit the high-frequency application of SiC power modules.

[0006] Specifically, in the drive circuit, introducing excessive parasitic inductance will cause significant gate voltage oscillations, leading to crosstalk and false turn-on in the bridge arms, exacerbating electromagnetic interference, increasing the risk of gate overvoltage breakdown, and causing device reliability degradation. In the power circuit, during the switching process of SiC power modules in high-frequency applications, the parasitic inductance of the power circuit will form a resonant circuit with the parasitic capacitance of the SiC device, generating high-frequency oscillations. Furthermore, the high switching speed of SiC power modules results in a high di / dt, which will induce voltage overshoot in the parasitic inductance of the power circuit, leading to additional losses. Simultaneously, excessive voltage overshoot may exceed the device's maximum withstand voltage rating, posing a failure risk.

[0007] 2. Complex circuit design and large module size: Traditional power modules often use two-dimensional planar packaging, which requires multiple independent current paths to be allocated on the ceramic substrate and space to be reserved for components such as chips, bonding wires, gate resistors and terminals. Multiple factors combined result in complex circuit design of ceramic substrates and difficulty in reducing size, which in turn makes it difficult to improve the power density of the module, fail to give full play to the small size advantage of SiC devices, and fail to meet the current power electronic system's demand for miniaturization and high power density.

[0008] 3. Poor heat dissipation performance: As the power levels of power electronic systems gradually increase, the heat generation of power modules will become increasingly severe. Traditional single-sided cooling solutions are no longer sufficient to efficiently dissipate heat from within the module, and heat dissipation design is becoming a key obstacle to the development of power modules towards higher power density. Although SiC chips can operate under relatively harsh temperature conditions, weak points within the module, such as bonding wires and interconnect layers, will fail more quickly, severely impacting the module's lifespan.

[0009] 4. Weak current-carrying capacity: Most existing embedded power modules have a single-layer circuit on top. A large current flowing through a thin copper layer will cause its temperature to rise rapidly, introducing a heat source close to the power chip inside the module and affecting the normal operation of the power module. At the same time, the weak current-carrying capacity also limits the improvement of the module's power level, restricting its promotion in high-performance application scenarios.

[0010] 5. Copper metallization is required on the top of the chip: To connect the blind via to the power chip, a layer of copper metal needs to be pre-formed on the pads on the top surface of the power chip. However, traditional electroless plating and magnetron sputtering copper metallization processes have the risk of failure. In addition, copper is prone to oxidation and requires special handling during storage or transportation. This solution has the disadvantages of complex process, high cost and high risk.

[0011] 6. Poor drilling accuracy: Most existing embedded power modules use fixtures for positioning. The tolerance of the fixture, combined with the error introduced by the previous process, and the small pad size of SiC power chips, cause the laser drilling to deviate from the predetermined position, which can easily damage the chip. Blind holes with excessive deviation will cause short circuits after electroplating, leading to module failure.

[0012] 7. No Gate Resistor: To achieve a smaller size, most existing embedded power modules do not incorporate a gate resistor. Without a gate resistor, the switching speed of the power chip will be significantly increased, which can easily lead to gate oscillation in high-frequency applications, causing false turn-on or false turn-off. Excessively high switching speeds will also cause extremely high voltage / current overshoot and increase the reverse recovery stress of the diode, increasing losses and the risk of failure. Utility Model Content

[0013] In order to overcome the shortcomings of the prior art, this utility model provides an embedded power module.

[0014] To achieve the above objectives, this utility model provides an embedded power module, which includes: a multilayer circuit layer, a power chip, and a substrate stacked together; the multilayer circuit layers are connected to each other, between the circuit layer and the power chip, and between the circuit layer and the substrate through copper-filled blind vias; a copper foil layer is sintered on the power chip, and the copper-filled blind vias between the circuit layer and the power chip are connected to the copper foil layer.

[0015] Preferably, the circuit layer includes: a first circuit layer and a second circuit layer; the copper foil layer on the power chip includes: a gate copper foil layer, a secondary source copper foil layer, and a power source copper foil layer;

[0016] Preferably, the gate copper foil layer, secondary source copper foil layer, and power source copper foil layer on the first circuit layer and the power chip are connected by copper-filled blind vias.

[0017] Preferably, the copper-filled blind vias between the first circuit layer and the second circuit layer and the copper-filled blind vias between the first circuit layer and the power source copper foil layer and the secondary source copper foil layer are aligned.

[0018] Preferably, the top of the second circuit layer has an exposed copper layer.

[0019] Preferably, the substrate includes: an upper copper layer, a ceramic layer, and a lower copper layer disposed sequentially; the first circuit layer and the power chip are connected to the upper copper layer.

[0020] Preferably, the copper layer and the first circuit layer on the substrate are provided with multiple positioning marks for determining the drilling position.

[0021] Preferably, a gate resistor is provided on the copper layer on the substrate, and the first circuit layer is connected to the gate resistor through a copper-filled blind via.

[0022] Preferably, it further includes: multiple connection layers, the connection layers including:

[0023] Gate resistor connection layer, used to connect the gate resistor to the copper layer on the substrate;

[0024] The secondary source connection layer is used to connect the power chip and the secondary source copper foil layer;

[0025] The power source interconnect layer is used to connect the power chip and the power source copper foil layer;

[0026] Drain interconnect layer, used to connect the power chip to the copper layer on the substrate;

[0027] The gate interconnect layer is used to connect the power chip to the gate copper foil layer.

[0028] The embedded power module provided by this utility model has the following advantages compared with the prior art: the electrodes on the chip surface are vertically led out through blind holes and distributed in multi-layer circuits to achieve leadless 3D packaging, specifically manifested in the following aspects:

[0029] 1. Low Parasitic Parameters: Multilayer embedded power modules achieve leadless packaging, and the elimination of bond wires significantly reduces the parasitic inductance of the power and drive circuits. According to the mutual inductance cancellation effect, the reverse magnetic flux generated by two current loops with opposite current paths will cancel each other out, thereby reducing the overall equivalent inductance. The closer the two conductors are, the more pronounced the cancellation effect of parasitic inductance. Multilayer circuits allow for stacked placement of drive circuits. Placing the source and gate circuits on adjacent layers and aligning them allows the mutual inductance cancellation effect to be fully utilized, further reducing the parasitic inductance of the drive circuit.

[0030] 2. Simplify circuit design and reduce module size: Multilayer embedded power modules can decompose the circuit on the ceramic substrate into multiple layers on top, effectively reducing the circuit design complexity of the ceramic substrate and reducing its size, thereby reducing the size of the power module and increasing power density.

[0031] 3. Excellent heat dissipation performance: The exposed copper foil layer on the top of the multi-layer embedded power module can introduce a brand-new heat dissipation path for the module, realizing double-sided heat dissipation from the top and bottom of the module, which helps to quickly remove heat from the inside of the module.

[0032] 4. Enhanced Current Carrying Capacity: The multi-layered circuitry introduced at the top of the embedded power module can distribute the current, effectively reducing heat generation in the circuitry. Simultaneously, this design also helps the embedded power module significantly increase its current rating, enabling it to adapt to higher power level applications.

[0033] 5. Simplified Process: Copper foil sintering replaces chemical plating and magnetron sputtering. Specifically, a layer of copper foil is sintered onto the upper surface of the power chip, achieving a reliable connection between the power chip and the copper-plated blind vias. This solution only requires one round of copper foil sintering after the chip sintering is complete, saving time, reducing risks and costs, and offering better process compatibility.

[0034] 6. High drilling accuracy: Image recognition is used to replace fixtures for positioning. Specifically, several positioning marks are pre-printed at fixed positions on the copper layer of the ceramic substrate. The laser drilling equipment only needs to drill to the copper layer of the substrate within a large specified range to read the positioning marks. Then, the drilling position is automatically calibrated according to the position of the marks. This solution improves drilling accuracy, does not require high-precision fixtures, and helps to reduce costs and improve yield.

[0035] 7. Integrated Gate Resistor: The multilayer embedded power module integrates a gate resistor internally, which can effectively control the switching speed of the power chip, reduce the probability of false turn-on or false turn-off, reduce voltage / current overshoot and reverse recovery stress of the diode, reduce the number of external components, reduce design complexity, and improve system reliability. Attached Figure Description

[0036] Figure 1 A side sectional view of an embedded power module provided by this utility model;

[0037] Figure 2 A front sectional view of an embedded power module provided by this utility model;

[0038] Figure 3 A SiC power chip pad structure diagram for an embedded power module provided by this utility model;

[0039] Figure 4 This utility model provides a SiC power chip drain pad for an embedded power module;

[0040] Figure 5 The flowchart of the manufacturing process of an embedded power module provided by this utility model, from chip sintering to module secondary molding, is shown.

[0041] Figure 6 This utility model provides a flowchart of the manufacturing process of an embedded power module, from secondary molding to via filling electroplating and circuit etching.

[0042] Reference numerals: 1-Encapsulation material; 21- Upper copper layer on substrate; 22- Substrate ceramic layer; 23- Lower copper layer on substrate; 31- Second circuit layer; 32- First circuit layer; 4- Power chip; 41- Power source copper foil layer; 42- Sub-source copper foil layer; 43- Gate copper foil layer; 41-1- Power source pad; 42-1- Sub-source pad; 43-1- Gate pad; 44- Drain pad; 5- Copper-filled blind via; 6- Positioning mark; 7-1- Sub-source connection layer; 7-2- Power source connection layer; 7-3- Drain connection layer; 7-4- Gate resistor connection layer; 7-5- Gate connection layer; 8- Gate resistor. Detailed Implementation

[0043] The following specific examples illustrate the implementation of this utility model. Those skilled in the art can easily understand other advantages and effects of this utility model from the content disclosed in this specification. This utility model can also be implemented or applied through other different specific embodiments, and various details in this specification can also be modified or changed based on different viewpoints and applications without departing from the spirit of this utility model. It should be noted that, unless otherwise specified, the following embodiments and features described therein can be combined with each other.

[0044] It should be noted that the illustrations provided in the following embodiments are only schematic representations of the basic concept of the present invention. Therefore, the drawings only show the components related to the present invention and are not drawn according to the number, shape and size of the components in actual implementation. In actual implementation, the form, quantity and proportion of each component can be arbitrarily changed, and the layout of the components may also be more complex.

[0045] In this embodiment of the invention, all directional indicators (such as up, down, left, right, front, back, horizontal, side, front, vertical, etc.) are only used to explain the relative positional relationship and movement of the components in a specific posture. If the specific posture changes, the directional indicator will also change accordingly.

[0046] Due to installation errors and other reasons, the parallel relationship referred to in the embodiments of this utility model may actually be an approximate parallel relationship, and the perpendicular relationship may actually be an approximate perpendicular relationship.

[0047] like Figure 1 , 2 As shown, this utility model provides an embedded power module, which includes: a multi-layer circuit layer stacked together, a power chip 4 and a substrate; the multi-layer circuit layers are connected to each other, between the circuit layers and the power chip 4, and between the circuit layers and the substrate through copper-filled blind vias 5; a copper foil layer is sintered on the power chip 4, and the copper-filled blind vias 5 are connected to the copper foil layer.

[0048] Specifically, this invention achieves three-dimensional packaging of the power chip through a vertical blind via design, realizing leadless packaging, reducing circuit design complexity, and shrinking the size of the ceramic substrate, thereby reducing the size of the power module. The elimination of bonding wires significantly reduces the parasitic inductance of the power and drive circuits. Simultaneously, the multi-layer circuit design enables the stacked placement of the drive circuits, thereby canceling out the mutual coupling of parasitic inductances and further reducing the parasitic inductance of the drive circuit. Compared to single-layer embedded packaging solutions, this embedded power module has lower parasitic parameters, stronger current carrying capacity, simpler circuit design, smaller module size, and higher power density. Furthermore, in this invention, copper metallization of the top of the power chip is achieved by sintering a copper foil layer on the power chip, meeting the substrate requirements for copper plating and producing high-quality copper-plated blind vias. This eliminates the need for copper metallization of the chip, saving time, reducing risk and cost, and providing good process compatibility.

[0049] In this embodiment, the circuit layer includes a second circuit layer 31 and a first circuit layer 32; the copper foil layer on the power chip 4 includes a gate copper foil layer 43, a secondary source copper foil layer 42, and a power source copper foil layer 41; the first circuit layer 32 and the gate copper foil layer 43, secondary source copper foil layer 42, and power source copper foil layer 41 on the power chip 4 are connected by copper-filled blind vias 5. The copper-filled blind vias between the first circuit layer 32 and the second circuit layer 31 and between the first circuit layer 32 and the power source copper foil layer 41 and the secondary source copper foil layer 42 are aligned.

[0050] Specifically, based on the mutual inductance cancellation effect, the magnetic fluxes generated by two current loops with opposite current paths in opposite directions will cancel each other out, thereby reducing the overall equivalent inductance. The closer the two conductors are, the more significant the cancellation effect of parasitic inductance. Multilayer drive circuits can achieve stacked placement of drive loops, placing the source loop and gate loop in adjacent layers and aligning them. The magnetic fields induced by the two circuits with opposite current flows can cancel each other out, further reducing the overall parasitic inductance of the drive loop. In this embodiment, each circuit layer includes a power loop and a drive loop. The power loops in the second circuit layer 31 and the first circuit layer 32 can share the current, effectively reducing the heat generation of the circuit and helping the embedded power module significantly increase its current rating, making it suitable for higher power level applications. The drive circuit, originally located on the substrate in a traditional power module, is moved to the second circuit layer 31 and the first circuit layer 32 on top of the power chip 4, further reducing the module size and space occupied.

[0051] In traditional embedded packaging, a layer of copper metal is often pre-formed on the pads of the power chip 4 as a substrate. Otherwise, copper deposition is difficult during the blind via electroplating process, or poor blind via connection quality may occur. Traditional copper metallization processes include electroplating, chemical plating, and magnetron sputtering. However, the power chip 4 is at risk of failure in these processes. In addition, copper is prone to oxidation and requires special handling during storage or transportation. This approach has the disadvantages of complex processes, high cost, and high risk. This invention replaces chemical plating and magnetron sputtering with copper foil sintering. Specifically, a layer of copper foil is sintered on the upper surface of the power chip 4, which also achieves copper metallization on the top of the power chip 4, meeting the substrate requirements for copper electroplating and producing high-quality copper-plated blind vias. The copper foil sintering method only requires one round of copper foil sintering after the chip sintering is completed, eliminating the need for chip surface treatment, saving time, reducing risk and cost, and providing better process compatibility.

[0052] In this embodiment, the second circuit layer 31 has an exposed copper layer on top.

[0053] Specifically, the second circuit layer 31 has an exposed copper layer on top during manufacturing. This, together with the copper-filled blind vias 5 between each circuit layer and the copper foil layer on the power chip 4, forms a completely new heat dissipation path, further improving the efficiency of the power chip 4. In addition, the substrate connected to the power chip 4 also provides the first heat dissipation path for the power chip 4. Based on this, the embedded power module can achieve double-sided heat dissipation from the top and bottom, which helps to quickly remove heat from the module.

[0054] In this embodiment, the substrate includes: an upper copper layer 21, a ceramic layer 22, and a lower copper layer 23 disposed sequentially; the first circuit layer 32 and the power chip 4 are connected to the upper copper layer 21.

[0055] Specifically, the first circuit layer 32 is connected to the copper layer 21 on the substrate, which enables the heat of the first circuit layer 32 to be quickly dissipated to the bottom of the module through the copper layer 21 on the substrate, thereby reducing the heat dissipation burden of the first circuit layer 32, and at the same time reducing the heat generation of the first circuit layer 32 and the heat dissipation burden of the second circuit layer 31 connected thereto.

[0056] In this embodiment, the copper layer 21 and the first circuit layer 32 on the substrate are provided with a plurality of positioning marks 6 for determining the drilling position.

[0057] Specifically, in traditional embedded packaging, drilling positioning is often achieved using high-precision fixtures or X-ray scanning-assisted positioning, both of which are costly and complex. This invention uses image recognition to replace high-precision fixtures for positioning. Specifically, several positioning marks 6 are pre-printed at fixed positions on the copper layer 21 of the ceramic substrate, and the positional relationship between the positioning marks 6 and various components on the substrate is recorded. In the laser drilling process, the semi-finished embedded module is placed on a low-precision fixture, and the equipment drills holes over a large area, exposing the positioning marks 6. Subsequently, the equipment identifies multiple positioning marks 6 through image recognition and automatically calibrates the drilling position. This solution achieves high-precision positioning even with a low-precision fixture. This solution improves drilling accuracy, helps reduce costs, and increases yield. The positioning marks 6 can be achieved by laser drilling, laser marking, or by sintering a small copper sheet on the substrate, or by leaving specific lines during etching. Furthermore, the purpose of placing the positioning mark 6 used during the second drilling on the first circuit layer 32 instead of the copper layer 21 on the substrate is that laser drilling on epoxy resin is easier to achieve than laser drilling on metallic copper, and the deeper the hole, the more difficult it is to achieve laser drilling.

[0058] In this embodiment, a gate resistor 8 is provided on the copper layer 21 on the substrate, and the first circuit layer 32 is connected to the gate resistor 8 through a copper-filled blind via 5.

[0059] Specifically, the embedded power module of the multi-layer drive circuit integrates a gate resistor 8 internally. The gate resistor 8 and the input capacitor (Ciss) of the power chip 4 form an RC charging and discharging circuit. A larger resistance value results in a longer charging time constant (τ = Rg × Ciss), a slower gate voltage change rate, and a longer switching time. The switching speed of the power chip 4 can be controlled by changing the resistance value. In high-frequency applications, artificially reducing the switching speed of the power chip 4 can effectively reduce the probability of false turn-on or false turn-off, and reduce voltage / current overshoot and reverse recovery stress on the diode. Simultaneously, when multiple power chips 4 are connected in parallel, the introduction of the gate resistor 8 can compensate for the parameter dispersion of the chips, ensuring synchronized switching actions of each chip and reducing current imbalance during switching. Furthermore, internal integration of the gate resistor 8 also helps reduce the number of external components, lower design complexity, and improve system reliability.

[0060] In this embodiment, the embedded power module further includes: multiple connection layers; through the multiple connection layers, the embedded power module can ensure the reliability of the connections between the various structures. The connection layers include:

[0061] Gate resistor connection layer 7-4 is used to connect the gate resistor 8 to the copper layer 21 on the substrate; secondary source connection layer 7-1 is used to connect the power chip 4 to the secondary source copper foil layer 42; power source connection layer 7-2 is used to connect the power chip 4 to the power source copper foil layer 41; drain connection layer 7-3 is used to connect the power chip 4 to the copper layer 21 on the substrate; gate connection layer 7-5 is used to connect the power chip 4 to the gate copper foil layer 43. The connection layer material is not limited to sintered silver; alloy solder, sintered copper paste, copper-silver mixed sintering paste, etc., can also be used.

[0062] like Figure 3 , 4 As shown, the power chip 4 is also provided with a secondary source pad 42-1, a power source pad 41-1, a gate pad 43-1 and a drain pad 44 for soldering the copper foil layers of the corresponding electrodes.

[0063] Based on the above-described embedded power module structure, its manufacturing process is as follows: Figure 5 , 6 As shown, it specifically includes:

[0064] 1. Chip and gate resistor sintering: The power chip 4 and the gate resistor 8 are sintered sequentially onto the copper layer 21 on the substrate. The drain connection layer 7-3 will realize a reliable connection between the drain pad 44 and the copper layer 21 on the substrate, and the gate resistor connection layer 7-4 will realize a reliable connection between the gate resistor 8 and the copper layer 21 on the substrate.

[0065] 2. Copper foil sintering: The copper foil layer is sintered onto the upper surface of the power chip 4. The gate copper foil layer 43 is reliably connected to the gate pad 43-1 through the gate connection layer 7-5; the secondary source copper foil layer 42 is reliably connected to the secondary source pad 42-1 through the secondary source connection layer 7-1; and the power source copper foil layer 41 is reliably connected to the power source pad 41-1 through the power source connection layer 7-2.

[0066] 3. First-stage molding: The semi-finished products prepared in steps 1 and 2 are embedded in molding material 1 using a molding process. Molding material 1 will fill the gaps and edge spaces of the copper layer 21 on the substrate, and the portion of molding material 1 that exceeds the top copper foil layer of the power chip 4 will serve as an insulating layer.

[0067] 4. Laser Drilling: Blind holes are drilled on the top of the molding compound 1 using laser drilling. First, holes are drilled in designated areas of the substrate to expose positioning marks 6. Secondary calibration is performed based on the position information determined by positioning marks 6, followed by formal drilling. The bottom of the blind holes in different locations will be drilled to different depths, exposing the copper foil layer on top of the power chip 4, the gate resistor 8, and the copper layer 21 on the substrate.

[0068] 5. Electroplating and Etching: Blind vias are filled by electroplating, and a copper foil layer is formed on the surface of the molding compound. After etching, the copper foil layer will form the second circuit layer 31. The copper-filled blind vias 5 will realize the electrical connection between the second circuit layer 31, the copper foil layer on top of the power chip 4, and the copper layer 21 on the substrate.

[0069] 6. Pre-defined positioning mark 6: Pre-defined positioning mark 6 is made on the surface of the second circuit layer 31 by laser drilling or laser marking to improve accuracy during subsequent secondary drilling.

[0070] 7. Secondary molding: The product manufactured in the previous process is re-embedded in molding material 1 using molding. Molding material 1 will fill the gaps and edge spaces of the second circuit layer 31, and the portion of molding material 1 above the second circuit layer 31 will serve as an insulating layer.

[0071] 8. Laser Drilling: A blind hole is drilled on the top of the encapsulation material 1 using laser drilling. First, a hole is drilled in a designated area of ​​the second circuit layer 31 to expose the positioning mark 6. Secondary calibration is performed based on the position information determined by the positioning mark 6, followed by formal drilling. The bottom of the blind hole will be drilled to the surface of the second circuit layer 31.

[0072] 9. Electroplating and Etching: Blind vias are filled by electroplating, and a copper foil layer is formed on the surface of the molding compound. After etching, the copper foil layer forms the first circuit layer 32. The copper-filled blind vias 5 will achieve the electrical connection between the second circuit layer 31 and the first circuit layer 32.

[0073] Based on this, by repeating the pre-defined positioning mark, plastic sealing, laser drilling, hole filling electroplating and circuit etching operations, a multi-layer circuit at the top can be achieved.

[0074] Obviously, the described embodiments are only some, not all, of the embodiments of this utility model. All other embodiments obtained by those skilled in the art based on the embodiments of this utility model without inventive effort should fall within the protection scope of this utility model.

Claims

1. An embedded power module, characterized in that, include: The top layer consists of multiple circuit layers, a power chip, and a substrate stacked together. The circuit layers are connected to each other, to the power chip, and to the substrate via copper-filled blind vias. A copper foil layer is sintered on the power chip, and the copper-filled blind vias between the circuit layers and the power chip are connected to the copper foil layer.

2. The embedded power module according to claim 1, characterized in that, The circuit layer includes: a first circuit layer and a second circuit layer; the copper foil layer on the power chip includes: a gate copper foil layer, a secondary source copper foil layer, and a power source copper foil layer.

3. The embedded power module according to claim 2, characterized in that, The first circuit layer and the gate copper foil layer, secondary source copper foil layer and power source copper foil layer on the power chip are connected by copper-filled blind vias.

4. The embedded power module according to claim 2, characterized in that, The copper-filled blind vias between the first circuit layer and the second circuit layer, and the copper-filled blind vias between the first circuit layer and the power source copper foil layer and the secondary source copper foil layer are aligned.

5. The embedded power module according to claim 4, characterized in that, The second circuit layer has an exposed copper layer on top.

6. The embedded power module according to claim 1, characterized in that, The substrate includes: an upper copper layer, a ceramic layer, and a lower copper layer disposed sequentially; the first circuit layer and the power chip are connected to the upper copper layer.

7. The embedded power module according to claim 6, characterized in that, The copper layer and the first circuit layer on the substrate are provided with multiple positioning marks for determining the drilling position.

8. The embedded power module according to claim 7, characterized in that, A gate resistor is provided on the copper layer of the substrate, and the first circuit layer is connected to the gate resistor through a copper-filled blind via.

9. The embedded power module according to claim 1, characterized in that, Also includes: Multiple connection layers, the connection layers including: Gate resistor connection layer, used to connect the gate resistor to the copper layer on the substrate; The secondary source connection layer is used to connect the power chip and the secondary source copper foil layer; The power source interconnect layer is used to connect the power chip and the power source copper foil layer; Drain interconnect layer, used to connect the power chip to the copper layer on the substrate; The gate interconnect layer is used to connect the power chip to the gate copper foil layer.

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