A pad structure, chip and integrated circuit
By adding a second metal layer as a thickened conductive layer to the pad structure, the problems of pad deformation and cracking are solved, thereby improving the reliability and stability of the pad, reducing costs and complexity, and making it suitable for high-density integrated circuit manufacturing.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Utility models(China)
- Current Assignee / Owner
- XIAMEN KIWI MICROELECTRONICS TECH CO LTD
- Filing Date
- 2025-06-16
- Publication Date
- 2026-07-07
Smart Images
Figure CN224473698U_ABST
Abstract
Description
Technical Field
[0001] This utility model relates to the field of integrated circuit technology, specifically but not limited to a pad structure, a chip, and an integrated circuit. Background Technology
[0002] In integrated circuit manufacturing, the wafer surface is typically covered with a silicon dioxide passivation layer to prevent external contamination from damaging the wafer and its circuitry. However, chip testing and packaging require exposed metal pads for electrical connections, necessitating windows in the passivation layer to expose these pads. During testing and packaging, the pads and the underlying structure must withstand mechanical stresses from probe contact and wire bonding. Current technologies primarily rely on the top metal (usually aluminum) and dielectric layer beneath the passivation layer to distribute this stress.
[0003] Common pad window structures such as Figure 1 , Figure 2 As shown, it has the following limitations: 1) Although aluminum as the top layer metal has excellent conductivity and ductility, excessive ductility can easily cause the pads to deform under stress, and even cause cracks. To improve reliability, it is usually necessary to increase the thickness of the top layer metal (e.g., ...). Figure 2 (As shown), but this would reduce the wiring density of the top metal layer 1, increase the chip area, and simultaneously increase the design difficulty and cost of the circuit under pad (CUP). 2) In the existing structure, external forces would directly act on the passivation layer window, easily causing stress concentration at the interface between the passivation layer and the top metal layer, leading to crack formation and propagation along the dielectric layer, ultimately affecting circuit functionality. 3) Simply increasing the thickness of the top metal layer would significantly increase material costs and process complexity, making it difficult to meet the requirements of high-density integration and low-cost manufacturing.
[0004] In view of this, a new structure is needed to solve at least some of the above problems. Utility Model Content
[0005] Addressing at least one or more problems in the background art, this utility model proposes a pad structure, chip, and integrated circuit. By increasing the thickness of the conductive layer of the pad, the risk of the pad cracking in subsequent processes is reduced, the reliability of the pad is improved, and the mechanical stability and crack propagation resistance of the chip are enhanced in testing, packaging, and long-term operating environments.
[0006] According to one aspect of the present invention, a pad structure includes:
[0007] The first metal layer serves as the basic conductive layer of the pad structure.
[0008] A passivation layer is applied over the first metal layer and has a window that exposes a portion of the first metal layer.
[0009] A second metal layer covers the first metal layer within the window, serving as a thickened conductive layer for the pad structure.
[0010] Optionally, the second metal layer is deposited on the first metal layer by a physical vapor deposition method.
[0011] Optionally, the thickness of the second metal layer is greater than or equal to the thickness of the passivation layer.
[0012] Optionally, the material of the first metal layer and / or the second metal layer is at least one of aluminum, copper, and aluminum alloy.
[0013] Optionally, the passivation layer is made of at least one of silicon dioxide, silicon nitride, and polyimide.
[0014] According to another aspect of the present invention, a chip includes any of the aforementioned pad structures.
[0015] Optionally, the thickness of the first metal layer of the pad structure is equal to the thickness of the top metal layer in other areas of the chip.
[0016] Optionally, integrated circuit devices and traces are arranged below the pad structure.
[0017] According to another aspect of the present invention, an integrated circuit includes a plurality of chips, wherein the chips include any of the pad structures described above.
[0018] The pad structure, chip, and integrated circuit proposed in this invention reduce the risk of cracking in subsequent processes and improve the reliability of the pads by increasing the thickness of the conductive layer. Furthermore, this pad structure is compatible with existing manufacturing processes, reducing process complexity and economic costs. The use of this pad structure in chips and integrated circuits improves their mechanical stability and crack propagation resistance during testing, packaging, and long-term operation. Additionally, the chip can use a thinner top metal layer to allow for the placement of devices and traces beneath the pads, thereby avoiding increased chip area and reducing costs. Attached Figure Description
[0019] The accompanying drawings are provided to further illustrate the present invention and, together with the description, serve to explain the embodiments of the present invention, but do not constitute a limitation thereof. In the drawings:
[0020] Figure 1 A schematic diagram of a pad structure in the prior art is shown;
[0021] Figure 2This diagram illustrates another pad structure in the prior art;
[0022] Figure 3 A schematic diagram of the pad structure according to an embodiment of the present invention is shown;
[0023] Figure 4 A flowchart illustrating a manufacturing method for the pad structure of this utility model is shown;
[0024] Figure 5 A flowchart illustrating another manufacturing method for the pad structure of this utility model is shown;
[0025] Figure 6 A schematic diagram of the passivation layer surface according to an embodiment of the present invention is shown;
[0026] Figure 7 A schematic diagram of the passivation layer surface according to another embodiment of the present invention is shown. Detailed Implementation
[0027] To further understand this utility model, preferred embodiments of this utility model are described below in conjunction with examples. However, it should be understood that these descriptions are only for further illustrating the features and advantages of this utility model, and not for limiting the scope of the claims of this utility model.
[0028] The description in this section pertains to only a few typical embodiments, and this utility model is not limited to the scope of the embodiments described. Combinations of different embodiments, substitution of some technical features in different embodiments, and substitution of the same or similar prior art with some technical features in the embodiments are also within the scope of the description and protection of this utility model.
[0029] This utility model proposes a pad structure, such as Figure 3 As shown, the pad structure includes a first metal layer 1, a passivation layer 2, and a second metal layer 3, wherein:
[0030] The first metal layer 1 serves as the basic conductive layer of the pad structure;
[0031] The passivation layer 2 covers the first metal layer 1 and has a window that exposes a portion of the first metal layer 1 to protect the area outside the pads;
[0032] The second metal layer 3 covers the first metal layer 1 inside the window, serving as a thickened conductive layer for the pad structure. At this time, the thickness of the pad is the sum of the thickness of the first metal layer 1 and the thickness of the second metal layer 3.
[0033] In one embodiment, the second metal layer 3 is deposited on the first metal layer 1 by physical vapor deposition. The second metal layer 3 can be deposited on the first metal layer 1 by methods such as magnetron sputtering, evaporation, or thermal deposition.
[0034] In one embodiment, the thickness of the second metal layer 3 is greater than or equal to the thickness of the passivation layer 2.
[0035] In one specific implementation, such as Figure 5 As shown, when the pad structure is prepared using photolithography and etching, the thickness of the second metal layer 3 in the obtained pad structure is greater than the thickness of the passivation layer 2.
[0036] In another specific implementation, such as Figure 4 As shown, when the pad structure is prepared using a physical grinding process, the thickness of the second metal layer 3 in the obtained pad structure is equal to the thickness of the passivation layer 2.
[0037] When the thickness of the first metal layer 1 is relatively thick, the thickness of the passivation layer 2 on the surface of the first metal layer 1 will be relatively thin, and the thickness of the second metal layer 3 will be less than or equal to the thickness of the first metal layer 1. Conversely, when the thickness of the first metal layer 1 is relatively thin, the thickness of the passivation layer 2 on the surface of the first metal layer 1 will be relatively thick, and the thickness of the second metal layer 3 will be greater than or equal to the thickness of the first metal layer 1.
[0038] In one embodiment, the first metal layer 1 and / or the second metal layer 3 are both made of aluminum. Aluminum has advantages such as low cost, high conductivity, and good corrosion resistance, and is commonly used as the main material for the first metal layer 1 and the second metal layer 3. In addition, depending on different pad structure requirements, chip requirements, and other specific needs, copper, aluminum alloys, etc., can also be used as the main material for the metal layers.
[0039] In one embodiment, the passivation layer 2 is made of silicon dioxide. Silicon dioxide, with its high resistivity, high stability, and thermal expansion coefficient close to that of silicon, is commonly used as the main material for passivation layer 2. Furthermore, higher-specification wafers may also use silicon nitride as the main material for passivation layer 2. For other requirements of different chips and pad structures, such as high-temperature resistance, compound materials such as polyimide may also be used as the main material for passivation layer 2.
[0040] Compared to existing pad structures, the above-mentioned pad structure increases the thickness of the pads without increasing the thickness of the top layer metal. This reduces the probability of cracks appearing on the pads and the underlying dielectric due to wire bonding pressure during the packaging process. It also reduces the possibility of malfunctions in the chip's internal functions caused by packaging defects.
[0041] The manufacturing method of the above-mentioned pad structure may include the following steps:
[0042] S1. Deposit a layer of metallic material as the first metallic layer 1.
[0043] S2. Deposit an insulating material on the first metal layer 1 as a passivation layer 2; coat the passivation layer 2 with photoresist, and use a mask to selectively remove the photoresist and the passivation layer 2 under it in the window area to obtain a passivation layer window and expose the first metal layer 1.
[0044] S3. Add a layer of metal material to the first metal layer 1 inside the window as the second metal layer 3.
[0045] Preferably, the method of depositing metal materials in S1 and S3 can be magnetron sputtering, vapor deposition, thermal deposition, etc.
[0046] In one embodiment, adding a layer of metal material to the first metal layer 1 within the window in S3 can be achieved using a physical grinding process, such as... Figure 4 As shown, the details are as follows:
[0047] S3-1. Deposit metallic material on the passivation layer 2 and the first metal layer 1 within the window.
[0048] S3-2. Perform physical grinding / chemical mechanical polishing on the metal material above the plane where the upper surface of the passivation layer 2 is located, grinding away the metal material above the plane where the upper surface of the passivation layer 2 is located until the passivation layer 2 is exposed. At this time, the metal layer remaining on the first metal layer 1 in the window is the second metal layer 3. The upper surface of the second metal layer 3 is coplanar with the upper surface of the passivation layer 2, that is, at this time the thickness of the second metal layer 3 is equal to the thickness of the passivation layer 2.
[0049] The above method removes excess metal from the surface through physical grinding, which does not significantly increase costs. However, the physical grinding process may damage the passivation layer on the surface. When the thickness of the first metal layer 1 is thin, such as... Figure 7 As shown, the passivation layer 2 on top is relatively thick, which can support CMP (Chemical & Mechanical Polishing) operation. After CMP, a passivation layer 2 with a smooth surface can be obtained. At this time, the process in this embodiment can be used to remove the excess metal layer on the surface.
[0050] In another embodiment, adding a layer of metal material on the first metal layer 1 within the window in S3 can also be achieved using a photolithography + etching process, such as... Figure 5 As shown, the details are as follows:
[0051] S3-1. Deposit metallic material on the passivation layer 2 and the first metal layer 1 within the window.
[0052] S3-2, Coat the metal material surface in S3-1 with photoresist, and use a mask to selectively retain the photoresist in the window area;
[0053] S3-3. Etch away the metal material not protected by photoresist, and then remove the remaining photoresist. At this time, the metal layer remaining on the first metal layer 1 in the window is the second metal layer 3. The upper surface of the second metal layer 3 is higher than the upper surface of the passivation layer 2, that is, the thickness of the second metal layer 3 is greater than the thickness of the passivation layer 2.
[0054] Although the method in this embodiment requires an additional photolithography step, increasing costs, it allows for precise control of the morphology of the second metal layer 3, reducing damage to the passivation layer 2, and ultimately resulting in a higher quality solder pad structure. When the first metal layer 1 is thicker, the surface of the passivation layer 2 above it is undulating, such as... Figure 6 As shown, CMP cannot be performed at this time, so only photolithography and etching in this embodiment can be used to remove the excess metal layer on the surface. When the thickness of the first metal layer 1 is relatively thin, the thickness of the passivation layer 2 above it is relatively thick, such as... Figure 7 As shown, the process described in this embodiment can also be used to remove excess metal layers from the surface.
[0055] This invention also proposes a chip including the above-described pad structure.
[0056] In one embodiment, the thickness of the first metal layer 1 of the pad structure is equal to the thickness of the top metal layer in other areas of the chip.
[0057] In one embodiment, integrated circuit devices and traces are arranged beneath the pad structure. Because a thinner first metal layer 1 can be used, devices and traces can be placed beneath the pad structure, thereby reducing chip area and saving costs.
[0058] This utility model also proposes an integrated circuit, which includes several chips, and the chips include the above-mentioned pad structure.
[0059] The description and application of this utility model herein are illustrative and not intended to limit the scope of the utility model to the above embodiments. The effects or advantages described in the specification may not be apparent in actual experimental examples due to uncertainties in specific conditions or parameters or other factors, and such descriptions are not intended to limit the scope of the utility model. Variations and modifications to the embodiments disclosed herein are possible, and various substitutions and equivalent components of the embodiments are well known to those skilled in the art. It should be clear to those skilled in the art that this utility model can be implemented in other forms, structures, arrangements, proportions, and with other components, materials, and parts without departing from the spirit or essential characteristics of the utility model. Other variations and modifications can be made to the embodiments disclosed herein without departing from the scope and spirit of the utility model.
Claims
1. A pad structure, characterized in that, include: The first metal layer serves as the basic conductive layer of the pad structure. A passivation layer is applied over the first metal layer and has a window that exposes a portion of the first metal layer. A second metal layer covers the first metal layer within the window, serving as a thickened conductive layer for the pad structure.
2. The pad structure according to claim 1, characterized in that, The second metal layer is deposited on the first metal layer by physical vapor deposition.
3. The pad structure according to claim 1 or 2, characterized in that, The thickness of the second metal layer is greater than or equal to the thickness of the passivation layer.
4. The pad structure according to claim 1 or 2, characterized in that, The material of the first metal layer and / or the second metal layer is at least one of aluminum, copper, and aluminum alloy.
5. The pad structure according to claim 1, characterized in that, The passivation layer is made of at least one of silicon dioxide, silicon nitride, and polyimide.
6. A chip, characterized in that, Includes the pad structure as described in any one of claims 1-5.
7. The chip according to claim 6, characterized in that, The thickness of the first metal layer of the pad structure is equal to the thickness of the top metal layer in other areas of the chip.
8. The chip according to claim 6, characterized in that, Integrated circuit devices and traces are arranged below the pad structure.
9. An integrated circuit, characterized in that, It includes a plurality of chips, said chips including the pad structure as described in any one of claims 1-5.