Static protection isolation filter circuit of USB2.0 interface

Abstract

The utility model relates to USB interface technical field, concretely relates to a static protection isolation filter circuit of USB2.0 interface, including symmetry protection filter circuit, high frequency differential mode filter circuit and power line protection filter circuit, the symmetry protection filter circuit symmetry is equipped with the both ends of common mode inductance L1 and the both ends of common mode inductance L1 are respectively connected with the D+ end, D of USB2.0 interface and chip U1, the high frequency differential mode filter circuit is connected in series on the passage between common mode inductance L1 and chip U1, the power line protection filter circuit is connected on the passage between the power end of USB2.0 interface and external power supply. Through above -mentioned design, integrate triple protection mechanism, cover signal and power path comprehensively, solve high frequency interference inhibition deficiency, differential mode noise filter and static protection intensification problem.

Description

Technical Field

[0001] This utility model relates to the field of USB interface technology, specifically to an electrostatic discharge (ESD) protection and isolation filter circuit for a USB 2.0 interface. Background Technology

[0002] USB 2.0 interfaces are widely used in electronic devices, but existing protection and filtering circuits have shortcomings. For example... Figure 1 and Figure 2 As shown, a circuit consisting of three electrostatic discharge transistors and one common-mode inductor can solve basic electrostatic discharge and common-mode noise problems, but it still has the following drawbacks: insufficient high-frequency noise suppression on the D+ and D- signal lines; the common-mode inductor can only filter down to a few hundred MHz, and cannot filter out high-frequency interference noise from a few hundred MHz to GHz; the 5V power supply line lacks filtering measures, and interference noise coupling may cause electromagnetic compatibility radiated emission test data to exceed the standard; weak differential-mode noise suppression capability; the common-mode inductor mainly suppresses common-mode noise, and its filtering effect on differential-mode interference is poor; insufficient electrostatic protection capability, unable to fully protect against high-level electrostatic tests, which may affect the normal operation of back-end chips. Utility Model Content

[0003] In view of this, the purpose of this utility model is to provide an electrostatic discharge protection and isolation filter circuit for a USB 2.0 interface to solve the problems mentioned in the background art.

[0004] To achieve the above objectives, the technical solution adopted by this utility model is as follows:

[0005] An electrostatic discharge (ESD) protection and isolation filter circuit for a USB 2.0 interface includes a symmetrical protection filter circuit, a high-frequency differential mode filter circuit, and a power line protection filter circuit. The symmetrical protection filter circuit is symmetrically disposed across the two ends of a common-mode inductor L1, and the two ends of the common-mode inductor L1 are electrically connected to the D+ and D- terminals of the USB 2.0 interface and the chip U1, respectively. The high-frequency differential mode filter circuit is connected in series in the path between the common-mode inductor L1 and the chip U1. The power line protection filter circuit is connected in the path between the power supply terminal of the USB 2.0 interface and the external power supply.

[0006] Preferably, the symmetry protection filter circuit includes transient voltage suppressors D1, D2, D3, and D4, ceramic capacitors C1, C2, C3, and C4;

[0007] One end of the transient voltage suppressor D1 is connected to the D- terminal of the USB 2.0 interface and the common mode inductor L1, and the other end of the transient voltage suppressor D1 is grounded; one end of the transient voltage suppressor D2 is connected to the D+ terminal of the USB 2.0 interface and the common mode inductor L1, and the other end of the transient voltage suppressor D2 is grounded.

[0008] One end of the ceramic capacitor C1 is connected to the D- terminal of the USB 2.0 interface and the common mode inductor L1, and the other end of the ceramic capacitor C1 is grounded; one end of the ceramic capacitor C2 is connected to the D+ terminal of the USB 2.0 interface and the common mode inductor L1, and the other end of the ceramic capacitor C2 is grounded.

[0009] One end of the transient voltage suppressor D4 is connected to the high-frequency differential-mode filter circuit and the common-mode inductor L1, and the other end of the transient voltage suppressor D4 is grounded; one end of the transient voltage suppressor D3 is connected to the high-frequency differential-mode filter circuit and the common-mode inductor L1, and the other end of the transient voltage suppressor D3 is grounded.

[0010] One end of the ceramic capacitor C4 is connected to the high-frequency differential-mode filter circuit and the common-mode inductor L1, and the other end of the ceramic capacitor C4 is grounded; one end of the ceramic capacitor C3 is connected to the high-frequency differential-mode filter circuit and the common-mode inductor L1, and the other end of the ceramic capacitor C3 is grounded.

[0011] Preferably, the response time of transient voltage suppressors D1, D2, D3 and D4 is no greater than 1ns and the clamping voltage is no greater than 5V.

[0012] Preferably, the capacitance values ​​of the ceramic capacitors C1, C2, C3 and C4 are all in the range of 10nF-100nF, and their withstand voltage values ​​are all not less than 6.3V.

[0013] Preferably, the high-frequency differential mode filter circuit includes ferrite bead FB1 and ferrite bead FB2;

[0014] One end of the magnetic bead FB1 is electrically connected to one end of the transient voltage suppressor D4, one end of the ceramic capacitor C4, and the common mode inductor L1, respectively, and the other end of the magnetic bead FB1 is electrically connected to the chip U1.

[0015] One end of the magnetic bead FB2 is electrically connected to one end of the transient voltage suppressor D3, one end of the ceramic capacitor C3, and the common mode inductor L1, respectively, and the other end of the magnetic bead FB2 is electrically connected to the chip U1.

[0016] Preferably, the impedance of the magnetic beads FB1 and FB2 at a frequency of 100MHz is not less than 600Ω.

[0017] Preferably, the power line protection filter circuit includes a transient voltage suppressor D5, a ceramic capacitor C5, a ceramic capacitor C6, and a ferrite bead FB3;

[0018] One end of the transient voltage suppressor D5, one end of the ceramic capacitor C5, one end of the ceramic capacitor C6, and one end of the ferrite bead FB3 are all electrically connected to the power supply of the USB 2.0 interface. The other ends of the transient voltage suppressor D5, the ceramic capacitor C5, and the ceramic capacitor C6 are all grounded. The other end of the ferrite bead FB3 is electrically connected to an external power supply.

[0019] Preferably, the capacitance values ​​of the ceramic capacitors C5 and C6 are both in the range of 10nF-100nF, and their withstand voltage values ​​are both not less than 6.3V.

[0020] Preferably, the response time of the transient voltage suppressor D5 is no greater than 1 ns, and the clamping voltage is no greater than 5 V.

[0021] The beneficial effects of this utility model are:

[0022] This utility model provides an electrostatic discharge (ESD) protection and isolation filter circuit for a USB 2.0 interface, comprising a symmetrical protection filter circuit, a high-frequency differential-mode filter circuit, and a power line protection filter circuit. The symmetrical protection filter circuit is symmetrically arranged across the two ends of a common-mode inductor L1, and the two ends of the common-mode inductor L1 are electrically connected to the D+ and D- terminals of the USB 2.0 interface and the chip U1, respectively. The high-frequency differential-mode filter circuit is connected in series in the path between the common-mode inductor L1 and the chip U1. The power line protection filter circuit is connected in the path between the power supply terminal of the USB 2.0 interface and the external power supply. Through the above design, a triple protection mechanism is integrated, comprehensively covering the signal and power paths, solving the problems of insufficient high-frequency interference suppression, differential-mode noise filtering, and enhanced ESD protection. Through FCC PART 15B CLASSB standard testing: radiated emission values ​​are significantly reduced, high-frequency band (hundreds of MHz-GHz) noise suppression is improved, differential-mode noise filtering rate is increased by ≥40%, and the ESD protection level reaches IEC 61000-4-2 Level 4 (±15kV contact discharge). Attached Figure Description

[0023] Figure 1 This is a circuit connection diagram of a protection filter circuit widely used in USB 2.0 interfaces in the background technology of this utility model;

[0024] Figure 2 This is a diagram showing actual test data of the protection filter circuit widely used in USB 2.0 interfaces in the background technology of this utility model;

[0025] Figure 3 This is a circuit connection diagram of an electrostatic protection isolation filter circuit for a USB 2.0 interface according to this utility model;

[0026] Figure 4 This is a diagram showing actual test data of an electrostatic discharge (ESD) protection and isolation filter circuit for a USB 2.0 interface according to this utility model. Detailed Implementation

[0027] The present invention will be further described below with reference to the accompanying drawings and specific embodiments:

[0028] Definitions:

[0029] FCC Part 15B Class B: Part of the Federal Communications Commission's (FCC) regulations for radio frequency (RF) emissions from wireless communication devices and other non-wireless devices, which covers the electromagnetic compatibility (EMC) of the devices.

[0030] like Figure 3 and Figure 4 As shown, this utility model provides an electrostatic discharge (ESD) protection and isolation filter circuit for a USB 2.0 interface, including a symmetrical protection filter circuit, a high-frequency differential mode filter circuit, and a power line protection filter circuit. The symmetrical protection filter circuit is symmetrically arranged across the two ends of the common mode inductor L1, and the two ends of the common mode inductor L1 are electrically connected to the D+ and D- terminals of the USB 2.0 interface and the chip U1, respectively. The high-frequency differential mode filter circuit is connected in series in the path between the common mode inductor L1 and the chip U1. The power line protection filter circuit is connected in the path between the power supply terminal of the USB 2.0 interface and the external power supply.

[0031] The beneficial effects of this utility model are:

[0032] This utility model provides an electrostatic discharge (ESD) protection and isolation filter circuit for a USB 2.0 interface, comprising a symmetrical protection filter circuit, a high-frequency differential-mode filter circuit, and a power line protection filter circuit. The symmetrical protection filter circuit is symmetrically arranged across the two ends of a common-mode inductor L1, and the two ends of the common-mode inductor L1 are electrically connected to the D+ and D- terminals of the USB 2.0 interface and the chip U1, respectively. The high-frequency differential-mode filter circuit is connected in series in the path between the common-mode inductor L1 and the chip U1. The power line protection filter circuit is connected in the path between the power supply terminal of the USB 2.0 interface and the external power supply. Through the above design, a triple protection mechanism is integrated, comprehensively covering the signal and power paths, solving the problems of insufficient high-frequency interference suppression, differential-mode noise filtering, and enhanced ESD protection. Through FCC PART 15B CLASSB standard testing: radiated emission values ​​are significantly reduced, high-frequency band (hundreds of MHz-GHz) noise suppression is improved, differential-mode noise filtering rate is increased by ≥40%, and the ESD protection level reaches IEC 61000-4-2 Level 4 (±15kV contact discharge).

[0033] The common-mode inductor L1 is connected in series with the D+ and D- signal lines, and its input and output terminals are directly connected to the D+ and D- signal lines, as shown in the specific connection diagram. Figure 2 As shown, its function is to enhance common-mode noise suppression and reduce radiated emissions.

[0034] Preferably, the symmetry protection filter circuit includes transient voltage suppressors D1, D2, D3, and D4, ceramic capacitors C1, C2, C3, and C4;

[0035] One end of the transient voltage suppressor D1 is connected to the D- terminal of the USB 2.0 interface and the common mode inductor L1, and the other end of the transient voltage suppressor D1 is grounded; one end of the transient voltage suppressor D2 is connected to the D+ terminal of the USB 2.0 interface and the common mode inductor L1, and the other end of the transient voltage suppressor D2 is grounded.

[0036] One end of the ceramic capacitor C1 is connected to the D- terminal of the USB 2.0 interface and the common mode inductor L1, and the other end of the ceramic capacitor C1 is grounded; one end of the ceramic capacitor C2 is connected to the D+ terminal of the USB 2.0 interface and the common mode inductor L1, and the other end of the ceramic capacitor C2 is grounded.

[0037] One end of the transient voltage suppressor D4 is connected to the high-frequency differential-mode filter circuit and the common-mode inductor L1, and the other end of the transient voltage suppressor D4 is grounded; one end of the transient voltage suppressor D3 is connected to the high-frequency differential-mode filter circuit and the common-mode inductor L1, and the other end of the transient voltage suppressor D3 is grounded.

[0038] One end of the ceramic capacitor C4 is connected to the high-frequency differential-mode filter circuit and the common-mode inductor L1, and the other end of the ceramic capacitor C4 is grounded; one end of the ceramic capacitor C3 is connected to the high-frequency differential-mode filter circuit and the common-mode inductor L1, and the other end of the ceramic capacitor C3 is grounded.

[0039] The above design achieves bidirectional electrostatic discharge (ESD) protection and wideband noise filtering for the signal lines. Specifically, transient voltage suppressors D1 and D2 are connected to the D+ and D- signal lines respectively and grounded to suppress forward / reverse ESD crosstalk, thus achieving bidirectional ESD protection. Ceramic capacitors C1, C2, C3, and C4 form a π-type filter, enhancing common-mode noise suppression and widening the filtering frequency band.

[0040] Preferably, the high-frequency differential mode filter circuit includes ferrite bead FB1 and ferrite bead FB2; wherein, the impedance of ferrite bead FB1 and ferrite bead FB2 at a frequency of 100MHz is not less than 600Ω, and its function is to ensure effective absorption of high-frequency differential mode noise.

[0041] One end of the magnetic bead FB1 is electrically connected to one end of the transient voltage suppressor D4, one end of the ceramic capacitor C4, and the common mode inductor L1, respectively, and the other end of the magnetic bead FB1 is electrically connected to the chip U1.

[0042] One end of the magnetic bead FB2 is electrically connected to one end of the transient voltage suppressor D3, one end of the ceramic capacitor C3, and the common mode inductor L1, respectively, and the other end of the magnetic bead FB2 is electrically connected to the chip U1.

[0043] The above design can filter out GHz-level differential mode noise and consume residual electrostatic energy.

[0044] Preferably, the power line protection filtering circuit includes a transient voltage suppressor D5, ceramic capacitors C5 and C6, and a ferrite bead FB3. One end of the transient voltage suppressor D5, one end of ceramic capacitors C5 and C6, and one end of the ferrite bead FB3 are all electrically connected to the power supply terminal of the USB 2.0 interface. The other ends of the transient voltage suppressor D5, ceramic capacitors C5 and C6 are all grounded, and the other end of the ferrite bead FB3 is electrically connected to an external power supply. This circuit design suppresses conducted interference on the power line and discharges electrostatic energy. The ferrite bead FB3 is connected in series with the input terminal of the external power supply, which can block external noise from coupling to the external power supply. The external power supply is a 5V power supply.

[0045] In this embodiment, the capacitance values ​​of ceramic capacitors C1, C2, C3, C4, C5, and C6 are all in the range of 10nF-100nF, and their withstand voltage is not less than 6.3V. Their function is to optimize high-frequency noise filtering and ensure circuit stability. The response times of transient voltage suppressors D1, D2, D3, D4, and D5 are all no greater than 1ns, and their clamping voltages are all no greater than 5V, enabling rapid discharge of static electricity and protection of the back-end chips.

[0046] In this embodiment, the test is performed using the FCC Part 15B Class B standard. Figure 2 and Figure 4 It is evident that this application demonstrates a significant improvement in electromagnetic compatibility radiated emission testing compared to the widely used traditional USB 2.0 interface circuit.

[0047] This utility model has been described with reference to the above-described embodiments and accompanying drawings. However, the above embodiments are merely examples for implementing this utility model. It must be noted that the disclosed embodiments do not limit the scope of this utility model. On the contrary, modifications and equivalent provisions included in the spirit and scope of the claims are all included within the scope of this utility model.

Claims

1. An electrostatic discharge (ESD) protection and isolation filter circuit for a USB 2.0 interface, characterized in that: It includes a symmetrical protection filter circuit, a high-frequency differential mode filter circuit, and a power line protection filter circuit; the symmetrical protection filter circuit is symmetrically arranged across the two ends of the common mode inductor L1, and the two ends of the common mode inductor L1 are electrically connected to the D+ and D- terminals of the USB 2.0 interface and the chip U1, respectively; the high-frequency differential mode filter circuit is connected in series in the path between the common mode inductor L1 and the chip U1; the power line protection filter circuit is connected in the path between the power supply terminal of the USB 2.0 interface and the external power supply.

2. The electrostatic discharge (ESD) protection and isolation filter circuit for a USB 2.0 interface according to claim 1, characterized in that: The symmetry protection filter circuit includes transient voltage suppressors D1, D2, D3, and D4, ceramic capacitors C1, C2, C3, and C4; One end of the transient voltage suppressor D1 is connected to the D- terminal of the USB 2.0 interface and the common mode inductor L1, and the other end of the transient voltage suppressor D1 is grounded; one end of the transient voltage suppressor D2 is connected to the D+ terminal of the USB 2.0 interface and the common mode inductor L1, and the other end of the transient voltage suppressor D2 is grounded. One end of the ceramic capacitor C1 is connected to the D- terminal of the USB 2.0 interface and the common mode inductor L1, and the other end of the ceramic capacitor C1 is grounded; one end of the ceramic capacitor C2 is connected to the D+ terminal of the USB 2.0 interface and the common mode inductor L1, and the other end of the ceramic capacitor C2 is grounded. One end of the transient voltage suppressor D4 is connected to the high-frequency differential-mode filter circuit and the common-mode inductor L1, and the other end of the transient voltage suppressor D4 is grounded; one end of the transient voltage suppressor D3 is connected to the high-frequency differential-mode filter circuit and the common-mode inductor L1, and the other end of the transient voltage suppressor D3 is grounded. One end of the ceramic capacitor C4 is connected to the high-frequency differential-mode filter circuit and the common-mode inductor L1, and the other end of the ceramic capacitor C4 is grounded; one end of the ceramic capacitor C3 is connected to the high-frequency differential-mode filter circuit and the common-mode inductor L1, and the other end of the ceramic capacitor C3 is grounded.

3. The electrostatic discharge (ESD) protection and isolation filter circuit for a USB 2.0 interface according to claim 2, characterized in that: The response time of transient voltage suppressors D1, D2, D3 and D4 is no greater than 1ns, and the clamping voltage is no greater than 5V.

4. The electrostatic discharge (ESD) protection and isolation filter circuit for a USB 2.0 interface according to claim 2, characterized in that: The capacitance values ​​of the ceramic capacitors C1, C2, C3, and C4 are all in the range of 10nF to 100nF, and their withstand voltage is not less than 6.3V.

5. The electrostatic discharge (ESD) protection and isolation filter circuit for a USB 2.0 interface according to claim 2, characterized in that: The high-frequency differential mode filter circuit includes ferrite bead FB1 and ferrite bead FB2; One end of the magnetic bead FB1 is electrically connected to one end of the transient voltage suppressor D4, one end of the ceramic capacitor C4, and the common mode inductor L1, respectively, and the other end of the magnetic bead FB1 is electrically connected to the chip U1. One end of the magnetic bead FB2 is electrically connected to one end of the transient voltage suppressor D3, one end of the ceramic capacitor C3, and the common mode inductor L1, respectively, and the other end of the magnetic bead FB2 is electrically connected to the chip U1.

6. The electrostatic discharge (ESD) protection and isolation filter circuit for a USB 2.0 interface according to claim 5, characterized in that: The impedance of the magnetic beads FB1 and FB2 at a frequency of 100MHz is not less than 600Ω.

7. The electrostatic discharge (ESD) protection and isolation filter circuit for a USB 2.0 interface according to claim 1, characterized in that: The power line protection filter circuit includes a transient voltage suppressor D5, a ceramic capacitor C5, a ceramic capacitor C6, and a ferrite bead FB3. One end of the transient voltage suppressor D5, one end of the ceramic capacitor C5, one end of the ceramic capacitor C6, and one end of the ferrite bead FB3 are all electrically connected to the power supply of the USB 2.0 interface. The other ends of the transient voltage suppressor D5, the ceramic capacitor C5, and the ceramic capacitor C6 are all grounded. The other end of the ferrite bead FB3 is electrically connected to an external power supply.

8. The electrostatic discharge (ESD) protection and isolation filter circuit for a USB 2.0 interface according to claim 7, characterized in that: The capacitance values ​​of ceramic capacitors C5 and C6 are both in the range of 10nF to 100nF, and their withstand voltage is not less than 6.3V.

9. The electrostatic discharge (ESD) protection and isolation filter circuit for a USB 2.0 interface according to claim 7, characterized in that: The transient voltage suppressor D5 has a response time of no more than 1 ns and a clamping voltage of no more than 5 V.

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