A permanganate ion selective photoelectric synergistic transient recognition system

Abstract

The utility model provides a kind of permanganate ion selective photoelectricity collaborative transient identification system, comprising: optical detection circuit, include light source drive circuit and photoelectric detection circuit;Micro-current pulse circuit is used to generate controllable micro-current pulse;Signal acquisition circuit, its input end is connected with the output end of photoelectric detection circuit;Phase-locked amplification circuit, its signal input end is connected with the output end of photoelectric detection circuit;Timing control circuit, using FPGA controls four-way synchronous signal to realize nanosecond level timing accuracy;Timing control circuit controls in the same measurement period first start light source to carry out baseline detection, then keep light source work while starting micro-current pulse to carry out collaborative excitation, finally stop pulse continues to light to carry out recovery detection. System is through photoelectricity collaborative excitation mechanism and transient feature extraction, realizes the selective detection of permanganate in high salt environment, improves detection precision, shortens response time.

Description

Technical Field

[0001] This invention belongs to the field of ion detection, and in particular to a selective photoelectric coordinated transient recognition system for permanganate ions. Background Technology

[0002] Permanganate is an important indicator of the redox state and organic pollution level of water bodies, playing a crucial role in marine environmental monitoring, industrial wastewater treatment, and drinking water safety assessment. Particularly in high-salt, high-chlorine seawater environments, accurate detection of permanganate concentration is vital for marine ecological protection, mariculture water quality management, and coastal industrial discharge monitoring. With the rapid development of the marine economy and increasingly stringent environmental protection requirements, there is an urgent need to develop advanced technologies for continuous online monitoring of permanganate in complex seawater matrices. While traditional laboratory analytical methods offer high precision, they cannot meet the demands of real-time on-site monitoring, and existing online detection technologies face significant technical challenges in high-salt, high-chlorine environments.

[0003] Existing online detection technologies for permanganate mainly fall into three categories: spectrophotometry, electrochemical methods, and chemiluminescence methods. Spectrophotometry is based on the characteristic absorption of permanganate ions at wavelengths of 525 nm or 545 nm, employing a single light source and a single photodetector design. Signal processing typically involves simple voltage amplification and a single ADC for acquisition. Electrochemical methods primarily use cyclic voltammetry or chronoamperometry, employing a three-electrode system to detect the redox reaction current. Signal processing utilizes traditional current-to-voltage conversion and low-pass filtering. Chemiluminescence methods utilize the reaction between permanganate and a luminescent reagent to generate a light signal, which is detected using a photomultiplier tube or photodiode. These methods often employ simple timers or microcontrollers for timing control, with timing accuracy typically in the microsecond range. Signal synchronization relies primarily on software delays. Regarding temperature compensation, existing technologies mainly employ single-point temperature measurement and linear compensation algorithms.

[0004] The existing technology has two core technical problems: First, it lacks a hardware-level multi-signal precise synchronization mechanism, resulting in timing uncertainties between optical detection and electrochemical excitation. Second, the signal processing circuit lacks the ability to extract frequency domain steady-state information and time domain transient information in parallel. Utility Model Content

[0005] Purpose of the utility model: To provide a permanganate ion selective photoelectric coordinated transient recognition system, in order to solve at least one technical problem existing in the prior art.

[0006] Technical solution: A permanganate ion selective photoelectric coordinated transient recognition system, comprising:

[0007] Optical detection circuit, including light source driving circuit and photoelectric detection circuit;

[0008] Microcurrent pulse circuit, used to generate controllable microcurrent pulses;

[0009] The signal acquisition circuit has its input terminal connected to the output terminal of the photoelectric detection circuit.

[0010] A lock-in amplifier circuit, whose signal input terminal is connected to the output terminal of a photoelectric detection circuit;

[0011] The timing control circuit has a first output terminal connected to the light source driving circuit, a second output terminal connected to the micro-current pulse circuit, a third output terminal connected to the signal acquisition circuit, and a fourth output terminal connected to the reference input terminal of the lock-in amplifier circuit.

[0012] The timing control circuit controls the following within the same measurement cycle: it starts the light source driving circuit for baseline detection, starts the micro-current pulse circuit for coordinated excitation while keeping the light source driving circuit working, stops the micro-current pulse circuit and continues to work the light source driving circuit for recovery detection; the signal acquisition circuit and the lock-in amplifier circuit simultaneously acquire the output signal of the photoelectric detection circuit during the coordinated excitation and recovery detection periods.

[0013] Beneficial effects: This invention achieves selective detection of permanganate in high-salt environments through photoelectric synergistic excitation mechanism and transient feature extraction, thereby improving detection accuracy and shortening response time. Attached Figure Description

[0014] Figure 1 The topology diagram of a permanganate ion selective photoelectric coordinated transient recognition system provided by this utility model.

[0015] Figure 2 The circuit diagram of the optical detection circuit provided by this utility model.

[0016] Figure 3 The circuit diagram of the microcurrent pulse circuit provided by this utility model.

[0017] Figure 4 The timing control diagram of the permanganate ion selective photoelectric coordinated transient recognition system provided by this utility model. Detailed Implementation

[0018] The study found that in traditional techniques, optical and electrochemical detection are often performed independently, and even within the same system, nanosecond-level timing synchronization is difficult to achieve. This timing deviation significantly affects the accurate acquisition of transient signals and the reproducibility of feature extraction. Existing software synchronization methods are affected by operating system scheduling and interrupt response, with timing jitter typically on the order of tens of microseconds, failing to meet the precise measurement requirements of fast transient processes. Furthermore, traditional techniques either focus only on steady-state response amplitude or only record time-domain waveforms, lacking a hardware architecture that synchronizes phase-locked detection and high-speed sampling. This single-dimensional information extraction method limits the selective identification capability of target substances in complex matrices, especially in highly interference environments where it is difficult to effectively distinguish target signals from background noise. Existing signal processing circuits typically employ a serial structure, performing analog processing first and then digital acquisition, failing to simultaneously obtain phase-locked steady-state characteristics and complete transient recovery process information.

[0019] like Figure 1 As shown, a permanganate ion selective photoelectric coordinated transient recognition system is proposed, comprising:

[0020] Optical detection circuit, including light source driving circuit and photoelectric detection circuit;

[0021] Microcurrent pulse circuit, used to generate controllable microcurrent pulses;

[0022] The signal processing circuit includes a signal acquisition circuit and a lock-in amplifier circuit, wherein the input terminal of the signal acquisition circuit is connected to the output terminal of the photoelectric detection circuit; the signal input terminal of the lock-in amplifier circuit is connected to the output terminal of the photoelectric detection circuit.

[0023] The timing control circuit has a first output terminal connected to the light source driving circuit, a second output terminal connected to the micro-current pulse circuit, a third output terminal connected to the signal acquisition circuit, and a fourth output terminal connected to the reference input terminal of the lock-in amplifier circuit.

[0024] The timing control circuit controls the following within the same measurement cycle: first, the light source driving circuit is started to perform baseline detection; then, while keeping the light source driving circuit working, the micro-current pulse circuit is started to perform coordinated excitation; finally, the micro-current pulse circuit is stopped and the light source driving circuit continues to work to perform recovery detection; the signal acquisition circuit and the lock-in amplifier circuit simultaneously acquire the output signal of the photoelectric detection circuit during the coordinated excitation and recovery detection periods.

[0025] According to one aspect of this application, the optical detection circuit includes:

[0026] LED constant current driving circuit, including a constant current source chip, whose output terminal is connected to an LED with a wavelength of 545nm;

[0027] A photodiode is placed in the optical path of an LED to receive transmitted light;

[0028] A transimpedance amplifier, whose inverting input is connected to the cathode of a photodiode, and whose output is connected to the inverting input through a parallel branch of a feedback resistor and a feedback capacitor;

[0029] A programmable gain amplifier whose input is connected to the output of a transimpedance amplifier.

[0030] In one embodiment of this application, such as Figure 2 As shown, the optical detection circuit adopts a series signal processing link topology, including an LED constant current drive circuit, a photodiode, a transimpedance amplifier, and a programmable gain amplifier circuit. The LED constant current drive circuit components are connected as follows: the power input (+12V) is connected to the input terminal of the constant current source chip U1 (LM317), and the output terminal is connected to 545nm LED1. The negative terminal of LED1 is grounded. The adjustment terminal (ADJ) of the constant current source chip U1 is connected to ground through a precision resistor R1 (12.5Ω, ±1%). The cathode of the photodiode PD1 (BPW34) is connected to -5V reverse bias, and the anode is connected to the inverting input terminal of the transimpedance amplifier U2 (OPA380). The non-inverting input terminal of the transimpedance amplifier U2 is grounded. The feedback network consists of a 1MΩ resistor R2 and a 10pF capacitor C1 connected in parallel, connected from the output terminal to the inverting input terminal. In the programmable gain amplifier circuit, the input of programmable gain amplifier U3 (PGA281) is connected to the output of a transimpedance amplifier. The SPI control interface is connected to a field-programmable gate array (FPGA) to achieve programmable gain adjustment. The output is sent to the subsequent circuit after passing through a low-pass filter composed of a 1kΩ resistor R3 and a 100nF capacitor C3. The other end of capacitor C3 is grounded. Optionally, the temperature compensation circuit includes a temperature sensor U4 (LM35) connected to operational amplifier U5, and the output is fed back to the input of the constant current source chip.

[0031] The optical detection circuit's operation embodies the design of constant current drive and temperature compensation. The LM317 constant current source precisely sets the 100mA drive current through adjusting resistor R1. The temperature compensation circuit monitors the LED temperature in real time and adjusts the drive current to compensate for temperature drift in the LED light output, ensuring the light source stability is better than ±0.3% / °C. The BPW34 photodiode operates in zero-bias mode to eliminate the influence of dark current. The OPA380 transimpedance amplifier converts the photocurrent into a voltage signal. A 1MΩ feedback resistor sets the transimpedance gain, and a 10pF feedback capacitor compensates for the frequency response, achieving a 15.9kHz bandwidth. The PGA281 programmable gain amplifier dynamically adjusts the gain from 1 to 128 times via the SPI interface, adapting to large dynamic range signal detection and achieving a dynamic range coverage of six orders of magnitude.

[0032] According to one aspect of this application, the microcurrent pulse circuit includes:

[0033] Digital-to-analog converter (DAC);

[0034] A precision operational amplifier, whose non-inverting input is connected to the output of a digital-to-analog converter (DAC).

[0035] The MOSFET constant current source has its gate connected to the output of a precision operational amplifier, its source grounded through a current sensing resistor, and its drain outputting a small current. The connection point between the source and the current sensing resistor is fed back to the inverting input of the precision operational amplifier to form a current closed-loop control.

[0036] The pulse generator's output is connected to the control terminal of an analog switch, which is connected in series in the drain output path of the MOSFET constant current source.

[0037] According to one aspect of this application, the microcurrent pulse circuit further includes:

[0038] The three-electrode interface circuit includes a working electrode interface, a counter electrode interface, and a reference electrode interface.

[0039] A potentiometer, with its working electrode end connected to the working electrode interface, its counter electrode end connected to the counter electrode interface, its reference electrode end connected to the reference electrode interface, and its current output terminal connected to the input terminal of an analog switch.

[0040] According to one aspect of this application, the pulse generator includes:

[0041] The timer chip is configured in monostable mode. The trigger terminal of the timer chip is connected to the current pulse trigger terminal, and the output terminal of the timer chip is connected to the control terminal of the analog switch.

[0042] The first timing resistor and the second timing resistor are connected in series between the power supply and the timing terminal of the timer chip;

[0043] The timing capacitor is connected between the timing terminal of the timer chip and ground.

[0044] The drain output microcurrent of the MOSFET constant current source is transmitted to the working electrode interface through an analog switch and a potentiometer. The analog switch is turned on during the high level output of the timer chip to realize the microcurrent output with controllable pulse width.

[0045] In one embodiment of this application, such as Figure 3As shown, the micro-current pulse circuit adopts a dual feedback loop topology, including a precision current source circuit and a pulse timing control circuit. The components of the precision current source circuit are connected as follows: the digital-to-analog converter U6 (DAC8568) receives the FPGA control signal through the SPI interface and outputs a 0-5V analog voltage to the non-inverting input of the precision operational amplifier U7 (OPA2277). The output of the precision operational amplifier U7 is connected to one end of the gate current limiting resistor R4 (100Ω), and the other end of the gate current limiting resistor R4 is connected to the gate of the MOSFET constant current source Q1 (2N7002). The source of the MOSFET constant current source Q1 is grounded through the precision current sensing resistor Rs (100Ω, ±0.01%). The drain of the MOSFET constant current source Q1 outputs a micro-current, and the voltage at the connection node between the source and the sensing resistor is fed back to the inverting input of the precision operational amplifier to form a current closed-loop control. In the pulse timing control circuit, timer U8 (NE555) is configured in monostable mode. Pins 2 and 6 of timer U8 are connected to one end of resistor Rb, and the other end of resistor Rb is connected to one end of timing capacitor C5, with the other end of timing capacitor C5 grounded. Pin 8 of timer U8 is connected to one end of resistor Ra, and the other end of resistor Ra is connected to pin 4 of timer U8. Resistor Ra (10kΩ) and Rb (100kΩ) and timing capacitor C5 (10nF) set the pulse parameters. Pin 3 of timer U8 is connected to one end of analog switch U59, and the other end of analog switch U59 is connected to the drain of MOSFET constant current source Q1. The on / off state of the current pulse is controlled by analog switch U59 (ADG1419). Optionally, the micro-current pulse circuit also includes a three-electrode interface circuit, which includes a working electrode (WE), a counter electrode (CE), and a reference electrode (RE), connected to the micro-current pulse output terminal through potentiometer U9 (LMP91000).

[0046] This embodiment demonstrates precise control using dual feedback. The DAC8568 generates a high-precision control voltage, and the OPA2277 low-drift operational amplifier drives the MOSFET to operate in the linear region. A negative feedback loop is formed through voltage feedback from the source current sensing resistor, achieving current accuracy control of ±0.1%. The NE555 timer generates a precise 10ms pulse width, and the ADG1419 analog switch performs pulse modulation. This dual feedback structure ensures both current accuracy and dynamic monitoring. The current output range is continuously adjustable from 1-100μA, with a resolution of 0.076μA and a response time of <1μs, providing ideal pulse conditions for the electrochemical excitation of permanganate ions.

[0047] According to one aspect of this application, the signal acquisition circuit includes:

[0048] A high-speed analog-to-digital converter, whose analog input is connected to the output of a photoelectric detection circuit, and whose sampling clock is connected to the third output of a timing control circuit;

[0049] The lock-in amplifier circuit includes:

[0050] A lock-in amplifier, whose signal input terminal is connected to the output terminal of a photoelectric detection circuit, and whose reference input terminal is connected to the fourth output terminal of a timing control circuit;

[0051] An analog filter is connected in series between the output of the photoelectric detection circuit and the analog input of the high-speed analog-to-digital converter.

[0052] The high-speed analog-to-digital converter records the complete waveform from the co-excitation stage to the recovery detection stage at a sampling rate of not less than 1 MSPS. The lock-in amplifier is used to extract the steady-state response amplitude during the co-excitation. The high-speed analog-to-digital converter and the lock-in amplifier process the same output signal from the photoelectric detection circuit in parallel to achieve synchronous extraction of steady-state and transient features.

[0053] The timing control circuit controls the LED constant current drive circuit, pulse generator, signal acquisition circuit and lock-in amplifier circuit to achieve nanosecond-level timing synchronization.

[0054] In one embodiment of this application, the signal processing circuit adopts a parallel processing topology architecture, including a lock-in amplifier circuit and a signal acquisition circuit. The signal acquisition circuit is a high-speed acquisition circuit, including a high-speed analog-to-digital converter. The lock-in amplifier circuit includes a lock-in amplifier and an analog filtering branch. In the lock-in amplifier branch, the signal input terminal of the lock-in amplifier U10 (AD630) is connected to the output of the optical detection circuit, and the reference input terminal is connected to the FPGA reference signal output. The power supply adopts a ±15V dual power supply. The analog filtering branch adopts a 4th-order Butterworth cascaded topology. The first-stage Sallen-Key circuit consists of an operational amplifier U11 (OP07), resistors R5 and R6 (both 10kΩ), and capacitors C6 (2.2nF) and C7 (1.0nF). The second-stage Sallen-Key circuit consists of an operational amplifier U12 (OP07), resistors R7 and R8 (both 10kΩ), and capacitors C8 (2.2nF) and C9 (1.0nF). The two cascaded stages achieve a cutoff frequency of 10.6kHz and a stopband attenuation of -80dB / dec. In the high-speed acquisition branch, the low-noise buffer U13 (OPA4277) is connected to the filter output. The anti-aliasing filter consists of a 100Ω resistor and a 10nF capacitor. The high-speed ADCU14 (ADS8688) adopts a 16-bit SAR architecture, a 1MSPS sampling rate, a +5V reference voltage, and an SPI interface for connecting to the FPGA and DSP.

[0055] This embodiment demonstrates parallel processing in the frequency and time domains. The AD630 lock-in amplifier extracts the useful signal that is in phase and frequency with the reference signal, suppressing noise and interference. Dual-phase detection technology simultaneously obtains amplitude and phase information. The 4th-order Butterworth filter employs a Sallen-Key cascaded topology, offering a steeper roll-off (-80dB / dec) and better passband flatness (<0.1dB ripple) compared to traditional single-stage filters. The ADS8688 high-speed ADC acquires the complete waveform in parallel, with a 1MSPS sampling rate ensuring accurate capture of transient signals. This parallel processing architecture of frequency-domain phase-locked detection and high-speed time-domain sampling obtains both steady-state response characteristics and captures the transient recovery process, providing rich signal information for multi-dimensional feature extraction.

[0056] According to one aspect of this application, the analog filter, i.e., the analog filter branch, includes:

[0057] The first-stage Sallen-Key filter includes a first operational amplifier, a first resistor, a second resistor, a first capacitor, and a second capacitor. One end of the first resistor is connected to the output of the photodetector circuit, and the other end is connected to the non-inverting input of the first operational amplifier and one end of the second resistor. The other end of the second resistor is connected to the output of the first operational amplifier and one end of the first capacitor. The other end of the first capacitor is connected to the non-inverting input of the first operational amplifier. The second capacitor is connected between the non-inverting input of the first operational amplifier and ground. The inverting input of the first operational amplifier is directly connected to its output.

[0058] The second-stage Sallen-Key filter includes a second operational amplifier, a third resistor, a fourth resistor, a third capacitor, and a fourth capacitor. One end of the third resistor is connected to the output of the first-stage Sallen-Key filter, and the other end is connected to the non-inverting input of the second operational amplifier and one end of the fourth resistor. The other end of the fourth resistor is connected to the output of the second operational amplifier and one end of the third capacitor. The other end of the third capacitor is connected to the non-inverting input of the second operational amplifier. The fourth capacitor is connected between the non-inverting input of the second operational amplifier and ground. The inverting input of the second operational amplifier is directly connected to its output.

[0059] The resistance of the first, second, third, and fourth resistors is 10kΩ, the capacitance of the first and third capacitors is 2.2nF, and the capacitance of the second and fourth capacitors is 1.0nF. The two cascaded stages realize the fourth-order Butterworth filter characteristics.

[0060] According to one aspect of this application, the timing control circuit includes:

[0061] The FPGA main controller is configured with a sequential state machine.

[0062] A high-precision clock source is connected to the clock input of the FPGA main controller;

[0063] The output ports of the FPGA main controller include:

[0064] The LED enable terminal outputs a PWM signal with an adjustable duty cycle to the light source driver circuit.

[0065] The current pulse trigger terminal outputs a delayed trigger pulse to the pulse generator during the high-level period of the LED enable terminal signal.

[0066] The synchronous sampling terminal outputs a sampling window signal synchronized with the delayed trigger pulse to a high-speed analog-to-digital converter;

[0067] The reference signal terminal outputs a square wave signal with the same frequency as the optical modulation to the lock-in amplifier.

[0068] The delay time of the delayed trigger pulse relative to the rising edge of the LED enable signal can be programmed. The sampling window signal covers the three time periods before, during and after the current pulse. The FPGA main controller realizes nanosecond-level timing synchronization between the LED enable terminal, the current pulse trigger terminal, the synchronous sampling terminal and the reference signal terminal through a timing state machine.

[0069] In one embodiment of this application, the timing synchronization control circuit adopts a hierarchical timing management topology, including a main controller branch, a clock management branch, and a multi-output branch. In the main controller branch, the Spartan-6 XC6SLX9 FPGA is configured with a timing state machine, powered by a +3.3V I / O power supply and a +1.2V core power supply. In the clock management branch, a 100MHz TCXO clock source is connected to the FPGA clock input, providing a reference clock with ±10ppm stability. The multi-output branch includes: an LED enable terminal outputting a 1kHz PWM signal with an adjustable duty cycle to the light source driver circuit; a current pulse trigger terminal outputting a 10ms delayed trigger pulse to the pulse generator during the high level of the LED enable signal; a synchronization sampling terminal outputting a 1MHz sampling window signal synchronized with the delayed trigger pulse to the high-speed ADC; and a reference signal terminal outputting a square wave signal with the same frequency as the optical modulation to the lock-in amplifier.

[0070] This embodiment demonstrates nanosecond-level precision control. The FPGA's internal timing state machine generates four synchronous control signals based on a 100MHz reference clock. The LED enable signal uses 1kHz PWM modulation to control the light source switch. The current pulse trigger signal is precisely delayed by 20ms relative to the LED signal to ensure coordinated excitation timing. The ADC synchronous sampling signal provides a 1MHz sampling clock, and the phase-locked loop reference signal is synchronized with the LED modulation to ensure phase locking. This multi-layered timing nesting design achieves nanosecond-level synchronization accuracy, with trigger jitter <±10ns, providing a precise timing control foundation for photoelectric coordinated detection.

[0071] According to one aspect of this application, a temperature compensation circuit is also included, the temperature compensation circuit comprising:

[0072] Temperature sensor, outputting a current signal proportional to absolute temperature;

[0073] A reference current source that outputs a constant reference current;

[0074] The first precision resistor has one end connected to the output terminal of the temperature sensor and the other end grounded.

[0075] The second precision resistor has one end connected to the output terminal of the reference current source and the other end grounded. The first and second precision resistors have the same resistance value.

[0076] An instrumentation amplifier, whose non-inverting input is connected to the connection node of the first precision resistor and the output of the temperature sensor, and whose inverting input is connected to the connection node of the second precision resistor and the output of the reference current source.

[0077] A reference voltage source is connected to the reference terminal of the instrumentation amplifier;

[0078] The output buffer has its input connected to the output of the instrumentation amplifier. The output of the output buffer is connected to the auxiliary channel input of the signal acquisition circuit to provide temperature compensation data for the high-speed analog-to-digital converter. The difference between the output current of the temperature sensor and the reference current is converted into a differential voltage through the first and second precision resistors. The instrumentation amplifier amplifies the differential voltage and eliminates common-mode interference.

[0079] In one embodiment of this application, the temperature compensation circuit employs a dual-current-source differential measurement topology, comprising a temperature sensing branch, a reference current branch, and a differential amplification branch. In the temperature sensing branch, the temperature sensor (AD590) outputs a current signal (1μA / K) proportional to the temperature. The reference current branch generates a 298μA reference current through a precision resistor. The two currents are precisely replicated using a current mirror circuit. In the differential amplification branch, the two currents are converted into voltage signals through a 1.000kΩ precision resistor (±0.01% accuracy, 5ppm / °C temperature coefficient). The differential voltage is fed into an instrumentation amplifier (INA128), with a gain setting resistor Rg (490Ω) determining the amplification factor to be 101. The reference voltage is provided by an ADR431 at +2.500V. The output, after passing through a 1kΩ / 100nF low-pass filter and an OPA277 buffer, provides a 0.5V–3.5V temperature signal output.

[0080] This embodiment enables differential measurement to eliminate common-mode errors. The AD590 sensor output current is strictly proportional to the absolute temperature (1μA / K), and the reference current source generates a 298μA reference current corresponding to 25°C. The difference between the two currents reflects the temperature deviation. The dual current sources are converted into differential voltages through precision matching resistors. The INA128 instrumentation amplifier has an extremely high common-mode rejection ratio (>120dB), effectively eliminating the effects of power supply fluctuations and environmental interference. The ADR431 high-precision reference voltage source provides a 2.500V reference, ensuring absolute measurement accuracy. Differential current measurement technology achieves a temperature measurement accuracy of ±0.5°C, providing a reliable basis for temperature compensation in concentration measurements.

[0081] According to one aspect of this application, the transimpedance amplifier is an operational transimpedance amplifier OPA380, the resistance of the feedback resistor is 1MΩ, and the capacitance of the feedback capacitor is 10pF.

[0082] The programmable gain amplifier is a PGA281, which is connected to the FPGA master controller via an SPI interface to achieve gain adjustment from 1x to 128x;

[0083] The photodiode is a silicon photodiode BPW34, which operates in zero-bias mode. Its cathode is connected to ground potential, and its anode is connected to the inverting input of the transimpedance amplifier.

[0084] The digital-to-analog converter (DAC) is a DAC8568, which is connected to the FPGA main controller via an SPI interface.

[0085] The precision operational amplifier is an OPA2277, whose output is connected to the gate of a MOSFET constant current source through a gate current limiting resistor;

[0086] The MOSFET constant current source is an N-channel MOSFET 2N7002, whose source is connected to ground potential through a current sensing resistor;

[0087] The current sensing resistor has a resistance of 100Ω and an accuracy of ±0.01%.

[0088] The high-speed analog-to-digital converter is ADS8688, with a sampling rate of 1MSPS and a resolution of 16 bits;

[0089] The lock-in amplifier is an AD630.

[0090] According to one aspect of this application, a power management circuit is also included, the power management circuit comprising:

[0091] A switching regulator whose input is connected to an external power supply and whose output provides a first regulated power supply;

[0092] The first linear regulator has its input connected to the first regulated power supply and its output providing a +3.3V power supply to the I / O power supply of the FPGA main controller.

[0093] The second linear regulator has its input connected to the first regulated power supply and its output providing a +1.2V power supply to the core power supply terminal of the FPGA main controller.

[0094] A bipolar converter has its input connected to a first regulated power supply, its positive output provides a +15V power supply, and its negative output provides a -15V power supply. The +15V and -15V power supplies provide dual power supplies for the transimpedance amplifier, the precision operational amplifier, and the lock-in amplifier.

[0095] An EMI filter is connected in series between the external power supply and the input of the switching regulator.

[0096] The multi-channel voltage monitor has its monitoring input terminals connected to a +3.3V power supply, a +1.2V power supply, a +15V power supply, and a -15V power supply, respectively.

[0097] The switching frequency of the switching regulator is set to 150kHz, the output voltage of the first regulated power supply is +5.16V, and the EMI filter includes a common-mode choke and a safety capacitor.

[0098] In one embodiment of this application, the power management circuit adopts a multi-stage voltage regulation topology, including an input protection branch, a switching regulation branch, a linear post-regulation branch, and a monitoring and protection branch. In the input protection branch, a 3A fast-blow fuse F1, a common-mode choke (L_CM), an SMBJ15A TVS transient suppressor, and an X2 safety capacitor (CX) constitute EMI filtering and overvoltage protection. In the switching regulation branch, the LM2596S-ADJ buck converter, along with a 68μH inductor L2 (5A saturation current) and a 1000μF low-ESR capacitor C10, achieves a +5.16V / 3A output. The switching frequency is set to 150kHz. Feedback resistors R9 (2.4kΩ) and R10 (1.2kΩ) set the output voltage, and a 22μF ceramic capacitor and a 0.1μF decoupling capacitor are connected in parallel to provide high-frequency filtering. The linear regulator branch includes an AMS1117-3.3 linear regulator (1A output) and an AMS1117-1.2 linear regulator (0.8A output) to provide digital and core power to the FPGA. A TPS65130 bipolar converter generates ±15V / 200mA to power the analog circuitry. In the monitoring and protection branch, a TPS3851 timing controller manages the power supply, a TPS3431 four-channel voltage monitor monitors the status of multiple power supplies, an LM75 temperature monitor sets an 85°C over-temperature threshold, and an INA219 current monitor connects to the I / O circuit. 2 The C interface enables current detection within a range of ±3.2A, and multiple LED indicators display the status of each power supply.

[0099] This embodiment achieves low noise through multi-stage filtering. The input EMI filter effectively suppresses electromagnetic interference. The LM2596S switching regulator uses a 150kHz switching frequency to avoid sensitive signal frequencies. Multi-stage LC filtering and capacitor combinations suppress switching ripple to <5mVpp. The linear regulator further reduces ripple to <1mVpp, providing ultra-low noise power for sensitive analog circuits. The TPS65130 bipolar converter provides ±15V symmetrical power to the operational amplifier, ensuring the dynamic range of the signal processing circuitry. The hybrid switching + linear topology balances efficiency and noise performance. The TPS3851 timing controller enables soft-start to avoid inrush current, and multi-parameter monitoring and protection ensure reliable system operation.

[0100] According to one aspect of this application, the temperature sensor is an AD590 temperature sensor, whose output current is proportional to the absolute temperature;

[0101] The reference current source generates a reference current corresponding to room temperature through a precision reference voltage source and a precision resistor voltage divider network;

[0102] The instrumentation amplifier is the INA128, which features adjustable gain and high common-mode rejection ratio;

[0103] The gain setting resistor is connected between the gain control terminals of the instrumentation amplifier to set the amplification factor.

[0104] The reference voltage source is an ADR431 high-precision reference voltage source;

[0105] A low-pass filter is connected in series between the output of the instrumentation amplifier and the input of the output buffer. The low-pass filter includes a filter resistor and a filter capacitor.

[0106] The output buffer is an OPA277 operational amplifier configured as a voltage follower.

[0107] The AD590 temperature sensor, precision reference voltage source, and gain setting resistor work together to achieve linear temperature-voltage conversion across the entire temperature range, while a low-pass filter removes high-frequency noise to improve temperature measurement accuracy.

[0108] According to one aspect of this application, the timer chip is an NE555 timer;

[0109] The potentiometer is an LMP91000 potentiometer chip;

[0110] The analog switch is the ADG1419 high-precision analog switch;

[0111] The current monitoring circuit has its input terminal connected to the connection node between the current sensing resistor and the source of the MOSFET constant current source, and its output terminal connected to the monitoring input terminal of the FPGA main controller for real-time monitoring of the output current value.

[0112] The fault detection circuit is connected between the potentiometer and the three-electrode interface circuit to detect the electrode connection status and the electrochemical cell impedance.

[0113] The current monitoring circuit obtains the actual output current by detecting the voltage drop across the current sensing resistor. When the fault detection circuit detects an electrode disconnection or abnormal impedance, it sends a fault signal to the FPGA main controller. The FPGA main controller implements current closed-loop control and fault protection based on the feedback signals from the current monitoring circuit and the fault detection circuit.

[0114] According to another aspect of this application, a permanganate ion selective photoelectric coordinated transient recognition system adopts a distributed modular architecture, comprising seven core functional circuits: an FPGA timing control circuit in the main control layer, an optical detection circuit and a micro-current pulse circuit in the signal excitation layer, a lock-in amplifier circuit and a high-speed ADC acquisition circuit in the signal processing layer, a DSP processing circuit (digital signal) in the data analysis layer, and a temperature compensation circuit and a power management circuit in the auxiliary support layer. The circuit topology is as follows: the FPGA control circuit is connected to the optical detection, micro-current pulse, ADC acquisition, and lock-in amplifier circuits respectively via four control signals (LED_EN, PULSE_TRIG, ADC_SYNC, LIA_REF). The output signal of the optical detection circuit is connected in parallel to the lock-in amplifier circuit and the high-speed ADC circuit. The digital outputs of the lock-in amplifier circuit and the ADC circuit are both connected to the DSP processing circuit. The temperature compensation circuit is independently connected to the auxiliary channel of the ADC. The power management circuit provides multiple regulated power supplies for all functional circuits. The system timing control diagram is shown below. Figure 4 As shown.

[0115] In one specific embodiment of this application, an online permanganate monitoring system is provided, which is particularly suitable for real-time detection of permanganate concentration in high-salt, high-chloride seawater environments (chloride ion concentration 15000-20000 mg / L). This system is mainly used for monitoring water quality in mariculture, marine environmental protection monitoring stations, and automatic water quality monitoring at coastal industrial discharge outlets.

[0116] The system includes the following main circuits: an optical detection circuit, including a 545nm LED light source, a BPW34 photodiode, an OPA380 transimpedance amplifier, and a PGA281 programmable gain amplifier; a micro-current pulse generation circuit, including a DAC8568 digital-to-analog converter, an OPA2277 precision operational amplifier, a 2N7002 MOSFET current source, and an NE555 pulse generator; a timing synchronization control circuit, using a Xilinx Spartan-6 XC6SLX9 FPGA with a 100MHz TCXO clock source; a signal processing circuit, including an AD630 lock-in amplifier, a 4th-order Butterworth filter, and an ADS8688 high-speed ADC; a data analysis circuit, using a TMS320F28335 floating-point DSP processor; and a temperature compensation circuit, using an AD590 temperature sensor and an INA128 instrumentation amplifier.

[0117] The system is based on permanganate ions (MnO4). - The characteristic absorption peak at 545 nm wavelength is used to enhance its optical response by combining microcurrent pulse excitation. The detection process consists of three stages: Stage 1: Baseline measurement (0-20 ms), where the LED is driven by a constant current of 100 mA to generate 545 nm monochromatic light, the photodiode detects the transmitted light intensity I0, and the system records the baseline signal when there is no current excitation; Stage 2: Co-excitation (20-30 ms), where a 10 μA microcurrent pulse is applied while maintaining illumination, and permanganate ions undergo transient polarization under the action of the electric field, and the photodetector records the enhanced absorption signal I1; Stage 3: Recovery detection (30-50 ms), where the current pulse is stopped and illumination continues, and the time constant τ is obtained by monitoring the signal recovery process.

[0118] The LED driver circuit uses an LM317 constant current source design, and the output current calculation formula is I. LED = 1.25V / R1, where R1 = 12.5Ω, therefore I LED = 1.25V / 12.5Ω = 100mA. The incorrect grounding method of the LM317 in the original design was corrected; the adjustment terminal is now correctly grounded through a 12.5Ω precision resistor, ensuring the constant current source functions properly. LED power consumption P LED = 3.3V × 100mA = 330mW, using an OSRAM LG L29K 545nm LED, with a light power output of 50mW and a photoelectric conversion efficiency of 15.2%. A temperature compensation circuit was added, using an LM35 temperature sensor to detect the LED temperature, which is then conditioned by an operational amplifier and fed back to the constant current drive circuit, achieving a temperature compensation accuracy of ±0.3% / °C.

[0119] The photodiode BPW34 operates in zero-bias mode and has a responsivity of 0.62 A / W at a wavelength of 545 nm. Under typical measurement conditions, the incident light power P... in = 5mW (after 10mm optical path attenuation), photocurrent I ph = 0.62A / W × 5mW = 3.1μA. The transimpedance amplifier used is OPA380, with a gain V. out = I ph × R2 = 3.1μA × 1MΩ = 3.1V. The feedback network uses a 1MΩ feedback resistor and a 10pF feedback capacitor in parallel, with a bandwidth of 1 / (2π × R2 × C1) = 15.9kHz. The programmable gain amplifier PGA281 provides an adjustable gain of 1-128x and is controlled by the FPGA via an SPI interface. The output is fed into the ADC after passing through a low-pass filter consisting of a 1kΩ resistor and a 100nF capacitor.

[0120] The current source employs a dual feedback loop design. The main control loop consists of a DAC8568 → OPA2277 → 2N7002 MOSFET, with voltage feedback from a current sensing resistor Rs=100Ω (±0.01% accuracy) forming a closed-loop control. The DAC has a 16-bit resolution, a full-scale voltage of 5V, and a minimum resolution current I. min = (5V / 2 16 The current setting range is 1-100μA, with a step size of 0.076μA and a current accuracy of ±0.1%. The pulse timing parameters are corrected as follows: the NE555 reset terminal is correctly connected to +5V, the timing capacitor is maintained at 10nF to ensure a 10ms pulse width, and the pulse frequency is f = 1.44 / ((Ra + 2Rb) × C5) = 68.6Hz, where Ra = 10kΩ, Rb = 100kΩ, and C5 = 10nF. An analog switch ADG1419 is connected in series in the MOSFET drain output path to achieve pulse modulation.

[0121] The FPGA uses a Spartan-6 XC6SLX9, configured with 6272 logic cells, powered by a +3.3V I / O power supply and a +1.2V core power supply. The 100MHz master clock TCXO provides ±10ppm stability, timing resolution of 10ns, synchronization delay <50ns, and trigger jitter <±10ns. FPGA output ports include: a 1kHz PWM signal output to the light source driver circuit for the LED enable pin; a 10ms delayed trigger pulse output during the high level of the LED enable signal; a 1MHz sampling window signal output to the high-speed ADC for the synchronization sampling pin; and a square wave signal with the same frequency as the optical modulation output to the lock-in amplifier for the reference signal pin. Key timing parameters are set as follows: LED enable signal period 100ms, LED on-time 50ms, current pulse delay 20ms (relative to LED start), current pulse width 10ms, ADC sampling window 30ms, sampling rate 1MSPS, and 30,000 sampling points per cycle.

[0122] The AD630 lock-in amplifier employs biphase detection, operates on ±15V power, and has a phase difference of 0° and 90° between the reference signal and the signal under test. It has an integration time of 10ms, a gain of 60dB, and a time constant of 10ms. The 4th-order Butterworth filter uses a Sallen-Key cascaded topology design. Both the first and second stages use OP07 operational amplifiers with RC parameters of R5=R6=R7=R8=10kΩ, C6=C8=2.2nF, C7=C9=1.0nF, a cutoff frequency of fc=10.6kHz, a stopband attenuation of -80dB / dec, and a passband ripple of <0.1dB. The high-speed ADC uses the ADS8688, a 16-bit SAR architecture, a 1MSPS sampling rate, a ±10V input range, a +5V reference voltage, and an OPA4277 low-noise buffer and a 100Ω / 10nF anti-aliasing filter at the input.

[0123] The temperature compensation system employs a dual-current-source differential measurement architecture. The AD590 temperature sensor outputs current I... temp=(273.15 + T°C) × 1μA, outputting 298.15μA at 25°C. A reference current source generates a 298μA reference current, which is replicated through a current mirror circuit. Both currents are converted into voltage signals via 1.000kΩ precision resistors (±0.01% accuracy, 5ppm / °C temperature coefficient). The differential voltage is fed into an INA128 instrumentation amplifier with a gain of 101 (Rg=490Ω), and the reference voltage is provided by an ADR431 at +2.500V. The output provides the temperature signal after passing through a 1kΩ / 100nF low-pass filter and an OPA277 buffer. Temperature measurement range -10°C to +60°C, temperature resolution 0.1°C, accuracy ±0.5°C, output voltage range 0.5V to 3.5V, temperature coefficient 10.1mV / °C, zero-point voltage (25°C) 2.752V, linearity ±0.05% FS, noise level <0.1mVrms.

[0124] The power supply system employs a multi-stage filtering and voltage regulation design. Input protection includes a 3A fast-blow fuse, an SMBJ15A TVS transient suppressor, and a common-mode choke EMI filter. The main DC-DC converter uses an LM2596S-ADJ with a switching frequency of 150kHz, an output of +5.16V / 3A, an efficiency of 85%, and feedback resistors R9=2.4kΩ and R10=1.2kΩ. Output filtering uses a 68μH inductor (saturation current 5A) and a 1000μF low-ESR capacitor, with a 22μF ceramic capacitor and a 0.1μF decoupling capacitor in parallel, resulting in a ripple of <5mVpp. The linear post-regulator group includes AMS1117-3.3 (1A output) and AMS1117-1.2 (0.8A output) to provide digital and core power to the FPGA, with a ripple of <1mVpp. A bipolar power supply TPS65130 generates ±15V / 200mA to power the analog circuitry. The power supply timing control uses the TPS3851 to achieve programmable delay and reset management. The monitoring and protection system includes a TPS3431 four-channel voltage monitoring, an LM75 temperature monitoring (85°C threshold), an INA219 current monitoring, and multiple LED status indicators.

[0125] The system extracts three feature parameters: baseline absorbance A0 = log(I ref / I0), excited-state absorbance A1 = log(I ref / I1), the enhancement factor EF = (A1 - A0) / A0. The recovery time constant τ is obtained by fitting the recovery curve: I(t) = I1× exp(-(t-t0) / τ) + I0. The permanganate concentration is calculated using a multiple regression model: C = k1 × A0 + k2 × EF + k3 × A0 × EF + k4 × τ, where the calibration coefficients k1 = 12.5 L / (mg·cm), k2 = 8.3 L / (mg·cm), k3 = -2.1 L / (mg·cm), and k4 = 0.8 L / (mg·cm·s). The chloride ion interference compensation algorithm is EF corrected =EF × (1 + α × C Cl ), where α = -1.2 × 10 -5 L / mg. The temperature compensation algorithm is C. corrected = C measured ×[1 + β×(T-25°C)], where β = -0.02 / °C is the temperature coefficient of permanganate.

[0126] Under laboratory conditions, artificial seawater (chloride ion concentration 19000 mg / L) prepared with standard potassium permanganate solution was used for testing. The detection range was 0.1-50 mg / L, the detection limit was 0.05 mg / L (3 times the noise standard deviation), the measurement accuracy was ±1.8% (full range), the reproducibility RSD was <1.2% (n=10, 5 mg / L standard solution), the response time was 85 ms (reaching 95% stability), and the baseline drift was <0.5% / h (continuous operation for 8 hours). Anti-interference performance tests showed that the measurement errors at different chloride ion concentrations were as follows: 0 mg / L Cl - Error 0.3%, 5000mg / L Cl - Error 0.8%, 10000mg / L Cl - Error 1.2%, 19000 mg / L - Error 1.8%, 25000 mg / L Cl - The error was 2.3%. Long-term stability testing, conducted continuously for 30 days, showed a zero-point drift of <0.1 mg / L, a range drift of <2%, and a calibration period of >30 days.

[0127] This system was installed at a sea cucumber farm to monitor permanganate content in the aquaculture ponds. Water parameters included salinity of 30‰, chloride ion concentration of 18500 mg / L, temperature range of 15-28°C, and pH of 7.8-8.4. After 60 days of continuous operation, the permanganate concentration ranged from 0.5 to 8.2 mg / L, with a daily variation of ±1.5 mg / L. The correlation coefficient R was compared with the national standard method (GB 11892-1989). 2=0.996, with an average relative error of -1.82%, meeting the accuracy requirement of ±5% for online monitoring. Compared with traditional detection methods, the detection accuracy has been improved from ±5-8% to ±1.8%, the anti-interference capability has been reduced from 30% to 1.8% in a 19000 mg / L chloride ion environment, the response time has been shortened from 5-10 minutes to 85 ms, and the baseline drift has been reduced from 2-5% / h to 0.5% / h.

[0128] This embodiment utilizes photoelectric collaborative detection technology to achieve high-precision online monitoring of permanganate in high-salt and high-chloride seawater environments. The system achieves a detection accuracy of ±1.8%, a response time of 85ms, and can operate stably in environments with chloride ion concentrations as high as 25,000 mg / L, meeting the technical requirements for marine environmental monitoring.

[0129] In summary, this application integrates a 545nm optical detection circuit with a 1-100μA micro-current pulse circuit in the same spatiotemporal domain, achieving nanosecond-level hardware synchronization through precise FPGA control. Unlike traditional single-detection methods, this approach utilizes micro-current pulses to induce transient polarization of permanganate ions while simultaneously detecting their absorption changes using optical methods, forming a unique three-dimensional collaborative detection mechanism of light, electricity, and time. The FPGA achieves precise timing coordination of multiple modules through four independent control signals (LED_EN, PULSE_TRIG, ADC_SYNC, LIA_REF), achieving nanosecond-level timing accuracy between the LED enable signal, current pulse trigger signal, and ADC sampling signal. The micro-current pulse circuit employs a dual-feedback loop architecture. The main control loop consists of a voltage-controlled current source composed of DAC8568→OPA2277→2N7002 MOSFET. Voltage feedback from the detection resistor forms a current closed-loop control, and the feedback signal is sent to the FPGA for real-time monitoring and fault diagnosis. Compared to traditional single-feedback constant current sources, this system not only achieves ultra-high current accuracy of 0.1%, but also possesses real-time monitoring and adaptive adjustment capabilities. The MOSFET operates in the linear region rather than in switching mode, achieving smooth current regulation through continuous control by a precision operational amplifier, avoiding interference from switching noise on the sensitive detection circuit. The signal processing circuit employs a parallel processing architecture of an AD630 lock-in amplifier and an ADS8688 high-speed ADC, allowing the same input signal to be simultaneously fed into two processing channels. The lock-in amplifier extracts the amplitude and phase information of the steady-state response, while the high-speed ADC records the complete transient waveform change process at a sampling rate of 1 MSPS. This approach is uncommon in traditional electrochemical detection circuits, providing a rich hardware foundation for subsequent multi-dimensional feature analysis. The two signals are fused and processed in the DSP, fully utilizing the complementarity of steady-state and transient information. The analog filtering circuit uses a two-stage Sallen-Key topology cascade to form a fourth-order Butterworth filter. Compared to traditional single-stage RC filters or multi-stage RC cascades, the Sallen-Key topology offers better frequency characteristics and lower component sensitivity. Each stage uses the same RC parameters (R=10kΩ, C1=2.2nF, C2=1.0nF), achieving an ideal Butterworth response with a cutoff frequency of 10.6kHz and a stopband attenuation of -80dB / dec through precise component matching. This avoids the complexity of active filters while providing better performance than passive filters, especially in suppressing ADC aliasing and switching power supply noise. The temperature compensation circuit employs a dual current source differential measurement architecture. The AD590 sensor output current is differentially compared with a precision reference current, and converted into a differential voltage signal through matching precision resistors. Compared to traditional single-ended temperature measurement, this offers higher accuracy and better anti-interference capability, effectively eliminating the effects of power supply fluctuations, line voltage drops, and environmental electromagnetic interference.The high common-mode rejection ratio (>120dB) of the INA128 instrumentation amplifier further enhances measurement accuracy, while the ADR431 reference voltage source ensures long-term stability. The entire circuit achieves a temperature measurement accuracy of ±0.5°C. The power management circuit employs a hybrid topology of switching regulator and linear regulator, ensuring both high efficiency and ultra-low noise. The LM2596S switching regulator uses a 150kHz switching frequency, avoiding the sensitive frequency band of signal detection, and suppresses switching ripple to <5mVpp through multi-stage LC filtering. The subsequent AMS1117 linear regulator further reduces ripple to <1mVpp, providing ultra-low noise power for sensitive analog front-end circuits. The TPS65130 bipolar converter generates a symmetrical ±15V output from a single +5V input, avoiding the complexity of traditional dual-supply designs. Appropriate levels of power quality are provided based on the noise sensitivity of different module circuits. The PGA281 programmable gain amplifier in the optical detection circuit communicates with the FPGA via an SPI interface, enabling dynamic gain adjustment from 1 to 128 times. Overcoming the limitations of fixed-gain amplifiers in large dynamic range detection, this system automatically adjusts the gain based on signal strength, ensuring the ADC input is always within the optimal quantization range. Digital gain switching avoids the reliability issues of mechanical switches, and a switching time of <10μs ensures measurement continuity, providing the system with a dynamic range coverage of six orders of magnitude. In the photoelectric detection circuit, the BPW34 photodiode operates in zero-bias mode, exhibiting lower dark current and better linearity compared to traditional reverse-bias modes. The virtual short characteristic of the OPA380 transimpedance amplifier ensures the voltage across the photodiode is always zero, eliminating the influence of bias voltage on the photocurrent. The precise ratio of a 1MΩ feedback resistor to a 10pF feedback capacitor achieves optimal frequency response compensation, with a 15.9kHz bandwidth meeting system requirements while maximizing the signal-to-noise ratio. This offers significant advantages in high-precision optical detection. The timing control circuit employs a three-level nested architecture: a 100MHz TCXO provides the reference clock, the FPGA performs fine timing division, and the NE555 and ADG1419 implement pulse modulation. It guarantees nanosecond-level timing accuracy while providing the ability to generate complex pulse sequences. The FPGA's internal state machine can generate arbitrarily complex timing relationships, supporting pulse coding and modulation, providing a flexible timing control platform for optoelectronic collaborative detection. Compared with traditional single clock source designs, it offers greater flexibility and scalability. The current mirror design in the temperature compensation circuit is used to accurately replicate the AD590's output current. Precise current replication through matched MOSFETs ensures the accuracy of differential measurements. The current mirror uses a common-gate structure to improve output impedance and reduce the impact of load changes on current replication accuracy. The reference current source is generated from the regulated power supply through a precision resistor network, forming a precise differential relationship with the AD590's output current. Compared with voltage domain measurements, it offers better anti-interference capabilities and higher accuracy.

[0130] It should be noted that the various specific technical features described in the above embodiments can be combined in any suitable manner without contradiction. To avoid unnecessary repetition, this utility model will not describe the various possible combinations separately.

Claims

1. A permanganate ion selective photoelectric coordinated transient recognition system, characterized in that, include: Optical detection circuit, including light source driving circuit and photoelectric detection circuit; Microcurrent pulse circuit, used to generate controllable microcurrent pulses; The signal acquisition circuit has its input terminal connected to the output terminal of the photoelectric detection circuit. A lock-in amplifier circuit, whose signal input terminal is connected to the output terminal of a photoelectric detection circuit; The timing control circuit has a first output terminal connected to the light source driving circuit, a second output terminal connected to the micro-current pulse circuit, a third output terminal connected to the signal acquisition circuit, and a fourth output terminal connected to the reference input terminal of the lock-in amplifier circuit. The timing control circuit controls the following within the same measurement cycle: it starts the light source driving circuit for baseline detection, starts the micro-current pulse circuit for coordinated excitation while keeping the light source driving circuit working, stops the micro-current pulse circuit and continues to work the light source driving circuit for recovery detection; the signal acquisition circuit and the lock-in amplifier circuit simultaneously acquire the output signal of the photoelectric detection circuit during the coordinated excitation and recovery detection periods.

2. The system according to claim 1, characterized in that, The optical detection circuit includes: LED constant current driving circuit, including a constant current source chip, whose output terminal is connected to an LED of a predetermined wavelength; A photodiode is placed in the optical path of an LED to receive transmitted light; A transimpedance amplifier, whose inverting input is connected to the cathode of a photodiode, and whose output is connected to the inverting input through a parallel branch of a feedback resistor and a feedback capacitor; A programmable gain amplifier whose input is connected to the output of a transimpedance amplifier.

3. The system according to claim 2, characterized in that, The microcurrent pulse circuit includes: Digital-to-analog converter (DAC); A precision operational amplifier, whose non-inverting input is connected to the output of a digital-to-analog converter (DAC). The MOSFET constant current source has its gate connected to the output of a precision operational amplifier, its source grounded through a current sensing resistor, and its drain outputting a small current. The connection point between the source and the current sensing resistor is fed back to the inverting input of the precision operational amplifier to form a current closed-loop control. The pulse generator's output is connected to the control terminal of an analog switch, which is connected in series in the drain output path of the MOSFET constant current source.

4. The system according to claim 3, characterized in that, The signal acquisition circuit includes: A high-speed analog-to-digital converter, whose analog input is connected to the output of a photoelectric detection circuit, and whose sampling clock is connected to the third output of a timing control circuit; The lock-in amplifier circuit includes: A lock-in amplifier, whose signal input terminal is connected to the output terminal of a photoelectric detection circuit, and whose reference input terminal is connected to the fourth output terminal of a timing control circuit; An analog filter is connected in series between the output of the photoelectric detection circuit and the analog input of the high-speed analog-to-digital converter.

5. The system according to claim 4, characterized in that, The timing control circuit includes: The FPGA main controller is configured with a sequential state machine. A high-precision clock source is connected to the clock input of the FPGA main controller; The output ports of the FPGA main controller include: The LED enable terminal outputs a PWM signal with an adjustable duty cycle to the light source driver circuit. The current pulse trigger terminal outputs a delayed trigger pulse to the pulse generator during the high-level period of the LED enable terminal signal. The synchronous sampling terminal outputs a sampling window signal synchronized with the delayed trigger pulse to a high-speed analog-to-digital converter; The reference signal terminal outputs a square wave signal with the same frequency as the optical modulation to the lock-in amplifier.

6. The system according to claim 1, characterized in that, It also includes a temperature compensation circuit, which includes: Temperature sensor, outputting a current signal proportional to absolute temperature; A reference current source that outputs a constant reference current; The first precision resistor has one end connected to the output terminal of the temperature sensor and the other end grounded. The second precision resistor has one end connected to the output terminal of the reference current source and the other end grounded. The first and second precision resistors have the same resistance value. An instrumentation amplifier, whose non-inverting input is connected to the connection node of the first precision resistor and the output of the temperature sensor, and whose inverting input is connected to the connection node of the second precision resistor and the output of the reference current source. A reference voltage source is connected to the reference terminal of the instrumentation amplifier; The output buffer has its input connected to the output of the instrumentation amplifier and its output connected to the auxiliary channel input of the signal acquisition circuit.

7. The system according to claim 4, characterized in that, Analog filters include: The first-stage Sallen-Key filter includes a first operational amplifier, a first resistor, a second resistor, a first capacitor, and a second capacitor. One end of the first resistor is connected to the output of the photodetector circuit, and the other end is connected to the non-inverting input of the first operational amplifier and one end of the second resistor. The other end of the second resistor is connected to the output of the first operational amplifier and one end of the first capacitor. The other end of the first capacitor is connected to the non-inverting input of the first operational amplifier. The second capacitor is connected between the non-inverting input of the first operational amplifier and ground. The inverting input of the first operational amplifier is directly connected to its output. The second-stage Sallen-Key filter includes a second operational amplifier, a third resistor, a fourth resistor, a third capacitor, and a fourth capacitor. One end of the third resistor is connected to the output of the first-stage Sallen-Key filter, and the other end is connected to the non-inverting input of the second operational amplifier and one end of the fourth resistor. The other end of the fourth resistor is connected to the output of the second operational amplifier and one end of the third capacitor. The other end of the third capacitor is connected to the non-inverting input of the second operational amplifier. The fourth capacitor is connected between the non-inverting input of the second operational amplifier and ground. The inverting input of the second operational amplifier is directly connected to its output.

8. The system according to claim 3, characterized in that, The microcurrent pulse circuit also includes: The three-electrode interface circuit includes a working electrode interface, a counter electrode interface, and a reference electrode interface. A potentiometer, with its working electrode end connected to the working electrode interface, its counter electrode end connected to the counter electrode interface, its reference electrode end connected to the reference electrode interface, and its current output terminal connected to the input terminal of an analog switch.

9. The system according to claim 5, characterized in that, The pulse generator includes: The timer chip is configured in monostable mode, with its trigger terminal connected to the current pulse trigger terminal and its output terminal connected to the control terminal of the analog switch. The first timing resistor and the second timing resistor are connected in series between the power supply and the timing terminal of the timer chip; The timing capacitor is connected between the timing terminal of the timer chip and ground.

10. The system according to claim 5, characterized in that, It also includes a power management circuit, which includes: A switching regulator whose input is connected to an external power supply and whose output provides a first regulated power supply; The first linear regulator has its input connected to the first regulated power supply and its output providing a +3.3V power supply to the I / O power supply of the FPGA main controller. The second linear regulator has its input connected to the first regulated power supply and its output providing a +1.2V power supply to the core power supply terminal of the FPGA main controller. A bipolar converter has its input connected to a first regulated power supply, its positive output provides a +15V power supply, and its negative output provides a -15V power supply. The +15V and -15V power supplies provide dual power supplies for the transimpedance amplifier, the precision operational amplifier, and the lock-in amplifier. An EMI filter is connected in series between the external power supply and the input of the switching regulator. The multi-channel voltage monitor has its monitoring input terminals connected to a +3.3V power supply, a +1.2V power supply, a +15V power supply, and a -15V power supply, respectively.

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