A new semiconductor discrete device burn-in test board

By designing a novel semiconductor discrete device aging test board, which adopts a combination structure of substrate and gold finger shorting board, the problem of time-consuming and labor-intensive manual guidance in the existing technology is solved, and the device orientation is quickly guided and the operation is convenient.

CN224500827UActive Publication Date: 2026-07-14西安睿国半导体有限公司
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Patent Information

Application Number
CN202520177642.2
Authority / Receiving Office
CN · China
Patent Type
Utility models(China)
Current Assignee / Owner
Filing Date
2025-02-05
Publication Date
2026-07-14
Estimated Expiration
2035-02-05

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Abstract

The utility model belongs to the technical field of electronic component aging test, especially a new type semiconductor discrete device aging test board, including substrate, gold finger one, gold finger two, power wiring, aging test seat, fuse, shunt wiring and gold finger shorting plate, the upper end fixedly connected with gold finger one has of substrate, the bottom fixedly connected with gold finger two has of substrate, the right side fixedly connected with power wiring has of substrate, a plurality of aging test seats are fixedly connected on the substrate, the both sides of aging test seat are connected with fuse in series, the upper fixedly connected with a plurality of shunt wiring has of substrate, the upper end of shunt wiring is fixedly connected with gold finger one, the upper end plug -in combination connection has gold finger one of gold finger one, through the utility model can fast realize the physical orientation of device, can reduce the time of human adjustment replacement device direction, also can avoid the problem of unsuccessful orientation caused by human error, simple operation, convenient to use.
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Description

Technical Field

[0001] This utility model belongs to the field of electronic component aging test technology, specifically relating to a novel semiconductor discrete device aging test board. Background Technology

[0002] With the rapid development of modern electronic science and technology, electronic products are becoming increasingly sophisticated, with more detailed structures, more complex processes, and more intricate manufacturing techniques. This has created a series of hidden dangers in the production and manufacturing process. A good electronic product not only needs high performance indicators but also good stability. Currently, high-temperature aging processes are widely used both domestically and internationally to improve the reliability and stability of electronic components, especially for military electronic components, which have even higher aging requirements during testing, screening, identification, and quality consistency testing. Electronic products currently face various temperature and environmental conditions during application. Once affected by thermal expansion and contraction, the thermal matching performance of electronic components will decrease, leading to product malfunctions. The aging test of electronic components mainly aims to eliminate components that do not meet the requirements in terms of manufacturing process, durability, and critical interfaces. The aging test board used in high-temperature reverse polarization is used to eliminate non-compliant or defective electronic components, thereby improving the reliability of the components.

[0003] Current aging tests on electronic components, as well as research, analysis, and discussions on the latest equipment, reveal that the use of aging boards is currently quite cumbersome, with a limited number of components that can be screened. When aging bidirectional electronic components, aging is required in both directions, necessitating manual guidance, which is time-consuming and labor-intensive. Furthermore, during the guidance process, operational errors may lead to components that have not been repositioned flowing into the customer's market, causing potentially faulty components to malfunction at the application end, resulting in significant economic and human resource losses and unsatisfactory performance.

[0004] Based on the above, this utility model designs a novel semiconductor discrete device aging test board. Summary of the Invention

[0005] To address the aforementioned problems in the existing technology, this utility model provides a novel semiconductor discrete device aging test board that can quickly achieve physical orientation of devices, reduce the time required for manual adjustment and replacement of device orientation, and avoid the problem of unsuccessful orientation due to human error. It is simple to operate and convenient to use.

[0006] To achieve the above objectives, this utility model provides the following technical solution: a novel semiconductor discrete device aging test board, comprising a substrate, a first gold finger, a second gold finger, power wiring, an aging test socket, a fuse, branch wiring, and a gold finger shorting board, wherein the first gold finger is fixedly connected to the upper end of the substrate, and the second gold finger is fixedly connected to the bottom end of the substrate.

[0007] A power supply wiring is fixedly connected to the right side of the substrate, and the upper and lower ends of the power supply wiring are fixedly connected to gold finger one and gold finger two, respectively.

[0008] Several aging test sockets are fixedly connected to the substrate, and fuses are connected in series on both sides of each aging test socket.

[0009] The substrate is fixedly connected with several branch wirings. The upper end of the branch wirings is fixedly connected to a gold finger, and the end of the branch wirings that is different from the gold finger is fixedly connected to a fuse.

[0010] The upper end of the gold finger is connected to the gold finger.

[0011] As a preferred technical solution for a novel semiconductor discrete device aging test board according to this utility model, the substrate is a double-layer PCB board with a size of 579mm*282mm.

[0012] As a preferred technical solution for a novel semiconductor discrete device aging test board according to this utility model, both the first gold finger and the second gold finger are 100-pin gold fingers.

[0013] As a preferred technical solution of the novel semiconductor discrete device aging test board of this utility model, the number of aging test sockets is 40.

[0014] As a preferred technical solution of the novel semiconductor discrete device aging test board of this utility model, the gold finger shorting board has a size of 190mm*30mm.

[0015] Compared with the prior art, the beneficial effects of this utility model are:

[0016] This utility model mainly consists of a substrate, gold finger one, gold finger two, power wiring, aging test socket, fuse, branch wiring, and gold finger shorting board. In use, the substrate is inserted into the aging equipment chamber, and gold finger one is connected to the gold finger shorting board. After the aging time in one direction of the device is completed, the gold finger shorting board is simply removed and connected to the substrate, and gold finger one is inserted into the aging equipment chamber. This quickly achieves physical guidance of the device, reducing the time required for manual adjustment and replacement of device orientation, and also avoiding the problem of unsuccessful guidance due to human error. It is simple to operate and convenient to use. Attached Figure Description

[0017] The accompanying drawings are provided to further illustrate the present invention and form part of the specification. They are used together with the embodiments of the present invention to explain the present invention, but do not constitute a limitation thereof. In the drawings:

[0018] Figure 1 is a schematic diagram of the structure of this utility model;

[0019] Figure 2 is a schematic diagram of the gold finger shorting plate structure of this utility model.

[0020] In the diagram: 1. Substrate; 2. Gold finger one; 3. Gold finger two; 4. Power wiring; 5. Aging test socket; 6. Fuse; 7. Branch wiring; 8. Gold finger shorting board. Detailed Implementation

[0021] The technical solutions of the present utility model will be clearly and completely described below with reference to the accompanying drawings of the embodiments. Obviously, the described embodiments are only some embodiments of the present utility model, and not all embodiments. Based on the embodiments of the present utility model, all other embodiments obtained by those of ordinary skill in the art without creative effort are within the protection scope of the present utility model.

[0022] Example

[0023] Please refer to Figures 1-2. This utility model provides the following technical solution: A novel semiconductor discrete device aging test board, including a substrate 1, gold finger one 2, gold finger two 3, power wiring 4, aging test socket 5, fuse 6, branch wiring 7, and gold finger shorting board 8. The substrate 1 is a double-layer PCB board with a size of 579mm*282mm. Gold finger one 2 is fixedly connected to the upper end of the substrate 1, and gold finger two 3 is fixedly connected to the bottom end of the substrate 1. Both gold finger one 2 and gold finger two 3 are 100-pin gold fingers. Power wiring 4 is fixedly connected to the right side of the substrate 1. The upper and lower ends of the power wiring 4 are fixedly connected to gold finger one 2 and gold finger two 3, respectively.

[0024] Referring to Figure 1, further, a plurality of aging test sockets 5 are fixedly connected to the substrate 1, and the number of aging test sockets 5 is 40. Fuse 6 is connected in series on both sides of the aging test sockets 5. A plurality of branch wiring 7 are fixedly connected to the substrate 1. The upper end of the branch wiring 7 is fixedly connected to the gold finger 2, and the end of the branch wiring 7 that is different from the gold finger 2 is fixedly connected to the fuse 6.

[0025] Referring to Figures 1 and 2, further, the upper end of the gold finger 2 is connected to the gold finger 2, which has a size of 190mm*30mm.

[0026] In this embodiment, the present invention mainly consists of a substrate 1, gold fingers 1 and 2, gold fingers 2 and 3, power wiring 4, aging test socket 5, fuse 6, branch wiring 7, and gold finger shorting board 8. In use, the substrate 1 is inserted into the aging equipment housing, and gold fingers 1 and 2 are connected to the gold finger shorting board 8. After the aging time in one direction of the device is completed, the gold finger shorting board 8 is simply removed and connected to the substrate 1, and gold fingers 1 and 2 are inserted into the aging equipment housing. This quickly achieves physical guidance of the device, reducing the time required for manual adjustment and replacement of the device's orientation, and avoiding the problem of unsuccessful guidance due to human error. The operation is simple and convenient.

[0027] The key protection points of this implementation plan are the design and use of the dual gold fingers and the gold finger shorting board.

[0028] In addition, all content not described in detail in this embodiment falls within the scope of existing technology and common knowledge.

[0029] Finally, it should be noted that the above are merely preferred embodiments of this utility model and are not intended to limit the utility model. Although the utility model has been described in detail with reference to the foregoing embodiments, those skilled in the art can still modify the technical solutions described in the foregoing embodiments or make equivalent substitutions for some of the technical features. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of this utility model should be included within the protection scope of this utility model.

Claims

1. A novel semiconductor discrete device aging test board, characterized in that: It includes a substrate (1), gold finger one (2), gold finger two (3), power wiring (4), aging test socket (5), fuse (6), branch wiring (7) and gold finger shorting board (8). The upper end of the substrate (1) is fixedly connected to gold finger one (2), and the lower end of the substrate (1) is fixedly connected to gold finger two (3). The right side of the substrate (1) is fixedly connected to a power wiring (4), and the upper and lower ends of the power wiring (4) are fixedly connected to gold finger one (2) and gold finger two (3) respectively. A plurality of aging test sockets (5) are fixedly connected to the substrate (1), and fuses (6) are connected in series on both sides of the aging test sockets (5). The substrate (1) is fixedly connected with a plurality of branch wiring (7), the upper end of the branch wiring (7) is fixedly connected to the gold finger (2), and the end of the branch wiring (7) that is different from the gold finger (2) is fixedly connected to the fuse (6). The upper end of the gold finger one (2) is connected to the gold finger one (2).

2. The novel semiconductor discrete device aging test board according to claim 1, characterized in that: The substrate (1) is a double-layer PCB board with a size of 579mm*282mm.

3. The novel semiconductor discrete device aging test board according to claim 1, characterized in that: Both the first (2) and the second (3) gold fingers are 100-pin gold fingers.

4. The novel semiconductor discrete device aging test board according to claim 1, characterized in that: The number of aging test sockets (5) is 40.

5. The novel semiconductor discrete device aging test board according to claim 1, characterized in that: The dimensions of the gold finger shorting board (8) are 190mm*30mm.