A state detection unit, system and card IO module

Abstract

The utility model discloses a state detection unit, system and card formula IO module, state detection unit is applied to card formula IO module, and this card formula IO module has two signal transmission ends, and one of two signal transmission ends is as the current input of state detection unit, and the other is as the current output of state detection unit, wherein state detection unit still includes control end, PMOS pipe Q1, NMOS pipe Q2 and resistance R2, wherein control end is used to receive control signal, PMOS pipe Q1, its source electrode links with current input, drain electrode links with current output, and its grid pole connects NMOS pipe Q2's drain electrode, NMOS pipe Q2, its source stage ground connection, grid pole links with control end, resistance R2, one end links with current input, and the other end links with NMOS pipe Q2's drain electrode, can automatically realize fault isolation.

Description

Technical Field

[0001] This utility model relates to the field of electronic circuits, and more specifically, to a state detection unit, system, and card-type I / O module. Background Technology

[0002] In the field of industrial automation, the structural and functional characteristics of card-type I / O modules make them highly favored. Card-type I / O modules feature a highly compatible and scalable design, supporting mainstream bus protocols. Users can flexibly select and configure different functional modules according to their actual needs. Their flexibility and convenience are reflected in the pluggable terminal design, allowing users to easily add, remove, or replace I / O modules without complex wiring, significantly reducing maintenance costs and shortening equipment downtime. Furthermore, the easy-to-use structure of card-type I / O modules and the contact spring clip design make connecting and disconnecting wires quick and simple, eliminating the need for tools such as screwdrivers. The compact design saves installation space, and distributed control reduces wiring and construction time, further lowering installation and maintenance costs.

[0003] However, existing card-type I / O modules have significant shortcomings in fault detection and isolation. Current technologies struggle to quickly and reliably isolate faults when modules fail, as a faulty module may disrupt the entire system's operation and even affect the function of other healthy modules, leading to reduced system reliability. Furthermore, traditional methods often rely on complex wiring and diagnostic processes to detect and isolate faulty modules, which not only increases system maintenance costs but also extends equipment downtime, failing to meet the demands of modern industrial automation systems for efficient, simple, and low-cost maintenance. These problems urgently necessitate a technical solution that can effectively address fault isolation and improve system reliability. Utility Model Content

[0004] This utility model provides a status detection unit, a system, and a card-type I / O module.

[0005] A status detection unit is applied to a card-type I / O module. The card-type I / O module has two signal transmission terminals. The card-type I / O module receives a bus signal through one signal transmission terminal and outputs the bus signal through the other signal transmission terminal. One of the two signal transmission terminals serves as the current input terminal of the status detection unit, and the other serves as the current output terminal of the status detection unit. The status detection unit further includes a control terminal, a PMOS transistor Q1, an NMOS transistor Q2, and a resistor R2.

[0006] The current input terminal is used to receive voltage drive signals;

[0007] The current output terminal is used to output a voltage drive signal;

[0008] The control terminal is used to receive control signals, wherein the control signal is high level when the card-type IO module passes the self-test; and the control signal is low level when the card-type IO module fails the self-test.

[0009] The PMOS transistor Q1 has its source connected to the current input terminal, its drain connected to the current output terminal, and its gate connected to the drain of the NMOS transistor Q2.

[0010] The source of the NMOS transistor Q2 is grounded, and its gate is connected to the control terminal.

[0011] The resistor R2 has one end connected to the current input terminal and the other end connected to the drain of the NMOS transistor Q2.

[0012] in:

[0013] When the control signal is high, the NMOS transistor Q2 is turned on, pulling down the gate voltage of the PMOS transistor Q1, thus turning on the PMOS transistor Q1 and connecting the two signal transmission terminals of the card-type IO module.

[0014] When the control signal is low, the NMOS transistor Q2 is turned off and the PMOS transistor Q1 is in a high-impedance state, which disconnects the electrical connection between the two signal transmission terminals of the card-type IO module.

[0015] A card-type I / O module, comprising:

[0016] The state detection circuit described above;

[0017] The control unit is used to output a high-level control signal when the card-type I / O module passes the self-test, and to output a low-level control signal when the card-type I / O module fails the self-test.

[0018] A state detection system includes a resistor R1, a data acquisition unit, and the card-type I / O module described above; wherein:

[0019] When there is one card-type IO module, one end of the resistor R1 is connected to the power supply VCC, and the other end is connected to the current input terminal of the state detection unit. The acquisition unit is connected to the current input terminal of the state detection unit, wherein the drain of the PMOS transistor in the state detection unit is floating.

[0020] When there are at least two card-type I / O modules, the current input terminal of the status detection unit in each card-type I / O module is connected to the current output terminal of the status detection unit in the previous card-type I / O module, so that the status detection units in at least two card-type I / O modules form a cascade structure. One end of the resistor R1 is connected to the power supply VCC, and the other end is connected to the current output terminal of the first status detection unit in the cascade structure. The acquisition unit is connected to the current input terminal of the first status detection unit in the cascade structure. The drain of the PMOS transistor in the last status detection unit in the cascade structure is left floating.

[0021] The acquisition unit is used to acquire voltage signals and output the fault detection results of the card-type IO module based on the voltage signals.

[0022] This embodiment of the invention utilizes a control signal to control the conduction and cutoff of NMOS transistor Q2, thereby controlling the on / off state of PMOS transistor Q1 and effectively managing the electrical connections between modules. When the card-type I / O module passes its self-test, the signal transmission terminal is connected, and the card-type I / O module operates normally; if the self-test fails, the signal transmission terminal is disconnected, and the module is isolated. This approach not only improves system reliability but also facilitates maintenance personnel in quickly locating and handling faulty modules, reducing the impact on other modules and the overall system operation, and significantly enhancing system stability and maintainability.

[0023] Other features and advantages of this invention will be set forth in the description which follows, and will be apparent in part from the description, or may be learned by practicing the invention. The objects and other advantages of this invention can be realized and obtained by means of the structures particularly pointed out in the description and the drawings. Attached Figure Description

[0024] The accompanying drawings are provided to further illustrate the technical solution of this utility model and constitute a part of the specification. They are used together with the embodiments of this application to explain the technical solution of this utility model and do not constitute a limitation on the technical solution of this utility model.

[0025] Figure 1 This is a schematic diagram of the structure of the state detection unit provided in the embodiments of this application;

[0026] Figure 2 for Figure 1 Another structural schematic diagram of the state detection unit shown;

[0027] Figure 3 This is a schematic diagram of the structure of the card-type I / O module provided in the embodiments of this application;

[0028] Figure 4This is a first structural schematic diagram of the state detection system provided in an embodiment of this application;

[0029] Figure 5 This is a second structural schematic diagram of the state detection system provided in an embodiment of this application;

[0030] Figure 6 This is a schematic diagram of a state detection system provided in an embodiment of this application. Detailed Implementation

[0031] To make the objectives, technical solutions, and advantages of this utility model clearer, the embodiments of this utility model will be described in detail below with reference to the accompanying drawings. It should be noted that, unless otherwise specified, the embodiments and features described in this application can be arbitrarily combined with each other.

[0032] Figure 1 This is a schematic diagram of the structure of the state detection unit provided in an embodiment of this application. Figure 1 As shown, the status detection unit is applied to a card-type I / O module, which is equipped with two signal transmission terminals, one for receiving bus signals and the other for outputting bus signals. In the status detection unit, one signal transmission terminal is designated as a current input terminal for receiving voltage drive signals, and the other is designated as a current output terminal for outputting voltage drive signals.

[0033] The status detection unit also includes:

[0034] The control terminal is responsible for receiving control signals. When the card-type I / O module successfully completes its self-test, the control signal is high; if the self-test fails, the control signal is low.

[0035] PMOS transistor Q1 has its source connected to the current input terminal, its drain connected to the current output terminal, and its gate connected to the drain of NMOS transistor Q2. When NMOS transistor Q2 is turned on, the gate voltage of PMOS transistor Q1 is pulled low, thus turning on PMOS transistor Q1 and connecting the two signal transmission terminals of the card-type I / O module. When NMOS transistor Q2 is turned off, PMOS transistor Q1 is in a high-impedance state, causing the electrical connection between the two signal transmission terminals to be broken.

[0036] NMOS transistor Q2 has its source grounded and its gate connected to the control terminal. When the control signal is high, NMOS transistor Q2 is turned on; when the control signal is low, NMOS transistor Q2 is turned off.

[0037] Resistor R2 is connected at one end to the current input terminal and at the other end to the drain of NMOS transistor Q2, which is connected to the gate of PMOS transistor Q1. When NMOS transistor Q2 is turned off, it provides a pull-up voltage to the gate of PMOS transistor Q1.

[0038] Self-test passed scenario: When the card-type I / O module successfully completes its self-test, the control signal goes high. At this time, NMOS transistor Q2 turns on, and its source and drain are connected to GND, causing the gate voltage of PMOS transistor Q1 to be pulled down to near 0V. PMOS transistor Q1 then turns on, and its source and drain are connected. The voltage drive signal at the current input terminal can be normally transmitted to the current output terminal, and the two signal transmission terminals are connected. The card-type I / O module participates in signal transmission normally.

[0039] Self-test failure scenario: If the card-type I / O module fails the self-test, the control signal goes low. NMOS transistor Q2 is turned off, and the source and drain are disconnected. At this time, resistor R2 pulls the gate voltage of PMOS transistor Q1 up to the input voltage, causing PMOS transistor Q1 to turn off. The source and drain present a high impedance state, and the electrical connection between the current input terminal and the current output terminal is cut off, realizing the isolation of the faulty module and preventing it from affecting other modules in the cascaded system.

[0040] As can be seen from the above, when the card-type IO module fails, the aforementioned status detection unit can actively cut off the signal path, effectively preventing the faulty module from affecting other normal modules in the cascaded system and ensuring stable system operation.

[0041] The status detection unit itself does not directly participate in fault detection, but relies on the control signal output by the self-test circuit inside the card-type I / O module. If the self-test circuit determines that the module is malfunctioning, it outputs a low-level control signal, which triggers the status detection unit to cut off the signal path between the current input and current output terminals. Essentially, this unit is an actuator that converts the logic control signal output by the self-test circuit into the physical on / off action of the PMOS transistor, providing fundamental support for system-level fault location and handling.

[0042] Figure 2 for Figure 1 Another structural schematic diagram of the state detection unit shown. (See diagram below.) Figure 2 As shown, the state detection unit also includes at least one of resistors R3 and R4 to enhance the reliability and stability of the circuit.

[0043] Resistor R3 has one end connected to the control terminal and the other end connected to the gate of NMOS transistor Q2.

[0044] The role of resistor R3 in the state detection unit is as follows:

[0045] Limiting gate transient current: During the switching process of a MOSFET, voltage spikes can easily occur, which may damage the gate oxide layer. The presence of resistor R3 can effectively limit the gate transient current, reduce the impact of voltage spikes on the gate oxide layer, and thus protect the gate of NMOS transistor Q2.

[0046] Oscillation Suppression: High-frequency noise may interfere with the gate, causing oscillations in the circuit and affecting its stability and reliability. Resistor R3 can weaken the interference of high-frequency noise on the gate, suppress oscillations, improve the circuit's immunity to electromagnetic interference, and enable the circuit to work more stably in complex electromagnetic environments.

[0047] Electrostatic Discharge (ESD) Protection: In practical applications, ESD can damage the gate of a MOSFET. Resistor R3 acts as an ESD protection barrier, which can withstand the high voltage and large current generated by ESD to a certain extent, protecting the gate of the NMOS transistor Q2 from damage. Typically, a TVS diode is connected in parallel with the gate to further enhance the ESD protection effect.

[0048] In the exemplary embodiment described above, by introducing resistor R3, the status detection unit enhances the reliability and stability of the circuit while maintaining its original functions. Resistor R3 not only protects the gate of NMOS transistor Q2 from damage caused by excessive transient current, high-frequency noise, and electrostatic discharge, but also improves the anti-interference capability and stability of the entire status detection unit in practical applications. This allows it to better adapt to complex industrial environments and working conditions, providing a stronger guarantee for the stable operation of the card-type I / O module.

[0049] The state detection unit also includes a resistor R4, which is connected in parallel between the gate of the NMOS transistor Q2 and ground.

[0050] The functions of resistor R4 include:

[0051] Pull-down anchoring: When the control signal is low (card-type I / O module failure), NMOS transistor Q2 needs to be reliably turned off, i.e., its gate voltage is close to 0V. Resistor R4 provides a low-impedance path between the gate and ground, forcibly pulling the gate voltage of NMOS transistor Q2 low to GND. This avoids accidental turn-on due to electrostatic interference, noise, or floating state, ensuring that Q2 is absolutely turned off under a low-level control signal.

[0052] Noise interference immunity: In industrial environments, various electromagnetic interference sources exist, such as motor start-stop and relay operation. These interferences may couple to the control signal lines. Resistor R4 and the gate parasitic capacitance form a low-pass filter circuit, which can absorb high-frequency noise and prevent instantaneous interference voltage from triggering the NMOS transistor Q2 to malfunction, thereby improving the circuit's electromagnetic interference immunity.

[0053] Accelerated turn-off: When the control signal switches from high to low, the charge on the gate of NMOS transistor Q2 needs to be quickly discharged to ground to shorten the turn-off delay and improve the response speed. Resistor R4 provides a fast discharge path for the gate charge, enabling NMOS transistor Q2 to turn off quickly.

[0054] In the exemplary embodiment described above, resistor R4, acting as a gate pull-down resistor, is a crucial redundant design element ensuring that the NMOS transistor Q2 is absolutely turned off under a low-level control signal. Essentially, it provides a definite "0" level reference for the control signal, eliminating uncertainty at the hardware level. This is of great significance for improving the performance and stability of the state detection unit in practical applications.

[0055] Figure 3 This is a schematic diagram of the structure of a card-type I / O module provided in an embodiment of this application. Figure 3 As shown, the card-type I / O module includes the status detection circuit and control unit described above; wherein:

[0056] The control unit is configured to output a high-level control signal when the card-type I / O module passes the self-test, and output a low-level control signal when the card-type I / O module fails the self-test.

[0057] The self-test operation refers to the automatic detection of key functions by the card-type I / O module upon power-on or operation. These key functions include, but are not limited to, power supply, signal sampling, and communication interface, to ensure that the module's basic operating conditions and performance meet the requirements. If the self-test passes, the control unit will output a high-level control signal; if the self-test fails, it will output a low-level control signal.

[0058] When the self-test result is normal, the control unit outputs a high-level control signal, and NMOS transistor Q2 and PMOS transistor Q1 are turned on. At this time, the signal path is connected, and the signal at the current input terminal can be smoothly transmitted to the current output terminal. This module can participate in the cascaded link normally and transmit the status signal to the subsequent modules or devices.

[0059] When the self-test result indicates a fault, the control unit outputs a low-level control signal, the NMOS transistor Q2 is turned off, the PMOS transistor Q1 is turned off, the signal path is cut off, and the module will be electrically isolated from the cascaded link to prevent the fault from spreading or affecting the normal operation of other modules.

[0060] As can be seen from the working mechanism of the control unit, the control unit is responsible for detecting and judging the key functions of the card-type IO module to determine whether the card-type IO module is faulty; while the status detection circuit performs corresponding on / off operations according to the control signals output by the control unit to realize the electrical connection or isolation of the card-type IO module in normal and fault states.

[0061] When the aforementioned card-type I / O module fails, it can actively disconnect the cascade path, which can prevent the fault from spreading. For example, it can prevent short circuits from affecting adjacent modules, thereby improving the reliability and stability of the entire system.

[0062] This application provides a status detection system, including a resistor R1, a data acquisition unit, and the aforementioned card-type I / O module, which can realize automatic detection of the card-type I / O module.

[0063] Figure 4 This is a first structural schematic diagram of the state detection system provided in an embodiment of this application. Figure 4 As shown, in a single-module scenario, the system contains only one card-type I / O module. Resistor R1 is directly connected to the current input terminal of this card-type I / O module. The acquisition unit monitors the voltage at the current input terminal of this card-type I / O module, while the PMOS drain at the current output terminal of this module is floating, with no downstream modules connected. If the voltage acquired by the acquisition unit meets the condition determined based on the voltage drop value of resistor R2, it indicates that the card-type I / O module is working normally; otherwise, it indicates that the card-type I / O module has malfunctioned.

[0064] Specifically, if the card-type module passes the self-test, the equivalent circuit is R1 and R2 in series, and the voltage value Vadc = Vcc×R2 / (R1 + R2) is collected; otherwise, the current input terminal has an equivalent high resistance, and the voltage value Vadc collected is approximately equal to Vcc.

[0065] By comparing Vadc with the expected value, it can be determined whether the card-type I / O module is faulty.

[0066] Figure 5 This is a schematic diagram of the second structure of the state detection system provided in an embodiment of this application. Figure 5 As shown, when there are at least two card-type IO modules, the current input terminal of the status detection unit in each card-type IO module is connected to the current output terminal of the status detection unit in the previous card-type IO module, so that the status detection units in at least two card-type IO modules form a cascade structure. One end of the resistor R1 is connected to the power supply VCC, and the other end is connected to the current output terminal of the first status detection unit in the cascade structure. The acquisition unit is connected to the current input terminal of the first status detection unit in the cascade structure. The drain of the PMOS transistor in the last status detection unit in the cascade structure is left floating.

[0067] The acquisition unit is used to acquire voltage signals and output the fault detection results of the card-type IO module based on the voltage signals.

[0068] The working mechanism of the state detection system described above is explained below:

[0069] In a multi-module scenario, the system has multiple card-type I / O modules. The status detection units deployed in each card-type I / O module form a cascaded system, connected as follows: VCC → R1 → [Current input of status detection unit 1] → [Current output of status detection unit 1] → [Current input of status detection unit 2] → ... → [Current output of status detection unit N is left floating]. The current input of the first card-type I / O module serves as the voltage acquisition point for the cascaded link and is connected to the acquisition unit. The current inputs of subsequent modules are sequentially connected to the current outputs of the preceding modules. The drain of the PMOS transistor Q1 in the last module is left floating, where N is a positive integer.

[0070] In multi-module scenarios, fault detection methods include:

[0071] If all modules pass the self-test, a high-level control signal is output, and the PMOS transistors inside each module are turned on. At this time, the equivalent resistance of the entire cascaded link is R2 / N (N R2 transistors in parallel). According to the principle of parallel resistors and voltage division, the voltage value Vadc acquired by the acquisition unit is calculated as Vadc = Vcc * (R2 / N) / (R1 + R2 / N). When the system is running normally, the number of modules N = {(Vcc × R2) / (Vadc × R1)} - (R2 / R1) is deduced from the voltage division formula, thereby realizing automatic topology discovery and replacing manual statistics.

[0072] If the Kth card-type I / O module fails, all PMOS transistors Q1 in card-type I / O modules 1 to (K-1) will be turned on, resulting in an equivalent resistance of R2 / (K-1). When PMOS transistor Q1 in card-type I / O module K is turned off, the cascaded link is broken, and the acquired voltage value Vadc = Vcc × [R2 / (K-1)] / [R1 + R2 / (K-1)]. The change in voltage value allows us to locate the first fault point in card-type I / O module K. The location range (K value) of the faulty module can be determined by single-point voltage acquisition, eliminating the need for individual module diagnosis. For example, if Vadc corresponds to the voltage values ​​of three card-type I / O modules, the fault occurs in the fourth card-type I / O module, where K is a positive integer.

[0073] Figure 6 This is a schematic diagram of a state detection system provided in an embodiment of this application. Figure 6As shown, Vcc=3.3V, R1=3.3KΩ, control voltage Vctl=3.3V, and the resistor configuration in each state detection unit is the same, where R2=100KΩ, R3=1KΩ, R4=100KΩ, and the collected voltage value Vadc=2.833V. The calculation process for the number of card-type IO modules is as follows:

[0074] N={(Vcc*R2) / (Vadc*R1)}-(R2 / R1)={(3.3*100000) / (2.833*3300)}-(100000 / 3300)=35.3-30.3=5.

[0075] Compare the calculation results with Figure 3 As can be seen from the structure, the two are consistent.

[0076] Among them, VCC, R1, and R2 can be selected with appropriate resistance values ​​and PMOS components according to the actual application circuit to meet the usage scenario.

[0077] Optionally, at least one of the resistor R1 and the acquisition unit is deployed in the PLC.

[0078] Fault diagnosis of the card-type I / O module is completed within the card-type I / O module itself. The PLC main controller does not need to frequently poll and diagnose each module. It only needs to read the corresponding voltage value to obtain the status information of the module, thereby saving computing resources and improving the operating efficiency of the main controller.

[0079] Furthermore, by deploying resistor R1 and the acquisition unit within the PLC, a high degree of hardware integration is achieved, reducing the use of external components, simplifying the system assembly and debugging process, and improving the system's reliability and stability.

[0080] In the description of this utility model, it should be noted that the terms "upper", "lower", "one side", "the other side", "one end", "the other end", "side", "opposite", "four corners", "periphery", "'mouth' structure", etc., indicate the orientation or positional relationship based on the orientation or positional relationship shown in the accompanying drawings. They are only for the convenience of describing this utility model and simplifying the description, and do not indicate or imply that the structure referred to has a specific orientation, or is constructed and operated in a specific orientation. Therefore, they should not be construed as limitations on this utility model.

[0081] In the description of the embodiments of this utility model, unless otherwise expressly specified and limited, the terms "connection," "direct connection," "indirect connection," "fixed connection," "installation," and "assembly" should be interpreted broadly. For example, they can refer to a fixed connection, a detachable connection, or an integral connection. The terms "installation," "connection," and "fixed connection" can refer to a direct connection or an indirect connection through an intermediate medium, or they can refer to the internal communication between two components. For those skilled in the art, the specific meaning of the above terms in this utility model can be understood according to the specific circumstances.

[0082] Although the embodiments disclosed in this utility model are as described above, the content described is only for the purpose of facilitating understanding of this utility model and is not intended to limit this utility model. Any person skilled in the art to which this utility model pertains may make any modifications and changes in the form and details of the implementation without departing from the spirit and scope disclosed in this utility model, but the patent protection scope of this utility model shall still be defined by the appended claims.

Claims

1. A state detection unit, characterized in that, This is applied to a card-type I / O module, which has two signal transmission terminals. The card-type I / O module receives a bus signal through one signal transmission terminal and outputs the bus signal through the other signal transmission terminal. One of the two signal transmission terminals serves as the current input terminal of the status detection unit, and the other serves as the current output terminal of the status detection unit. The status detection unit also includes a control terminal, a PMOS transistor Q1, an NMOS transistor Q2, and a resistor R2. The current input terminal is used to receive voltage drive signals; The current output terminal is used to output a voltage drive signal; The control terminal is used to receive control signals, wherein the control signal is high level when the card-type IO module passes the self-test; and the control signal is low level when the card-type IO module fails the self-test. The PMOS transistor Q1 has its source connected to the current input terminal, its drain connected to the current output terminal, and its gate connected to the drain of the NMOS transistor Q2. The source of the NMOS transistor Q2 is grounded, and its gate is connected to the control terminal. The resistor R2 has one end connected to the current input terminal and the other end connected to the drain of the NMOS transistor Q2. in: When the control signal is high, the NMOS transistor Q2 is turned on, pulling down the gate voltage of the PMOS transistor Q1, thus turning on the PMOS transistor Q1 and connecting the two signal transmission terminals of the card-type IO module. When the control signal is low, the NMOS transistor Q2 is turned off and the PMOS transistor Q1 is in a high-impedance state, which disconnects the electrical connection between the two signal transmission terminals of the card-type IO module.

2. The state detection unit according to claim 1, characterized in that, The state detection unit further includes: Resistor R3 has one end connected to the control terminal and the other end connected to the gate of NMOS transistor Q2.

3. The state detection unit according to claim 1 or 2, characterized in that, The state detection unit further includes: Resistor R4 is connected in parallel between the gate of NMOS transistor Q2 and ground.

4. A card-type I / O module, characterized in that, include: The state detection unit as described in any one of claims 1 to 3; The control unit is used to output a high-level control signal when the card-type I / O module passes the self-test, and to output a low-level control signal when the card-type I / O module fails the self-test.

5. A state detection system, characterized in that, It includes a resistor R1, a data acquisition unit, and a card-type I / O module as described in claim 4; wherein: When there is one card-type IO module, one end of the resistor R1 is connected to the power supply VCC, and the other end is connected to the current input terminal of the state detection unit. The acquisition unit is connected to the current input terminal of the state detection unit, wherein the drain of the PMOS transistor in the state detection unit is floating. When there are at least two card-type I / O modules, the current input terminal of the status detection unit in each card-type I / O module is connected to the current output terminal of the status detection unit in the previous card-type I / O module, so that the status detection units in at least two card-type I / O modules form a cascade structure. One end of the resistor R1 is connected to the power supply VCC, and the other end is connected to the current output terminal of the first status detection unit in the cascade structure. The acquisition unit is connected to the current input terminal of the first status detection unit in the cascade structure. The drain of the PMOS transistor in the last status detection unit in the cascade structure is left floating. The acquisition unit is used to acquire voltage signals and output the fault detection results of the card-type IO module based on the voltage signals.

6. The state detection system according to claim 5, characterized in that: The number N of the card-type IO modules is determined based on the voltage value Vadc of the voltage signal, the resistor R1, and the resistor R2, where N is a positive integer; The calculation expression is as follows: .

7. The state detection system according to claim 5 or 6, characterized in that: The resistor R1 and at least one of the acquisition units are deployed in the PLC.

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