Display substrate and display device

Abstract

Provided are a display substrate and a display device, which belong to the technical field of display. The display substrate comprises a substrate, a GOA circuit located in a first region of the substrate, a plurality of COF units and a plurality of PLG wires arranged along the edge of a second region of the substrate. The plurality of PLG wires comprises a first wire group and a second wire group, one end of a first PLG wire in the first wire group and the second wire group is connected with the GOA circuit, the other end of the first PLG wire in the first wire group and the second wire group is connected with two ends in the same COF unit, or the other end of the first PLG wire in the first wire group and the other end of the first PLG wire in the second wire group are connected with different COF units. The wiring density of the first PLG wire can be reduced, and the temperature of the region can be reduced.

Description

Technical Field

[0001] This disclosure relates to the field of display technology, and in particular to a display substrate and a display device. Background Technology

[0002] To broaden the commercial and home functions of displays, high pixel density, high refresh rate, and narrow bezels are the future trends in display product development.

[0003] A display substrate exists in the related technology, which includes a substrate, a gate driver on array (GOA) circuit, multiple periphery line glass (PLG) traces, and multiple chip on film (COF) units. One end of each PLG trace is connected to the GOA circuit, and the other end is connected to the COF unit.

[0004] When space is limited for PLG traces, a large number of PLG traces are densely arranged on the substrate. When the display product is working, the PLG traces dissipate heat in a concentrated manner, causing the temperature to rise. Excessive temperature may damage the display product. Utility Model Content

[0005] This disclosure provides a display substrate and a display device that can reduce the wiring density of PLG traces on the display substrate, thereby reducing the risk of excessive temperature in the PLG trace arrangement area on the display substrate. The technical solution is as follows:

[0006] In a first aspect, embodiments of this disclosure provide a display substrate, which includes a substrate, a first GOA circuit, a plurality of COF units, and a plurality of first PLG traces. The substrate includes a display area and a peripheral area surrounding the display area. The peripheral area includes a first region and a second region connected together. The first region is arranged along a first side of the substrate, and the second region is arranged along a second side of the substrate. The first GOA circuit is located in the first region. A plurality of COF units are arranged at intervals along the second side and connected to the second region. One end of each of the plurality of first PLG traces is connected to the first GOA circuit. The plurality of first PLG traces include a first trace group and a second trace group, and the other end of a first PLG trace in the first trace group is connected to a first PLG trace in the second trace group. The other end of each line is connected to the first COF unit, and the connection point between the first PLG trace in the first trace group and the first COF unit and the connection point between the first PLG trace in the second trace group are respectively located at both ends of the side of the first COF unit closer to the display area. The first COF unit is any one of the plurality of COF units. Alternatively, the first PLG trace in the first trace group is connected to the second COF unit, and the first PLG trace in the second trace group is connected to the third COF unit. The second COF unit and the third COF unit are different COF units among the plurality of COF units.

[0007] Optionally, the first PLG trace in the first trace group includes a first trace segment, the first trace segment being located in the first region and one end connected to the first GOA circuit; the first PLG trace in the second trace group includes a second trace segment, the second trace segment being located in the first region and one end connected to the first GOA circuit; both the first trace segment and the second trace segment are located on the side of the first GOA circuit away from the display area or on the side of the first GOA circuit closer to the display area, and the first trace segment is located on the side of the second trace segment closer to the first side; or, the first trace segment is located on the side of the first GOA circuit away from the display area, and the second trace segment is located on the side of the first GOA circuit closer to the display area.

[0008] Optionally, the first PLG trace in the second trace group further includes a fourth trace segment and a sixth trace segment. One end of the fourth trace segment is connected to the other end of the second trace segment, and the other end of the fourth trace segment is connected to one end of the sixth trace segment. The sixth trace segment is located in the second region and its other end is connected to the first COF unit. Alternatively, the sixth trace segment is located in the second region and its other end is connected to the third COF unit. The portions of the first PLG trace, the second trace segment, and the sixth trace segment in the first trace group that are close to the first COF unit are all located in the first metal conductive layer of the display substrate. The fourth trace segment or the portion of the fourth trace segment that is far from the second trace segment is located in the second metal conductive layer of the display substrate. The portion of the sixth trace segment connected to the fourth trace segment is located in the second metal conductive layer.

[0009] Optionally, the first metal conductive layer is a gate layer, and the second metal conductive layer is a source / drain layer.

[0010] Optionally, the peripheral area further includes a fan-out area located between the second area and the display area, and the display substrate further includes multiple fan-out traces located in the fan-out area, the multiple fan-out traces being located in the first metal conductive layer; the orthographic projection of a portion of the fourth trace segment located in the second metal conductive layer on the substrate overlaps with the orthographic projection of a portion of the fan-out traces on the substrate.

[0011] Optionally, the first PLG trace in the first trace group further includes a third trace segment and a fifth trace segment. One end of the third trace segment is connected to the other end of the first trace segment, and the other end of the third trace segment is connected to one end of the fifth trace segment. The fifth trace segment is located in the second region and its other end is connected to the first COF unit, or the fifth trace segment is located in the second region and its other end is connected to the second COF unit. The distance between two adjacent fifth trace segments is less than the distance between the nearest fifth trace segment and a sixth trace segment. And / or, the length of the fourth trace segment is greater than the length of the third trace segment.

[0012] Optionally, the first PLG trace includes any one or more of the following signal lines: clock signal line, positive power supply voltage signal line, negative power supply voltage signal line, frame start signal line, low level signal line, and high level signal line.

[0013] Optionally, the first trace group includes only multiple clock signal lines, and the second trace group includes a first positive power supply voltage signal line, a second positive power supply voltage signal line, a first negative power supply voltage signal line, and a first frame start signal line; or, the first trace group includes a first positive power supply voltage signal line, a second positive power supply voltage signal line, a first negative power supply voltage signal line, and a first frame start signal line, and the second trace group includes only multiple clock signal lines.

[0014] Optionally, the first COF unit is the COF unit closest to the first region; the second COF unit and the third COF unit are the two COF units closest to the first region.

[0015] Optionally, the system also includes a printed circuit board connected to the side of the plurality of COF units away from the substrate.

[0016] Optionally, it further includes a second GOA circuit, the second GOA circuit and the first GOA circuit being arranged axially symmetrically about the center line of the substrate perpendicular to the second side; and a plurality of second PLG traces, the plurality of second PLG traces and the plurality of first PLG traces being arranged axially symmetrically about the center line of the substrate perpendicular to the second side.

[0017] Secondly, embodiments of this disclosure provide a display substrate, which includes a substrate, a first GOA circuit, a plurality of COF units, and a plurality of first PLG traces. The substrate includes a display area and a peripheral area surrounding the display area. The peripheral area includes a first region and a second region connected together. The first region is arranged along a first side of the substrate, and the second region is arranged along a second side of the substrate. The first GOA circuit is located in the first region. The plurality of COF units are spaced apart along the second side and connected to the second region. One end of each of the plurality of first PLG traces is connected to the first GOA circuit. The plurality of first PLG traces include a first trace group and a second trace group. The other end of the first PLG trace in the first trace group and the other end of the first PLG trace in the second trace group are both connected to the first COF units, and the first PLG trace in the first trace group is connected to the first COF unit. The connection point and the connection point of the first PLG trace in the second trace group are both located on the side of the first COF unit closer to the display area and at one end closer to the first side of the display substrate. The first COF unit is any one of the plurality of COF units. The first PLG trace in the first trace group includes a first trace segment, which is located in the first region and is connected to the first GOA circuit at one end. The first PLG trace in the second trace group includes a second trace segment, which is located in the first region and is connected to the first GOA circuit at one end. The first trace segment is located on the side of the first GOA circuit away from the display area, and the second trace segment is located on the side of the first GOA circuit closer to the display area.

[0018] Thirdly, embodiments of this disclosure provide a display substrate, which includes a substrate, a first GOA circuit, at least one COF unit, and multiple first PLG traces. The substrate includes a display area and a peripheral area surrounding the display area. The peripheral area includes a first region and a second region connected together. The first region is arranged along a first side of the substrate, and the second region is arranged along a second side of the substrate. The first GOA circuit is located in the first region. The at least one COF unit is connected to the second region.

[0019] The plurality of first PLG traces include a first trace group and a second trace group. The first PLG trace in the first trace group includes a first trace segment, a third trace segment, and a fifth trace segment connected sequentially between the first GOA circuit and the at least one COF unit. The first PLG trace in the second trace group includes a second trace segment, a fourth trace segment, and a sixth trace segment connected sequentially between the first GOA circuit and the at least one COF unit. The extension directions of the first trace segment, the second trace segment, the fifth trace segment, and the sixth trace segment are all the same as the extension direction of the first side. The distance between two adjacent first trace segments and the distance between two adjacent second trace segments are both less than the distance between the nearest first trace segment and the nearest second trace segment. And / or, the distance between two adjacent fifth trace segments and the distance between two adjacent sixth trace segments are both less than the distance between the nearest first trace segment and the nearest sixth trace segment.

[0020] Fourthly, embodiments of this disclosure also provide a display device, including any of the aforementioned display substrates.

[0021] The beneficial effects of the technical solutions provided in this disclosure include at least the following:

[0022] The first PLG trace is divided into a first PLG trace group and a second PLG trace group. The other end of the first PLG trace in the first PLG trace group is connected to the first COF unit, and the first PLG trace in the second trace group is connected to the first COF unit. The connection points of the first PLG trace in the first trace group and the first COF unit and the first PLG trace in the second trace group are respectively located at the two ends of the side of the first COF unit near the display area. This can increase the spacing between the first PLG traces in the first trace group and the first PLG traces in the second trace group near the first COF unit, reduce the wiring density of the first PLG traces in the peripheral area of ​​the display substrate, and reduce the heat dissipation temperature of the peripheral area of ​​the display substrate.

[0023] Alternatively, the first PLG trace in the first trace group can be connected to the second COF unit, and the first PLG trace in the second trace group can be connected to the third COF unit. This allows the PLG traces in the first trace group and the PLG traces in the second trace group to be distributed in two different COF units, reducing the wiring density of the first PLG traces in the peripheral area of ​​the display substrate, thereby reducing the heat dissipation temperature of the peripheral area of ​​the display substrate. At the same time, the driving power consumption of a single COF unit is reduced, thereby reducing the heat dissipation temperature of the COF unit area.

[0024] The two wiring methods described above separate the two wiring groups in terms of spatial distribution by grouping the first PLG traces. This separates the first PLG traces in the first wiring group from the first PLG traces in the second wiring group at the periphery of the display substrate, thereby reducing the wiring density of the first PLG traces in the periphery of the display substrate and thus reducing the heat dissipation temperature of the periphery of the display substrate. Attached Figure Description

[0025] To more clearly illustrate the technical solutions in the embodiments of this disclosure, the accompanying drawings used in the description of the embodiments of this disclosure will be briefly introduced below. Obviously, the accompanying drawings described below are only some embodiments of this disclosure. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0026] Figure 1 This is a schematic diagram of the structure of a display substrate based on related technologies;

[0027] Figure 2 This is a schematic diagram of the structure of a display substrate provided in an embodiment of this disclosure;

[0028] Figure 3 yes Figure 2 Enlarged view of region A2 in the middle;

[0029] Figure 4 yes Figure 2 Structural diagrams of the fourth and sixth routing segments;

[0030] Figure 5 yes Figure 4 A magnified schematic diagram of the AA section;

[0031] Figure 6 yes Figure 4 A magnified structural diagram of the BB section;

[0032] Figure 7 This is a circuit diagram showing the connection between a PLG trace and a GOA circuit according to an embodiment of this disclosure;

[0033] Figure 8 This is a schematic diagram of another display substrate structure provided in an embodiment of this disclosure;

[0034] Figure 9 This is a schematic diagram of another display substrate structure provided in an embodiment of this disclosure;

[0035] Figure 10 This is a schematic diagram of another display substrate structure provided in an embodiment of this disclosure;

[0036] Figure 11 yes Figure 10 Enlarged view of area A3 in the middle;

[0037] Figure 12 This is a schematic diagram of another display substrate provided in an embodiment of the present disclosure.

[0038] Figure Labels

[0039] Substrate 1; First region 11; Second region 12; Display area 13; Fan-out region 14;

[0040] First GOA circuit 21; Second GOA circuit 22;

[0041] First PLG wiring 3;

[0042] First wiring group 31; First wiring segment 311; Third wiring segment 312; Fifth wiring segment 313;

[0043] Second wiring group 32; Second wiring segment 321; Fourth wiring segment 322; Sixth wiring segment 323;

[0044] First child line segment 3221; Second child line segment 3222; Third child line segment 3231; Fourth child line segment 3232;

[0045] COF unit 4;

[0046] First COF unit 41; First terminal group 411; Second terminal group 412;

[0047] Second COF unit 42; Third terminal group 421;

[0048] Third COF unit 43; Fourth terminal group 431;

[0049] First metal conductive layer 51; Second metal conductive layer 52;

[0050] Printed circuit board 6;

[0051] Multiple second PLG routing lines 7; third routing group 71; fourth routing group 72. Detailed Implementation

[0052] To make the objectives, technical solutions, and advantages of this disclosure clearer, the embodiments of this disclosure will be described in further detail below with reference to the accompanying drawings.

[0053] Unless otherwise defined, the technical or scientific terms used herein shall have the ordinary meaning understood by one of ordinary skill in the art to which this disclosure pertains. The terms “first,” “second,” “third,” and similar terms used in this patent application specification and claims do not indicate any order, quantity, or importance, but are merely used to distinguish different components. Similarly, the terms “an” or “a” and similar terms do not indicate a quantity limitation, but rather indicate the presence of at least one. The terms “comprising” or “including” and similar terms mean that the element or object preceding “comprising” or “including” encompasses the element or object listed following “comprising” or “including” and its equivalents, and do not exclude other elements or objects. The terms “connected” or “linked” and similar terms are not limited to physical or mechanical connections, but can include electrical connections, whether direct or indirect. The terms “upper,” “lower,” “left,” “right,” etc., are used only to indicate relative positional relationships, and these relative positional relationships may change accordingly when the absolute position of the described object changes.

[0054] To broaden the commercial and home functionality of displays, high pixel density, high refresh rates, and narrow bezels are the future trends in display product development. The demand for high-specification products is accompanied by more complex product designs, which leads to concentrated heat dissipation in the periphery line glass (PLG) wiring convergence area during operation, resulting in higher temperatures and further causing various defects.

[0055] Figure 1 This is a schematic diagram of the structure of a display substrate based on related technologies. For example... Figure 1 As shown, the display substrate includes a substrate 1', a GOA circuit 2', multiple PLG traces 3', and multiple COF units 4'.

[0056] The substrate 1' includes a display area 13' and a peripheral area surrounding the display area 13'. The peripheral area includes a first region 11' and a second region 12' connected to each other. The first region 11' is provided with a GOA circuit 2', and the second region 12' is provided with a plurality of COF units 4'. One end of a plurality of PLG traces 3' is connected to the GOA circuit 2', and the other end is connected to the COF units 4'.

[0057] Among them, multiple PLG traces 3' are located on the same side of the GOA circuit 2', and on the side closer to the edge of the substrate 1', and multiple PLG traces 3' are connected to the connection terminal on the side closer to the display area of ​​the same COF unit.

[0058] like Figure 1As shown, the dashed box A1 area represents two consecutive corners of multiple PLG traces near the outer perimeter of the display substrate. Tests on the PLG temperature distribution revealed that the signal lines in this area are concentrated, leading to increased temperature and potential issues with reduced quality and lifespan.

[0059] Therefore, this disclosure provides a display substrate and a display device that can reduce the temperature of the peripheral area of ​​the display substrate.

[0060] The display substrate and display device provided in the embodiments of this disclosure will now be described in detail with reference to the accompanying drawings.

[0061] Figure 2 This is a schematic diagram of the structure of a display substrate provided in an embodiment of this disclosure. For example... Figure 2 As shown, the display substrate includes a substrate 1, a first GOA circuit 21, multiple COF units 4, and multiple first PLG traces 3. Figure 2 The multiple COF units 4 and multiple first PLG traces 3 are only for illustrative purposes and do not represent the quantity.

[0062] The substrate 1 includes a display area 13 and a peripheral area surrounding the display area 13. The peripheral area includes a first region 11 and a second region 12 connected to each other. The first region 11 is arranged along a first side of the substrate 1, and the second region 12 is arranged along a second side of the substrate 1.

[0063] The first GOA circuit 21 is located in the first region 11, and multiple COF units 4 are arranged at intervals along the second side and connected to the second region 12.

[0064] The multiple first PLG traces 3 include a first trace group 31 and a second trace group 32. One end of the multiple first PLG traces 3 is connected to the first GOA circuit 21. The other end of the first PLG trace in the first trace group 31 and the other end of the first PLG trace in the second trace group 32 are both connected to the first COF unit 41.

[0065] The connection between the first PLG trace in the first wiring group 31 and the first COF unit 41, and the connection between the first PLG trace in the second wiring group 32, are located at both ends of the side of the first COF unit 41 closest to the display area 13, respectively.

[0066] exist Figure 2 In the embodiment shown, the first COF unit 41 is the COF unit closest to the first side.

[0067] The first COF unit is located close to the first side, which can make the length of the first PLG trace shorter and avoid the risk of trace breakage due to excessive length of the first PLG trace.

[0068] It should be noted that in other embodiments, the first COF unit 41 can be other COF units among multiple COF units 4, such as the second COF unit closest to the first side among multiple COF units.

[0069] In this embodiment, a plurality of pixel units are arrayed in the display area 13 for displaying an image. The first region 11 may also be referred to as the GOA region, and the second region 12 may also be referred to as the bonding region. The display substrate includes a plurality of connection terminals located in the bonding region and spaced apart along the extension direction of the second side. These connection terminals are divided into multiple terminal groups, each terminal group being used to connect to a COF unit. Correspondingly, a plurality of connection terminals are also provided on the side of the COF unit that is connected to the display substrate. Figure 2 The connection terminals are not shown in the diagram.

[0070] In practice, to facilitate connection with the COF unit, all connection terminals in the bonding area are located on the same metal conductive layer of the display substrate.

[0071] Figure 3 yes Figure 2 Enlarged diagram of area A2 in the middle, combined with Figure 2 and Figure 3 The side of the first COF unit 41 connected to the display substrate includes a first terminal group 411 and a second terminal group 412. The first terminal group 411 is located on the side of the first COF unit 41 close to the first side, and the second terminal group 412 is located on the side of the first COF unit 41 away from the first side.

[0072] For example, the first terminal group 411 includes a plurality of connection terminals, and the second terminal group 412 includes a plurality of connection terminals. Figure 3 The numbers are for illustrative purposes only and do not indicate quantity.

[0073] The connection points between the first PLG trace in the first wiring group 31 and the first COF unit 41, and the connection points between the first PLG trace in the second wiring group 32 and the first COF unit 41, are located at both ends of the side of the first COF unit 41 closest to the display area 13. That is, the first PLG trace in the first wiring group 31 is connected to the connection terminal in the first terminal group 411, and the first PLG trace in the second wiring group 32 is connected to the connection terminal in the second terminal group 412.

[0074] The first PLG traces are grouped into a first trace group and a second trace group. The first PLG traces in the first trace group are connected to the first terminal group of the first COF unit, and the first PLG traces in the second trace group are connected to the second terminal group of the first COF unit. This separates the wiring of the first PLG traces in the first trace group and the first PLG traces in the second trace group on the first COF unit, thereby reducing the heat dissipation temperature of the local area on the first COF unit. At the same time, the spacing between the first PLG traces in the first trace group and the first PLG traces in the second trace group on the outer periphery of the substrate is larger, reducing the metal wiring density in this area, thereby reducing the heat dissipation temperature of the outer periphery of the display substrate.

[0075] like Figure 2 As shown, each first PLG trace in the first trace group 31 includes a first trace segment 311, a third trace segment 312, and a fifth trace segment 313. The first trace segment 311 is located in the first region 11, and one end is connected to the first GOA circuit 21. One end of the third trace segment 312 is connected to the other end of the first trace segment 311, the other end of the third trace segment 312 is connected to one end of the fifth trace segment 313, and the other end of the fifth trace segment 313 is connected to the first COF unit 41.

[0076] Each first PLG trace in the second trace group 32 includes a second trace segment 321, a fourth trace segment 322, and a sixth trace segment 323. The second trace segment 321 is located in the first region 11 and one end is connected to the first GOA circuit 21. One end of the fourth trace segment 322 is connected to the other end of the second trace segment 321, the other end of the fourth trace segment 322 is connected to one end of the sixth trace segment 323, and the other end of the sixth trace segment 323 is connected to the first COF unit 41.

[0077] In this embodiment, both the first trace segment 311 and the second trace segment 321 are located on the side of the first GOA circuit away from the display area 13.

[0078] Combined Figure 3 For example, the fifth wiring segment 313 is connected to the connection terminal in the first terminal group 411 of the first COF unit 41, and the sixth wiring segment 323 is connected to the connection terminal in the second terminal group 412 of the first COF unit 41.

[0079] For example, the first terminal group 411 is located on the side of the first COF unit 41 closer to the first side, and the second terminal group 412 is located on the side of the first COF unit 41 away from the first side.

[0080] In this embodiment of the disclosure, the length of the fourth wiring segment 322 is greater than the length of the third wiring segment 312.

[0081] By extending the fourth trace segment to a length greater than that of the third trace segment, the sixth trace segment can be connected to the second terminal group of the first COF unit.

[0082] In this embodiment, the first wiring segment 311, the fifth wiring segment 313, the second wiring segment 321 and the sixth wiring segment 323 have the same extension direction, which is the first extension direction. The extension directions of the third wiring segment 312 and the fourth wiring segment 322 both intersect with the first extension direction.

[0083] For example, the first extension direction is the extension direction of the first side.

[0084] Optionally, the third wiring segment 312 can be a straight line or a bent line, and the fourth wiring segment 322 can be a straight line or a bent line. The choice can be made according to the actual wiring space, and this embodiment does not limit this.

[0085] like Figure 3 As shown in this embodiment, the distance D4 between two adjacent first routing segments is less than or equal to the distance D5 between the nearest first routing segment and a second routing segment. The distance D6 between two adjacent second routing segments is less than or equal to the distance D5 between the nearest first routing segment and a second routing segment.

[0086] The distance D1 between two adjacent fifth routing segments is less than the distance D2 between the nearest fifth routing segment and the sixth routing segment. The distance D3 between two adjacent sixth routing segments is also less than the distance D2 between the nearest fifth routing segment and the sixth routing segment.

[0087] This allows the first PLG trace in the first trace group to be routed separately from the first PLG trace in the second trace group on the first COF unit, thereby reducing the heat dissipation temperature of local areas on the first COF unit.

[0088] Figure 4 yes Figure 2 Structural diagrams of the fourth and sixth routing segments. (Combined with...) Figure 2 and Figure 4 The portions of the first PLG trace, the second trace segment 321, and the sixth trace segment 323 in the first trace group 31 that are close to the first COF unit 41 are located in the first metal conductive layer 51 of the display substrate. Figure 4 The image only shows the locations of multiple PLG traces, not their quantity.

[0089] like Figure 4As shown, the fourth routing segment 322 includes a first sub-routing segment 3221 and a second sub-routing segment 3222. The first sub-routing segment 3221 is located on the side closer to the second routing segment 321 and connected to one end of the second routing segment 321. The other end of the first sub-routing segment 3221 is connected to the second sub-routing segment 3222. The second sub-routing segment 3222 is located on the side away from the second routing segment 321. The sixth routing segment 323 includes a third sub-routing segment 3231 and a fourth sub-routing segment 3232. One end of the third sub-routing segment 3231 is connected to the other end of the second sub-routing segment 3222. The fourth sub-routing segment 3232 is connected to the other end of the third sub-routing segment. (Further details omitted) Figure 3 and Figure 4 The second end of the fourth sub-line segment 3232 is connected to the connection terminal in the second terminal group 412 of the first COF unit 41.

[0090] Optionally, the portion of the fourth trace segment 322 that is away from the second trace segment 321 is located in the second metal conductive layer 52 of the display substrate, and the portion of the sixth trace segment 323 that is connected to the fourth trace segment 322 is located in the second metal conductive layer 52; or, the entire fourth trace segment 322 is located in the second metal conductive layer 52 of the display substrate, and the portion of the sixth trace segment 323 that is connected to the fourth trace segment 322 is located in the second metal conductive layer 52.

[0091] Figure 5 yes Figure 4 A magnified structural diagram of the AA section. (Combined with...) Figure 4 and Figure 5 The second end of the first sub-segment 3221 is connected to the first end of the second sub-segment 3222 via a via overlap. Black indicates a via at the connection point in the diagram.

[0092] For example, the first sub-segment 3221 is located in the first metal conductive layer 51, and the second sub-segment 3222 is located in the second metal conductive layer 52.

[0093] Figure 6 yes Figure 4 A magnified structural diagram of the BB section. Combined with... Figure 4 and Figure 6 The second end of the third sub-segment 3231 is connected to the first end of the fourth sub-segment 3232 by means of a via overlap.

[0094] For example, the third sub-segment 3231 is located in the second metal conductive layer 52, and the fourth sub-segment 3232 is located in the first metal conductive layer 51.

[0095] See also Figure 2 As shown, the peripheral area also includes a fan-out area 14 located between the display area 13 and the second area 12, see [link / reference]. Figure 4The display substrate also includes multiple fan-out traces 141 located in the fan-out area 14. Figure 4 The image only shows the location of multiple fan-out routing lines 141, not the number of them.

[0096] The multiple fan-out traces 141 include multiple data signal traces, etc., used to connect to the pixel units in the display area 13 and provide driving signals to the pixel units in the display area 13. In this embodiment of the present disclosure, the multiple fan-out traces 141 are located in the first metal conductive layer 51.

[0097] Optionally, the orthographic projections of the fourth trace segment 322 and the sixth trace segment 323 on the substrate 1 of the portion of the second metal conductive layer 52 overlap with the orthographic projections of the portion of the fan-out trace 141 on the substrate 1.

[0098] A portion of the fourth trace segment (i.e., the second sub-trace segment) and a portion of the sixth trace segment (i.e., the third sub-trace segment) are located in the second metal conductive layer, which avoids affecting the wiring of the fan-out traces located in the fan-out area of ​​the first metal conductive layer. The other portion of the sixth trace segment (i.e., the fourth sub-trace segment) is located in the first metal conductive layer to facilitate connection with the corresponding connection terminals in the bonding area, while ensuring that the attachment surface of the COF unit on the side connected to the display substrate is flat.

[0099] Optionally, the first metal conductive layer 51 is a gate layer, and the second metal conductive layer 52 is a source / drain layer. The first PLG traces are arranged using the existing conductive layers in the display substrate; only the conductive pattern of the corresponding conductive layer needs to be changed, without requiring additional processing steps, making it easy to implement.

[0100] In other embodiments, the first metal conductive layer 51 is a source / drain layer, and the second metal conductive layer 52 is a conductive layer other than the source / drain layer and the gate layer.

[0101] Optionally, the first metal conductive layer 51 and the second metal conductive layer 52 are isolated by an insulating layer to avoid short circuits between different metal layers, which could cause signal crosstalk.

[0102] Optionally, the first PLG trace includes any one or more of the following signal lines: clock signal line CLK, positive power supply voltage signal line VDD, negative power supply voltage signal line VSS, frame start signal line STV, low level signal line VGL, and high level signal line VGH.

[0103] Figure 7 This is a circuit diagram illustrating the connection between a PLG trace and a GOA circuit according to an embodiment of this disclosure. The first PLG trace includes the following signal lines: multiple clock signal lines CLK, positive power supply voltage signal line VDD, negative power supply voltage signal line VSS, and frame start signal line STV.

[0104] Optionally, the number of first PLG traces in the first wiring group 31 and the number of first PLG traces in the second wiring group 32 may be equal or unequal.

[0105] like Figure 7 As shown in this embodiment, the first trace group 31 includes only clock signal lines, and the second trace group 32 includes first PLG traces other than clock signal lines.

[0106] For example, the first trace group 31 includes a first clock signal line CLK1, a second clock signal line CLK2, a third clock signal line CLK3, a fourth clock signal line CLK4, a fifth clock signal line CLK5, and a sixth clock signal line CLK. The second trace group 32 includes a first positive power supply voltage signal line VDD1, a second positive power supply voltage signal line VDD2, a first negative power supply voltage signal line VSS, and a first frame start signal line STV.

[0107] In other embodiments, the first wiring group 31 may include a first positive power supply voltage signal line VDD1, a second positive power supply voltage signal line VDD2, a first negative power supply voltage signal line VSS, and a first frame start signal line STV, while the second wiring group 32 may only include multiple clock signal lines: a first clock signal line CLK1, a second clock signal line CLK2, a third clock signal line CLK3, a fourth clock signal line CLK4, a fifth clock signal line CLK5, and a sixth clock signal line CLK6.

[0108] In this embodiment, the first GOA circuit is used to implement the progressive scan driving function within the display area 13. The COF unit is used to provide driving signals to the pixel units and the GOA circuit in the display area 13.

[0109] In some examples, such as Figure 7 As shown, the first GOA circuit includes N GOA units cascaded in line scanning order, where N is the total number of rows of pixel units in the display area. There are 6 clock signal lines.

[0110] The first clock signal line CLK1 is connected to the 6(n-1)+1th GOA unit; the second clock signal line CLK2 is connected to the 6(n-1)+2th GOA unit; the third clock signal line CLK3 is connected to the 6(n-1)+3th GOA unit; the fourth clock signal line CLK4 is connected to the 6(n-1)+4th GOA unit; the fifth clock signal line CLK5 is connected to the 6(n-1)+5th GOA unit; and the sixth clock signal line CLK6 is connected to the 6(n-1)+6th GOA unit, where n = 1, 2, ..., N / 6.

[0111] like Figure 7As shown, the first positive power supply voltage signal line VDD1 is connected to each GOA unit, the second positive power supply voltage signal line VDD2 is connected to each GOA unit, and the negative power supply voltage signal line VSS is connected to each GOA unit. The frame start signal line STV is connected to the first GOA unit, the second GOA unit, and the third GOA unit.

[0112] In this embodiment of the disclosure, in order to ensure that the scanning signals in the display area are turned on line by line, adjacent clock signals need to maintain the same time difference. Placing the clock signal lines in a group ensures that the wiring of all clock signal lines is consistent, avoiding differences in signal line resistance caused by differences in the wiring of different clock signal lines, which could lead to deviations between adjacent clock signal lines.

[0113] In other embodiments, some non-clock signal lines in the first PLG routing can be grouped with clock signal lines into the same routing group.

[0114] The above example illustrates the use of a first trace group comprising six clock signal traces. In other embodiments, the number of clock signal traces may be other numbers, such as 4, 8, or 10, and this disclosure does not impose any limitations on this.

[0115] See also Figure 2 The display substrate also includes a printed circuit board 6, which is connected to the side of the plurality of COF units 4 away from the substrate.

[0116] For example, the printed circuit board 6 can be an X-direction printed circuit board (XPCB). The X direction refers to the direction parallel to the second side of the display substrate.

[0117] Optionally, such as Figure 2 As shown, the display substrate also includes a second GOA circuit 22 and multiple second PLG traces 7. The second GOA circuit 22 and the first GOA circuit 21 are arranged axially symmetrically about the substrate perpendicular to the second side. The multiple second PLG traces 7 include a third trace group 71 and a fourth trace group 72. The third trace group 71 and the first trace group 31 are arranged axially symmetrically about the substrate perpendicular to the second side. The fourth trace group 72 and the second trace group 32 are arranged axially symmetrically about the substrate perpendicular to the second side.

[0118] For medium to large-sized display substrates, the gate line load is relatively large. By arranging a first GOA circuit and multiple first PLG traces on the first side of the display substrate, and symmetrically arranging a second GOA circuit and multiple second PLG traces about the second side of the substrate perpendicular to the substrate, the first GOA circuit on the first side of the display substrate and the second GOA circuit on the opposite side can charge the gate lines connected to them to meet the required load of the gate lines.

[0119] The arrangement of the second GOA circuit 22 and the multiple second PLG traces 7 can be found in the relevant content of the first GOA circuit 21 and the multiple first PLG traces 6, and detailed descriptions are omitted here.

[0120] Figure 8 This is a schematic diagram of another display substrate provided in an embodiment of this disclosure. Figure 2 The differences in the embodiments are as follows:

[0121] First, the first trace segment 311 is located on the side of the first GOA circuit 21 away from the display area 13, and the second trace segment 321 is located on the side of the first GOA circuit 21 closer to the display area 13.

[0122] Second, the fifth wiring segment 313 is connected to the connection terminal in the first terminal group of the first COF unit 41, and the sixth wiring segment 323 is connected to the connection terminal in the second terminal group of the first COF unit 41. The first terminal group and the second terminal group are both located at the same end of the side of the first COF unit 41 near the display area 13, that is, on the left side in the figure.

[0123] By placing the first trace segment and the second trace segment on both sides of the first GOA circuit, the wiring density on both sides of the first GOA circuit can be reduced, thereby reducing the wiring density on the first side of the display substrate and thus reducing the heat dissipation temperature of the first area of ​​the display substrate.

[0124] In this embodiment, the distance between two adjacent first routing segments 311 is less than the distance between the nearest first routing segment 311 and a second routing segment 321. The distance between two adjacent second routing segments 321 is also less than the distance between the nearest first routing segment 311 and a second routing segment 321.

[0125] The distance between two adjacent fifth line segments 313 is less than or equal to the distance between the nearest fifth line segment 313 and a sixth line segment 323. The distance between two adjacent sixth line segments 323 is also less than or equal to the distance between the nearest fifth line segment 311 and a sixth line segment 323.

[0126] Figure 9 This is a schematic diagram of another display substrate provided in an embodiment of this disclosure. Figure 2 The difference in the embodiment is that the first trace segment 311 is located on the side of the first GOA circuit 21 away from the display area 13, and the second trace segment 321 is located on the side of the first GOA circuit 21 closer to the display area 13.

[0127] By placing the first and second trace segments on opposite sides of the first GOA circuit, the wiring density on both sides of the first GOA circuit can be reduced, thereby decreasing the wiring density on the first side of the display substrate and lowering the heat dissipation temperature on the first side of the display substrate. Simultaneously, the first PLG traces in the first trace group and the first PLG traces in the second trace group are separated in the region of the display substrate near the COF unit, reducing the wiring density of the first PLG traces in the peripheral area of ​​the display substrate. This reduces the wiring density in both the first region and the peripheral area of ​​the display substrate, lowering the heat dissipation temperature of the peripheral area of ​​the display substrate over a larger area.

[0128] In this embodiment, the distance between two adjacent first routing segments 311 is less than the distance between the nearest first routing segment 311 and a second routing segment 321. The distance between two adjacent second routing segments 321 is also less than the distance between the nearest first routing segment 311 and a second routing segment 321.

[0129] The distance between two adjacent fifth routing segments 313 is less than the distance between the nearest fifth routing segment 313 and a sixth routing segment 323. The distance between two adjacent sixth routing segments 323 is also less than the distance between the nearest fifth routing segment 313 and a sixth routing segment 323.

[0130] Figure 10 This is a schematic diagram of another display substrate provided in an embodiment of this disclosure. Figure 2 The difference between the embodiments is:

[0131] The first PLG trace in the first trace group 31 is connected to the second COF unit 42, and the first PLG trace in the second trace group 32 is connected to the third COF unit 43. The second COF unit 42 and the third COF unit 43 are different COF units among multiple COF units.

[0132] Connecting the first PLG trace in the first trace group to the second COF unit, and connecting the first PLG trace in the second trace group to the third COF unit, allows the PLG traces in the first trace group and the PLG traces in the second trace group to be distributed in two different COF units. This reduces the wiring density of the first PLG trace in the peripheral area of ​​the display substrate, thereby avoiding concentrated heat dissipation in this area and causing a temperature rise. At the same time, the driving power consumption of a single COF unit is reduced, thereby reducing the heat dissipation temperature of the COF unit.

[0133] Optionally, the second COF unit 42 and the third COF unit 43 are the two COF units closest to the first side.

[0134] The COF unit is located close to the first side, which can make the length of the first PLG trace shorter and avoid the risk of trace breakage due to excessive length of the first PLG trace.

[0135] Figure 11 yes Figure 10 Enlarged view of area A3 in the middle. (Combined with...) Figure 10 and Figure 11 The side of the second COF unit 42 connected to the display substrate includes a third terminal group 421 near the first side, and the side of the third COF unit 43 connected to the display substrate includes a fourth terminal group 431 near the first side.

[0136] like Figure 11 As shown, the fifth segment 313 of the first PLG trace in the first trace group 31 is connected to the third terminal group 421 of the second COF unit 42, and the sixth segment 323 of the first PLG trace in the second trace group 32 is connected to the fourth terminal group 431 of the third COF unit 43.

[0137] The fifth trace segment is connected to the connection terminal in the third terminal group, and the sixth trace segment is connected to the connection terminal in the fourth terminal group. This can shorten the length of the first PLG trace and reduce the risk of trace breakage due to excessive length of the first PLG trace.

[0138] like Figure 11 As shown, in this embodiment, the distance D4 between two adjacent first routing segments 311 is less than or equal to the distance D5 between the nearest first routing segment 311 and a second routing segment 321. The distance D6 between two adjacent second routing segments 321 is less than or equal to the distance D5 between the nearest first routing segment 311 and a second routing segment 321.

[0139] The distance D1 between two adjacent fifth routing segments 313 is less than the distance D2 between the nearest fifth routing segment 313 and a sixth routing segment 323. The distance D3 between two adjacent sixth routing segments 323 is also less than the distance D2 between the nearest fifth routing segment 313 and a sixth routing segment 323.

[0140] The distance between two adjacent fifth trace segments is less than the distance between the nearest fifth trace segment and a sixth trace segment. This allows the PLG traces in the first trace group and the PLG traces in the second trace group to be distributed in two different COF units. This reduces the wiring density of the first PLG traces in the peripheral area of ​​the display substrate, thereby reducing the heat dissipation temperature of the peripheral area of ​​the display substrate. At the same time, the driving power consumption of a single COF unit is reduced, thereby reducing the heat dissipation temperature of the COF unit area.

[0141] Figure 12This is a schematic diagram of another display substrate provided in an embodiment of this disclosure. Figure 10 The difference in the embodiment is that the first trace segment 311 is located on the side of the first GOA circuit 21 away from the display area 13, and the second trace segment 321 is located on the side of the first GOA circuit 21 closer to the display area 13.

[0142] By placing the first and second trace segments on opposite sides of the first GOA circuit, the wiring density on both sides of the first GOA circuit can be reduced, thereby decreasing the wiring density on the first side of the display substrate and lowering the heat dissipation temperature of the first region of the display substrate. Simultaneously, the first PLG traces in the first trace group and the first PLG traces in the second trace group are separated at the periphery of the display substrate, reducing the wiring density of the first PLG traces in the periphery of the display substrate. This reduces the wiring density on both the first side and the periphery of the display substrate, lowering the heat dissipation temperature of the periphery of the display substrate over a larger area.

[0143] In this embodiment, the distance between two adjacent first routing segments 311 is less than the distance between the nearest first routing segment 311 and a second routing segment 321. The distance between two adjacent second routing segments 321 is also less than the distance between the nearest first routing segment 311 and a second routing segment 321.

[0144] The distance between two adjacent fifth line segments 313 is less than the distance between the nearest fifth line segment 313 and a sixth line segment 323. The distance between two adjacent sixth line segments 323 is also less than the distance between the nearest fifth line segment 313 and a sixth line segment 323.

[0145] This disclosure also provides a display panel, which is a liquid crystal display panel or an OLED (Organic Light-Emitting Diode) display panel.

[0146] The liquid crystal display panel includes an array substrate and a color filter substrate connected to each other, and a liquid crystal layer located between the array substrate and the color filter substrate. The array substrate can be any of the aforementioned display substrates.

[0147] For OLED display panels, in addition to the aforementioned display substrate, there is also a transparent cover plate connected to the display substrate.

[0148] This disclosure also provides a display device, which includes a power supply and any of the aforementioned display substrates, wherein the power supply and the display substrates are electrically connected.

[0149] Optionally, the display device can be any product or component with display function, such as a laptop, mobile phone, tablet, television, monitor, wearable device, or navigator.

[0150] The above description is merely an optional embodiment of this disclosure and is not intended to limit this disclosure. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of this disclosure should be included within the protection scope of this disclosure.

Claims

1. A display substrate, characterized in that, include: A substrate includes a display area and a peripheral area surrounding the display area. The peripheral area includes a first region and a second region connected together. The first region is arranged along a first side of the substrate, and the second region is arranged along a second side of the substrate. The first array substrate row driving circuit is located in the first region; Multiple flip-chip thin film units are arranged at intervals along the second side and connected to the second region; Multiple edge traces of the first glass substrate, one end of which is connected to the row driving circuit of the first array substrate; The plurality of first glass substrate edge traces include a first trace group and a second trace group. The other ends of the first glass substrate edge traces in both the first and second trace groups are connected to a first flip-chip thin film unit. The connection points between the first glass substrate edge traces in the first trace group and the first flip-chip thin film unit, and between the first glass substrate edge traces in the second trace group and the first glass substrate edge traces in the second trace group, are respectively located at both ends of the side of the first flip-chip thin film unit closest to the display area. The first flip-chip thin film unit is any one of the plurality of flip-chip thin film units. Alternatively, the other end of the edge trace of the first glass substrate in the first trace group is connected to the second flip-chip thin film unit, and the other end of the edge trace of the first glass substrate in the second trace group is connected to the third flip-chip thin film unit, wherein the second flip-chip thin film unit and the third flip-chip thin film unit are different flip-chip thin film units among the plurality of flip-chip thin film units.

2. The display substrate according to claim 1, characterized in that, The first glass substrate edge trace in the first trace group includes a first trace segment, which is located in the first region and one end is connected to the row driving circuit of the first array substrate. The first glass substrate edge trace in the second trace group includes a second trace segment, which is located in the first region and one end is connected to the row drive circuit of the first array substrate. Both the first trace segment and the second trace segment are located on the side of the first array substrate row driving circuit that is far from the display area or on the side of the first array substrate row driving circuit that is close to the display area, and the first trace segment is located on the side of the second trace segment that is close to the first side. or, The first trace segment is located on the side of the first array substrate row driving circuit away from the display area, and the second trace segment is located on the side of the first array substrate row driving circuit closer to the display area.

3. The display substrate according to claim 2, characterized in that, The first glass substrate edge trace in the second trace group further includes a fourth trace segment and a sixth trace segment. One end of the fourth trace segment is connected to the other end of the second trace segment, and the other end of the fourth trace segment is connected to one end of the sixth trace segment. The sixth trace segment is located in the second region and its other end is connected to the first flip-chip thin film unit, or the sixth trace segment is located in the second region and its other end is connected to the third flip-chip thin film unit. The portions of the first glass substrate edge trace, the second trace segment, and the sixth trace segment near the first flip-chip thin film unit in the first trace group are all located in the first metal conductive layer of the display substrate. The fourth trace segment or the portion of the fourth trace segment that is away from the second trace segment is located in the second metal conductive layer of the display substrate, and the portion of the sixth trace segment that is connected to the fourth trace segment is located in the second metal conductive layer.

4. The display substrate according to claim 3, characterized in that, The first metal conductive layer is a gate layer, and the second metal conductive layer is a source / drain layer.

5. The display substrate according to claim 4, characterized in that, The peripheral area also includes a fan-out area located between the second area and the display area, and the display substrate also includes multiple fan-out traces located in the fan-out area, the multiple fan-out traces being located in the first metal conductive layer; The orthographic projection of the portion of the fourth trace located in the second metal conductive layer on the substrate overlaps with the orthographic projection of a portion of the fan-out trace on the substrate.

6. The display substrate according to claim 3, characterized in that, The first glass substrate edge trace in the first trace group further includes a third trace segment and a fifth trace segment. One end of the third trace segment is connected to the other end of the first trace segment, and the other end of the third trace segment is connected to one end of the fifth trace segment. The fifth trace segment is located in the second region and its other end is connected to the first flip-chip thin film unit, or the fifth trace segment is located in the second region and its other end is connected to the second flip-chip thin film unit. The distance between two adjacent fifth routing segments is less than the distance between the nearest fifth routing segment and a sixth routing segment; and / or, the length of the fourth routing segment is greater than the length of the third routing segment.

7. A display substrate, characterized in that, include: A substrate includes a display area and a peripheral area surrounding the display area. The peripheral area includes a first region and a second region connected together. The first region is arranged along a first side of the substrate, and the second region is arranged along a second side of the substrate. The first array substrate row driving circuit is located in the first region; Multiple flip-chip thin film units are arranged at intervals along the second side and connected to the second region; Multiple edge traces of the first glass substrate, one end of which is connected to the row driving circuit of the first array substrate; The plurality of first glass substrate edge traces include a first trace group and a second trace group. The other end of the first glass substrate edge trace in the first trace group and the other end of the first glass substrate edge trace in the second trace group are both connected to the first flip-chip thin film unit. The connection point between the first glass substrate edge trace in the first trace group and the first flip-chip thin film unit and the connection point between the first glass substrate edge trace in the second trace group are both located on the side of the first flip-chip thin film unit that is closer to the display area and on the first side of the display substrate. The first flip-chip thin film unit is any one of the plurality of flip-chip thin film units. The first glass substrate edge trace in the first trace group includes a first trace segment, which is located in the first region and has one end connected to the first array substrate row driving circuit; the first glass substrate edge trace in the second trace group includes a second trace segment, which is located in the first region and has one end connected to the first array substrate row driving circuit; the first trace segment is located on the side of the first array substrate row driving circuit away from the display area, and the second trace segment is located on the side of the first array substrate row driving circuit closer to the display area.

8. The display substrate according to any one of claims 1-7, characterized in that, The edge traces of the first glass substrate include any one or more of the following signal lines: Clock signal line, positive power supply voltage signal line, negative power supply voltage signal line, frame start signal line, low level signal line, and high level signal line.

9. The display substrate according to claim 8, characterized in that, The first trace group includes only multiple clock signal lines, and the second trace group includes a first positive power supply voltage signal line, a second positive power supply voltage signal line, a first negative power supply voltage signal line, and a first frame start signal line. Alternatively, the first trace group may include a first positive power supply voltage signal line, a second positive power supply voltage signal line, a first negative power supply voltage signal line, and a first frame start signal line, while the second trace group may only include multiple clock signal lines.

10. The display substrate according to any one of claims 1-7 and claim 9, characterized in that, The first flip-chip thin film unit is the flip-chip thin film unit closest to the first side; The second flip-chip thin film unit and the third flip-chip thin film unit are the two flip-chip thin film units closest to the first side.

11. The display substrate according to any one of claims 1-7 and claim 9, characterized in that, It also includes a printed circuit board connected to the side of the plurality of flip-chip thin film units away from the substrate.

12. The display substrate according to any one of claims 1-7 and claim 9, characterized in that, It also includes a second array substrate row driving circuit, which is arranged axially symmetrically with respect to the center line of the substrate perpendicular to the second side about the first array substrate row driving circuit. Multiple second glass substrate edge traces are arranged axially symmetrically with respect to the multiple first glass substrate edge traces about the center line of the substrate perpendicular to the second side.

13. A display device, characterized in that, Includes the display substrate as described in any one of claims 1 to 12.

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