Display panel and display device

Abstract

The display panel and the display device are disclosed, and the display panel comprises a substrate provided with a plurality of scanning signal lines, a plurality of data signal lines and a plurality of data signal connection lines on one side, the plurality of data signal lines are arranged at intervals along a first direction, and the plurality of scanning signal lines are arranged at intervals along a second direction; one end of one of the plurality of data signal connection lines is electrically connected with M data signal lines in the plurality of data signal lines, M is a natural number greater than or equal to 4, and the other end of the one of the plurality of data signal connection lines is electrically connected with a data driving circuit; the display panel comprises a plurality of sub-pixel opening regions, the plurality of sub-pixel opening regions are arranged as rows in the first direction, a pixel electrode is arranged in each sub-pixel opening region, the pixel electrode is connected with a pixel circuit, and the pixel circuits corresponding to the sub-pixel opening regions in the same row are respectively electrically connected with M scanning signal lines in the plurality of scanning signal lines; and the M scanning signal lines are located between two rows of sub-pixel opening regions adjacent in the second direction and do not overlap with the sub-pixel opening regions.

Description

Technical Field

[0001] This disclosure relates to the field of display technology, and more particularly to a display panel and display device. Background Technology

[0002] Currently, with the continuous development of display technology, the consumer market has increasingly higher requirements for display products. In the design of existing LCD (Liquid Crystal Display) panels, typically one scan signal line and one data signal line control one sub-pixel, requiring the driver chip to set up a corresponding number of data signal ports. If multiple scan signal lines are used to control different sub-pixels in a row, one data signal port can be time-multiplexed to provide data signals to multiple columns of sub-pixels, thus reducing the number of data signal ports and consequently reducing the number of driver chips required, thereby lowering the cost of display products.

[0003] However, the existing technology that uses multiple scan signal lines to connect to a row of sub-pixels causes uneven pixel display, which seriously affects the display effect of the display panel. Utility Model Content

[0004] The first aspect of this disclosure provides a display panel, including:

[0005] A substrate, on one side of which are arranged multiple scan signal lines, multiple data signal lines and multiple data signal connection lines, wherein the multiple data signal lines are arranged at intervals along a first direction and the multiple scan signal lines are arranged at intervals along a second direction, and the first direction and the second direction intersect.

[0006] One end of one of the multiple data signal connection lines is electrically connected to M of the multiple data signal lines, where M is a natural number greater than or equal to 4, and the other end of one of the multiple data signal connection lines is electrically connected to the data driving circuit.

[0007] The display panel includes multiple sub-pixel opening areas, which are arranged in rows in the first direction. The multiple rows of sub-pixel opening areas are arranged along the second direction. Pixel electrodes are disposed in the sub-pixel opening areas, and pixel circuits are connected to the pixel electrodes. The pixel circuits corresponding to the sub-pixel opening areas in the same row are electrically connected to M of the multiple scan signal lines.

[0008] The M scanning signal lines are located between two adjacent rows of the sub-pixel opening regions in the second direction, and do not overlap with the sub-pixel opening regions.

[0009] In some implementations, the sub-pixel opening regions in the same row have the same size in the second direction; and / or,

[0010] The sub-pixel opening regions in the same row have the same size in the first direction.

[0011] In some implementations, the areas of the sub-pixel opening regions in the same row are the same, or the shapes and sizes of the sub-pixel opening regions in the same row are the same.

[0012] In some embodiments, the region between two adjacent rows of sub-pixel opening regions in the second direction is a gap region;

[0013] The M scanning signal lines connected to the pixel circuit corresponding to the sub-pixel opening region in the same row are respectively located in adjacent different interval regions.

[0014] In some embodiments, the region between two adjacent rows of the sub-pixel opening regions in the second direction is a spacing region, and the substrate includes a display region and a non-display region; within the display region, the two boundaries of the spacing region in the second direction are defined by two scan signal lines, and the two scan signal lines used to define the boundaries of the spacing region are symmetrical about a first center line, which is the center line of the region where the spacing region extends along the first direction.

[0015] In some embodiments, at least two scan signal lines are provided between the two scan signal lines used to define the boundary of the interval region, and the scan signal lines between the two scan signal lines used to define the boundary of the interval region have a bent section, and the scan signal lines at both ends of the bent section extend in different directions.

[0016] In some embodiments, within the display area, the bent scan signal lines in two adjacent interval areas in the second direction are parallel to each other, and the bent scan signal lines are scan signal lines with bent segments.

[0017] In some embodiments, the pixel circuit is electrically connected to the data signal line through a first via, the gate of the pixel circuit is electrically connected to the scan signal line, and the pixel circuit is electrically connected to the pixel electrode through a second via.

[0018] The orthographic projection of the scanning signal line on the substrate does not overlap with the orthographic projections of the first via and the second via on the substrate;

[0019] The orthogonal projections of the first via, the gate, and the second via on the substrate all fall into the spacing region;

[0020] The scan signal line portion surrounds the first via, the gate, and the second via.

[0021] In some embodiments, a portion of the first via is located between the bends of two adjacent scan signal lines; and / or,

[0022] A line connecting the center points of the first via, the gate, and the second via within the same interval region is a first connecting line, and the orthographic projection of the first connecting line onto the substrate is a straight line; or...

[0023] The maximum offset angle of the orthogonal projection of the first connection line on the substrate relative to the first direction is greater than 0° and less than or equal to 60°.

[0024] In some embodiments, a first scan signal line, a second scan signal line, a third scan signal line, and a fourth scan signal line are provided within the same interval region, wherein the second scan signal line and the third scan signal line are located between the first scan signal line and the fourth scan signal line, the first scan signal line, the fourth scan signal line, and the data signal line are used to define the sub-pixel opening region, and the first scan signal line and the fourth scan signal line are used to form the boundary of the interval region in the second direction;

[0025] The second scan signal line and the third scan signal line have the bent section.

[0026] In some embodiments, the interval regions on both sides of the sub-pixel aperture region in the second direction are respectively a first interval region and a second interval region, and the pixel circuits corresponding to the sub-pixel aperture regions in a row are respectively electrically connected to two scan signal lines of the first interval region and two scan signal lines of the second interval region; and / or,

[0027] The first scan signal line and the fourth scan signal line within the same interval region are parallel to each other; and / or,

[0028] The second scan signal line and the third scan signal line within the same interval region are parallel to each other.

[0029] In some embodiments, the first via, the gate, and the second via corresponding to a portion of the pixel circuit are all located between the third scan signal line and the fourth scan signal line; and / or,

[0030] The first via, the gate, and the second via corresponding to a portion of the pixel circuit are all located between the first scan signal line and the second scan signal line; and / or,

[0031] Multiple sub-pixel opening regions are arranged in columns along the second direction, and multiple columns of sub-pixel opening regions are arranged along the first direction. Second vias in the same column are equidistant from the first scan signal line, and second vias in the same column are equidistant from the fourth scan signal line; and / or,

[0032] The first vias in the same column are arranged in a straight line; and / or,

[0033] The second vias in the same column are arranged in a straight line; and / or,

[0034] The gates in the same column are arranged in a straight line; and / or,

[0035] The first vias in the same row are arranged in a straight line; and / or,

[0036] The second vias in the same row are arranged in a straight line.

[0037] In some implementations, the plurality of sub-pixel opening regions are divided into a plurality of first repeating units;

[0038] The interval regions on both sides of the sub-pixel opening region in the second direction are respectively the first interval region and the second interval region;

[0039] In the direction from the first interval region to the second interval region, the eleventh sub-scan signal line, the twelfth sub-scan signal line, the thirteenth sub-scan signal line and the fourteenth sub-scan signal line are arranged sequentially in the first interval region, and the twenty-first sub-scan signal line, the twenty-second sub-scan signal line, the twenty-third sub-scan signal line and the twenty-fourth sub-scan signal line are arranged sequentially in the second interval region.

[0040] The plurality of pixel circuits corresponding to the first repeating unit are electrically connected to the thirteenth sub-scan signal line, the fourteenth sub-scan signal line, the twenty-first sub-scan signal line, and the twenty-second sub-scan signal line, respectively.

[0041] In some embodiments, the first repeating unit includes a first sub-pixel opening region, a second sub-pixel opening region, a third sub-pixel opening region and a fourth sub-pixel opening region arranged sequentially in the first direction. The pixel circuit corresponding to the first sub-pixel opening region is a first pixel circuit, the pixel circuit corresponding to the second sub-pixel opening region is a second pixel circuit, the pixel circuit corresponding to the third sub-pixel opening region is a third pixel circuit, and the pixel circuit corresponding to the fourth sub-pixel opening region is a fourth pixel circuit.

[0042] The first pixel circuit is electrically connected to the thirteenth sub-scan signal line, the second pixel circuit is electrically connected to the twenty-second sub-scan signal line, the third pixel circuit is electrically connected to the fourteenth sub-scan signal line, and the fourth pixel circuit is electrically connected to the twenty-first sub-scan signal line.

[0043] In some implementations, the second scan signal line and the third scan signal line each have eight bends, with the boundary of a first repeating unit in the first direction as the boundary. The bends are close to the boundaries of two adjacent sub-pixel opening regions in the first direction.

[0044] In some embodiments, the first repeating unit includes a first sub-pixel opening region, a second sub-pixel opening region, a third sub-pixel opening region and a fourth sub-pixel opening region arranged sequentially in the first direction. The pixel circuit corresponding to the first sub-pixel opening region is a first pixel circuit, the pixel circuit corresponding to the second sub-pixel opening region is a second pixel circuit, the pixel circuit corresponding to the third sub-pixel opening region is a third pixel circuit, and the pixel circuit corresponding to the fourth sub-pixel opening region is a fourth pixel circuit.

[0045] The first pixel circuit is electrically connected to the 22nd sub-scan signal line, the second pixel circuit is electrically connected to the 21st sub-scan signal line, the third pixel circuit is electrically connected to the 13th sub-scan signal line, and the fourth pixel circuit is electrically connected to the 14th sub-scan signal line.

[0046] In some embodiments, the second scan signal line and the third scan signal line each have four bends, with the boundary of the first repeating unit in the first direction as the limit. Some of the bends are close to the boundaries of the second sub-pixel opening region and the third sub-pixel opening region adjacent in the first direction, and some of the bends are close to the boundaries of the first sub-pixel opening region and the fourth sub-pixel opening region adjacent in the first direction.

[0047] In some embodiments, the first repeating unit includes eight sub-pixel opening regions arranged sequentially in the first direction, each corresponding to one of eight pixel circuits. The pixel circuits corresponding to the eight sub-pixel opening regions are sequentially electrically connected to the twentieth sub-scan signal line, the twentieth sub-scan signal line, the fourteenth sub-scan signal line, the fourteenth sub-scan signal line, the twentieth sub-scan signal line, the twentieth sub-scan signal line, the twentieth sub-scan signal line, the twentieth sub-scan signal line, the thirteenth sub-scan signal line, and the thirteenth sub-scan signal line.

[0048] or,

[0049] The first repeating unit includes 12 sub-pixel opening regions arranged sequentially in the first direction, each corresponding to one of the 12 pixel circuits. The pixel circuits corresponding to the 12 sub-pixel opening regions are sequentially electrically connected to the 22nd sub-scan signal line, the 22nd sub-scan signal line, the 22nd sub-scan signal line, the 14th sub-scan signal line, the 14th sub-scan signal line, the 14th sub-scan signal line, the 21st sub-scan signal line, the 21st sub-scan signal line, the 21st sub-scan signal line, the 13th sub-scan signal line, the 13th sub-scan signal line, and the 13th sub-scan signal line.

[0050] or,

[0051] The first repeating unit includes 16 sub-pixel opening regions arranged sequentially in the first direction, each corresponding to a pixel circuit. The pixel circuits corresponding to the 16 sub-pixel opening regions are sequentially electrically connected to the 22nd sub-scan signal line, ...

[0052] In some embodiments, the second scan signal line and the third scan signal line each have eight bends, with the boundary of the first repeating unit in the first direction as the boundary.

[0053] In some implementations, the sub-pixel opening region corresponds to sub-pixels of three colors;

[0054] The plurality of sub-pixel opening regions are divided into a plurality of second repeating units, and the second repeating unit includes N sub-pixel opening regions;

[0055] The first repeating unit includes K sub-pixel opening regions, where N is the least common multiple of 3 and K;

[0056] The number of scan signal lines connected to the first repeating unit is M;

[0057] The number of data signal connection lines connected to the second repeating unit is N÷M;

[0058] Among them, M, N and K are all greater than 1.

[0059] A second aspect of this disclosure provides a display device, comprising:

[0060] The display panel as described in the first aspect.

[0061] The display panel is arranged between adjacent sub-pixel opening areas in the second direction via scanning signal lines. The pixel circuits corresponding to the sub-pixel opening areas in the same row are electrically connected to M scanning signal lines among the multiple scanning signal lines. Since the scanning signal lines do not overlap with the sub-pixel opening areas, the sub-pixel opening areas are not divided by the scanning signal lines. Each sub-pixel opening area can be considered as the opening of a complete sub-pixel. That is, the scanning signal lines do not cross over the sub-pixel openings, which can reduce the differences in sub-pixel opening areas caused by the scanning signal lines crossing and dividing the sub-pixel opening areas. This can reduce the problem of uneven brightness between different sub-pixels and eliminate the bright and dark stripe defects caused by the scanning signal lines dividing the sub-pixel openings. Therefore, the display panel provided in this embodiment can realize time-division multiplexing of data signal connection lines to reduce costs and improve display effects. Attached Figure Description

[0062] Figure 1 A schematic partial structural diagram of a display panel provided in an embodiment of this disclosure;

[0063] Figure 2 for Figure 1 A schematic cross-sectional view along A1-A2;

[0064] Figure 3 for Figure 1 Another schematic cross-sectional view along A1-A2;

[0065] Figure 4 for Figure 1 Another schematic sectional view along A1-A2;

[0066] Figure 5 A schematic structural diagram of a display panel provided in an embodiment of this disclosure;

[0067] Figure 6 A schematic partial structural diagram of another display panel provided in an embodiment of this disclosure;

[0068] Figure 7 A schematic partial structural diagram of another display panel provided in an embodiment of this disclosure;

[0069] Figure 8 A schematic partial structural diagram of another display panel provided in an embodiment of this disclosure;

[0070] Figure 9A schematic partial structural diagram of a display panel provided in an embodiment of this disclosure;

[0071] Figure 10 This is a schematic structural diagram of a display device provided in an embodiment of the present disclosure. Detailed Implementation

[0072] To better understand the technical solutions provided in the embodiments of this specification, the technical solutions of the embodiments of this specification will be described in detail below with reference to the accompanying drawings and specific embodiments. It should be understood that the embodiments of this specification and the specific features in the embodiments are detailed descriptions of the technical solutions of the embodiments of this specification, rather than limitations on the technical solutions of this specification. In the absence of conflict, the embodiments of this specification and the technical features in the embodiments can be combined with each other.

[0073] In this document, relational terms such as "first" and "second" are used merely to distinguish one entity or operation from another, without necessarily requiring or implying any such actual relationship or order between these entities or operations. Furthermore, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or apparatus. Without further limitation, an element defined by the phrase "comprising one..." does not exclude the presence of other identical elements in the process, method, article, or apparatus that includes said element. The term "two or more" includes two or more cases.

[0074] Currently, with the continuous development of display technology, the consumer market has increasingly higher requirements for display products. In existing LCD designs, typically one scan signal line and one data signal line control one sub-pixel, requiring the driver chip to have a corresponding number of data signal ports. For example, for a display screen with m rows × n columns of pixels, there are m rows of scan signal lines and n columns of data signal lines. The n columns of data signal lines require n data signal ports to control the electrical signal input. If two scan signal lines are used to control the odd and even columns of a row of sub-pixels respectively, then one column of data signal lines can control two columns of sub-pixels in a time-division multiplexing manner. This means that by doubling the number of scan signal lines driving a row of sub-pixels, the number of data signal lines can be halved. This halves the number of data signal ports required, and consequently, the number of driver chips needed for a display screen, leading to lower costs. Therefore, using multiple scan signal lines to control different sub-pixels within a row allows one data signal port to be time-division multiplexed to provide data signals to multiple columns of sub-pixels, reducing the number of data signal ports and thus the number of driver chips used, thereby lowering the cost of display products.

[0075] However, existing technologies that use multiple scan signal lines to connect a row of sub-pixels can spatially divide pixel openings into uneven sizes. Alternatively, the scan signal lines may obstruct parts of the pixel openings, for example, some scan signal lines may cross over the sub-pixel openings. This results in inconsistent shapes or areas of different sub-pixel openings, leading to differences in sub-pixel brightness. This can easily create stripes of varying brightness, causing uneven display and severely impacting the display panel's performance. For instance, with a display panel alignment deviation of 2μm and a liquid crystal alignment deviation of 0.4°, the light efficiency difference among the four pixel types is 7%.

[0076] Figure 1 A schematic partial structural diagram of a display panel provided in an embodiment of this disclosure; Figure 2 for Figure 1 A schematic cross-sectional view along A1-A2.

[0077] A first aspect of this disclosure is to provide a display panel, exemplary, with reference to Figure 1 and Figure 2The display panel includes a substrate 100 and a first conductive layer 200, a semiconductor layer 300, a second conductive layer 400, a third conductive layer 500, and a fourth conductive layer 600 sequentially disposed on one side of the substrate 100. An insulating layer is disposed between each conductive layer and between each conductive layer and the semiconductor layer. The first conductive layer 200 may be provided with a light-shielding structure 210, multiple scan signal lines 220, and multiple data signal lines 230. The light-shielding structure 210 is used to block backlight from the side of the substrate 100 away from the semiconductor layer 300, thereby preventing the backlight from affecting the electron mobility of the semiconductor channel. Semiconductor layer 300 may have semiconductor structure 310; second conductive layer 400 may have first electrode 410, second electrode 420, and gate 430. Both first electrode 410 and second electrode 420 are electrically connected to semiconductor structure 310. Scan signal line 220 is used to electrically connect to scan driving circuit and gate 430. First electrode 410, second electrode 420, semiconductor structure 310, and gate 430 can be used to form a thin-film transistor. First electrode 410 can be one of the source and drain of the thin-film transistor, and second electrode 420 can be the other of the source and drain. Second electrode 420 is electrically connected to data signal line 230 through first via 401, which is a through-hole penetrating the insulating layer between second conductive layer 400 and first conductive layer 200. Third conductive layer 500 may have common electrode 510. The fourth conductive layer 600 may be provided with a pixel electrode 610 and a pixel electrode connection structure 620. The pixel electrode 610 and the pixel electrode connection structure 620 may be an integral structure. The pixel electrode connection structure 620 is electrically connected to the first electrode 410 through a second via 601. The pixel electrode connection structure 620 is partially filled in the second via 601, that is, the pixel electrode 610 and the first electrode 410 are electrically connected through the second via 601. The second via 601 is a through-hole that penetrates the insulating layer between the fourth conductive layer 600 and the second conductive layer 400. The scan signal line 220 transmits a scan signal to the gate 430, which can drive the thin film transistor to turn on and off. When the thin film transistor is on, the data signal transmitted by the data signal line 230 is transmitted from the second electrode 420 through the semiconductor structure 310 to the first electrode 410. The first electrode 410 transmits the data signal to the pixel electrode 610. The data signal on the pixel electrode 610 and the common signal on the common electrode 510 can form a driving electric field. The driving electric field can drive the rotation of the liquid crystal molecules, thereby controlling the transmittance of the liquid crystal and controlling the amount of light emitted to achieve image display.

[0078] It should be noted that, Figure 2 This only illustrates the structure of a display panel, such as Figure 2As shown, the first conductive layer 200 is typically made of metal, which provides good light shielding and allows for the fabrication of signal lines within the same layer, increasing wiring space. The light shielding structure 210, data signal line 230, and scan signal line 220 are all disposed on the first conductive layer 200, and fabrication within the same layer can save fabrication steps.

[0079] refer to Figure 2 The gate 430, the first electrode 410, and the second electrode 420 are all disposed in the second conductive layer 400, that is, the gate 430 is disposed in the same layer as the source and drain electrodes.

[0080] It should be noted that, Figure 2 The driving transistor shown is a top-gate structure, meaning the gate 430 is located on the side of the semiconductor layer 300 away from the substrate 100. In other examples, the thin-film transistor can also be a bottom-gate structure, where the gate is located between the substrate and the semiconductor structure. The thin-film transistor can also be a dual-gate structure, where gates are located on both sides of the semiconductor structure in the thickness direction. If the scan signal line 220 is on a different layer than the gate 430, then a via in the insulating layer is required to connect the scan signal line 220 to the gate 430.

[0081] Figure 3 for Figure 1 Another schematic cross-sectional view along A1-A2.

[0082] refer to Figure 3 The scan signal line 220 is disposed in the second conductive layer 400, and the scan signal line 220 is disposed in the same layer as the first electrode 410, the second electrode 420 and the gate 430. Figure 3 The pixel electrode connection structure 620 shown is filled in the second via 601 and directly connected to the semiconductor structure 310. That is, the second via 601 is used to expose part of the upper surface of the semiconductor structure 310, so the pixel electrode connection structure 620 can be used as the first electrode 410.

[0083] Figure 4 for Figure 1 Another schematic sectional view along A1-A2.

[0084] refer to Figure 4 The third via 402 penetrates the insulating layer on the side of the semiconductor layer 300 away from the substrate 100. Therefore, the connection between the second electrode 420 and the semiconductor structure 310 is not achieved through the second conductive layer 400. Instead, conductive material is filled into the third via 402, and the connection between the conductive material and the semiconductor structure 310 is achieved through the third via 402, resulting in the second electrode 420. The connection between the second electrode 420 and the data signal line 230 is achieved through the connection between the first via 401 and the third via 402. In other words, the second via 601 exposes a portion of the upper surface of the semiconductor structure 310, so the pixel electrode connection structure 620 can share the same first electrode 410.

[0085] Figure 5 This is a schematic structural diagram of a display panel provided in an embodiment of the present disclosure.

[0086] For example, refer to Figure 5 The display panel may include a pixel scanning circuit 101, a scan driving circuit 102, multiple scan signal lines 220, multiple data signal lines 230, and multiple data signal connection lines 240. The multiple scan signal lines 220 are arranged along a second direction Y, and the multiple data signal lines 230 are arranged along a first direction X, where the first direction X intersects the second direction Y. The scan driving circuit 102 may include multiple thin-film transistors and may include a register circuit. The pixel circuit may include one or more thin-film transistors. The pixel circuit 101 and the scan driving circuit 102 are electrically connected via the scan signal lines 220. The scan driving circuit 102 provides scan signals to the pixel circuit 101. One end of the data signal line 230 is electrically connected to the driving transistor in the pixel circuit 101. The driving transistor is electrically connected to the pixel circuit, and its gate may be electrically connected to the scan signal line or to other components in the pixel circuit. The other end of data signal line 230 is electrically connected to data signal connection line 240, which is used to electrically connect to data driving circuit 103. Data driving circuit 103 can be integrated onto the display panel using thin-film technology. Data driving circuit 103 can also be a driver chip, which can be bonded to the display panel using a bonding process.

[0087] refer to Figure 5 The scan drive circuit 102 and the data drive circuit 103 are connected by some signal lines, such as clock signal lines, power signal lines and frame start signal lines. Figure 5 The scanning drive circuit shown is a dual-sided drive mode distribution, but it can also be a single-sided drive.

[0088] refer to Figure 5One end of one of the multiple data signal connection lines 240 is electrically connected to M of the multiple data signal lines 230, where M is a natural number greater than or equal to 4. The other end of one of the multiple data signal connection lines 240 is used to electrically connect to the data driving circuit 103. One data signal connection line 240 corresponds to multiple data signal lines 230. The data signal lines 230 are arranged along the first direction X, and the scan signal lines 220 are arranged along the second direction Y. The pixel circuits 101 are arranged in an array along the first direction X and the second direction Y. A row of pixel circuits 101 arranged along the first direction X constitutes a row, which can produce multiple columns in the first direction X. A row of pixel circuits 101 arranged along the second direction Y constitutes a column, which can produce multiple rows in the second direction Y. That is, the multi-row pixel circuits 101 are arranged along the second direction Y, and the multi-column pixel circuits 101 are arranged along the first direction X. The first direction X can be regarded as the row direction, and the second direction Y as the column direction.

[0089] It should be noted that the data signal connection line 240 can be set on the same layer as the data signal line 230 or on a different layer, which can be adjusted according to the wiring design.

[0090] refer to Figure 5 Each row of pixel circuit 101 corresponds to 4 scan signal lines 220, and 4 data signal lines 230 are connected to 1 data signal connection line 240. Figure 5 This is merely illustrative and not intended to limit the scope of this disclosure.

[0091] refer to Figure 1 and Figure 2 The first conductive layer 200 and the second conductive layer 400 can be made of metallic materials, and can be a single layer of metal or a stack of multiple metals. For example, a single conductive layer can be a single layer of molybdenum, or a stack of molybdenum-aluminum-molybdenum, or a stack of titanium-aluminum-titanium. Exemplarily, the third conductive layer 500 and the fourth conductive layer 600 can be made of transparent conductive materials, such as indium tin oxide. Metallic conductive layers have lower light transmittance, while indium tin oxide has higher light transmittance.

[0092] refer to Figure 1 The display panel includes multiple subpixel opening regions 700, one of which is shown in shadow. Figure 5Four sub-pixel opening regions 700 are shown, arranged along a first direction X. The data signal lines 230 and 220 can be made of metallic material, thus providing good light-shielding. Each sub-pixel opening region 700 can be a single area enclosed by the intersection of the data signal lines 230 and 220. The pixel electrode 610 can be disposed within the sub-pixel opening region 700. The pixel electrode 610 has good light transmittance and can be configured as a comb-like structure, minimizing light obstruction. The pixel electrode connection structure 620 can be disposed outside the sub-pixel opening region 700.

[0093] refer to Figure 1 and Figure 5 Multiple sub-pixel opening regions 700 are arranged in rows along the first direction X, and multiple rows of sub-pixel opening regions 700 are arranged along the second direction Y. Pixel electrodes 610 are disposed within each sub-pixel opening region 700, and pixel circuits are connected to the pixel electrodes 610. The pixel circuits corresponding to the sub-pixel opening regions 700 in the same row are electrically connected to M scan signal lines 220 among multiple scan signal lines 220. (Refer to...) Figure 1 M is set to 4; four scanning signal lines 220 are provided between two adjacent rows of sub-pixel opening regions 700 in the second direction Y, and the scanning signal lines 220 do not overlap with the sub-pixel opening regions 700.

[0094] For example, refer to Figure 1Each row of sub-pixel opening regions 700 has two opposite sides in the second direction Y, namely a first side Y1 and a second side Y2. In the second direction Y, four scan signal lines 220 are provided between adjacent rows of sub-pixel opening regions 700. In the direction from the first side Y1 to the second side Y2, the four scan signal lines 220 between adjacent rows of sub-pixel opening regions 700 are respectively a first scan signal line 221, a second scan signal line 222, a third scan signal line 223, and a fourth scan signal line. The four adjacent sub-pixel opening regions 700 in a row can be respectively a first sub-pixel opening region 710, a second sub-pixel opening region 720, a third sub-pixel opening region 730, and a fourth sub-pixel opening region 740. The gates of the pixel circuits corresponding to the four sub-pixel opening regions 700 are respectively a first gate 431, a second gate 432, a third gate 433, and a fourth gate 434. In the direction from the first side Y1 to the second side Y2, the four scanning signal lines located in the first side Y1 of the sub-pixel opening region 700 are, in sequence, the eleventh sub-scanning signal line 11, the twelfth sub-scanning signal line 12, the thirteenth sub-scanning signal line 13, and the fourteenth sub-scanning signal line 14; in the direction from the first side Y1 to the second side Y2, the four scanning signal lines located in the second side Y2 of the sub-pixel opening region 700 are, in sequence, the twenty-first sub-scanning signal line 21, the twenty-second sub-scanning signal line 22, the twenty-third sub-scanning signal line 23, and the twenty-fourth sub-scanning signal line 24.

[0095] refer to Figure 1 The first gate 431 is electrically connected to the twenty-second sub-scan signal line 22, the second gate 432 is electrically connected to the twenty-first sub-scan signal line 21, the third gate 433 is electrically connected to the thirteenth sub-scan signal line 13, and the fourth gate 434 is electrically connected to the fourteenth sub-scan signal line 14. The twenty-second and twenty-first sub-scan signal lines 22 and 21 are both located on the second side Y2 of the first sub-pixel opening region 710 and the second sub-pixel opening region 720, while the thirteenth and fourteenth sub-scan signal lines 13 and 14 are both located on the first side Y1 of the third sub-pixel opening region 730 and the fourth sub-pixel opening region 740. The first gate 431 and the second gate 432 are both located between the twenty-first and twenty-second sub-scan signal lines 21 and 22, and the third gate 433 and the fourth gate 434 are both located between the thirteenth and fourteenth sub-scan signal lines 13 and 14.

[0096] refer to Figure 1The four sub-pixel opening regions, from the first sub-pixel opening region 710 to the fourth sub-pixel opening region 740, can be considered as a minimum repeating unit. The pixel circuits of the sub-pixel opening regions of this minimum repeating unit are then connected to the scan signal lines on both sides of the second direction Y. The scan signal line 220 is located between two adjacent rows of sub-pixel opening regions 700 in the second direction Y. The scan signal line 220 does not overlap with any sub-pixel opening region 700 and is positioned to avoid sub-pixel opening regions 700. The scan signal line 220 closest to a sub-pixel opening region 700 can serve as the boundary of the sub-pixel opening region 700 in the second direction Y. The data signal line 230 can serve as the boundary of the sub-pixel opening region 700 in the first direction X.

[0097] refer to Figure 1 and Figure 5The pixel circuit corresponding to the first sub-pixel opening region 710 is electrically connected to the first data signal line 231; the pixel circuit corresponding to the second sub-pixel opening region 720 is electrically connected to the second data signal line 232; the pixel circuit corresponding to the third sub-pixel opening region 730 is electrically connected to the third data signal line 233; and the pixel circuit corresponding to the fourth sub-pixel opening region 740 is electrically connected to the fourth data signal line 234. A row of pixel circuits can be driven by four scan signal lines 220. The four pixel circuits corresponding to the four sub-pixel opening regions 700 in the same row can be connected to a single data signal connection line 240. For example, if the pixel circuit corresponding to the first sub-pixel opening region 710 is scanned by a scan signal provided by the twenty-second sub-scan signal line 22, then the data signal connection line 240 provides a data signal to the first data signal line 231 corresponding to the first sub-pixel opening region 710, thus driving the sub-pixel corresponding to the first sub-pixel opening region 710. The pixel circuit corresponding to the second sub-pixel opening region 720 is scanned by the scan signal provided by the twenty-first sub-scan signal line 21. At this time, the data signal connection line 240 provides a data signal to the second data signal line 232 corresponding to the second sub-pixel opening region 720, completing the driving of the sub-pixel corresponding to the second sub-pixel opening region 720. The pixel circuit corresponding to the third sub-pixel opening region 730 is scanned by the scan signal provided by the thirteenth sub-scan signal line 13. At this time, the data signal connection line 240 provides a data signal to the third data signal line 233 corresponding to the third sub-pixel opening region 730, completing the driving of the sub-pixel corresponding to the third sub-pixel opening region 730. The pixel circuit corresponding to the fourth sub-pixel opening region 740 is scanned by the scan signal provided by the fourteenth sub-scan signal line 14. At this time, the data signal connection line 240 provides a data signal to the fourth data signal line 234 corresponding to the fourth sub-pixel opening region 740, completing the driving of the sub-pixel corresponding to the fourth sub-pixel opening region 740. Since the pixel circuits corresponding to the first sub-pixel opening area 710 to the fourth sub-pixel opening area 740 are driven by 44 scanning signal lines in a time-division manner, the data signal connection line 240 can provide data signals to the four pixel circuits in a time-division manner. Therefore, the data signal connection line 240 of the four columns of pixel circuits can be shared. Compared with one-to-one data signal driving, the number of data signal connection lines can be reduced to 1 / 4 of the original number. Therefore, the data signal ports of the driver chip are also reduced to 1 / 4, which can reduce the number of driver chips, save costs, reduce the wiring density of data signal lines on the lower bezel of the display panel, and improve the signal transmission reliability of the signal lines.

[0098] refer to Figure 1The scan signal line 220 is disposed between adjacent sub-pixel opening regions 700 in the second direction Y, and the scan signal line 220 does not overlap with the sub-pixel opening region 700. Therefore, the sub-pixel opening region 700 will not be divided by the scan signal line 220, and each sub-pixel opening region 700 can be used as the opening of a complete sub-pixel. That is, the scan signal line will not cross through the sub-pixel opening, which can reduce the difference in sub-pixel opening regions caused by the cross-segmentation of the sub-pixel opening region by the scan signal line. In this way, the problem of uneven brightness between different sub-pixels can be reduced, and the problem of bright and dark stripes caused by the segmentation of the sub-pixel opening by the scan signal line can be eliminated. Therefore, the display panel provided in this embodiment can realize time-division multiplexing drive of data signal connection lines to reduce costs and improve display effect.

[0099] In some examples, reference Figure 1 The pixel electrode connection structure corresponding to the pixel electrode of the first sub-pixel opening region 710 is the first pixel electrode connection structure 621, the second sub-pixel opening region 720 corresponds to the second pixel electrode connection structure 622, the third sub-pixel opening region 730 corresponds to the third pixel electrode connection structure 623, and the fourth sub-pixel opening region 740 corresponds to the fourth pixel electrode connection structure 624. The first pixel electrode connection structure 621 and the third pixel electrode connection structure 623 are both located on the second side Y2 of the sub-pixel opening region, and the second pixel electrode connection structure 622 and the fourth pixel electrode connection structure 624 are both located on the first side Y1 of the sub-pixel opening region.

[0100] refer to Figure 1 The gate 430 and pixel electrode connection structure 620 corresponding to the sub-pixel aperture region 700 are both distributed on the first side Y1 or the second side Y2. The gate 430 of adjacent sub-pixel aperture regions 700 in the first direction X can be located on the same side or on different sides. The pixel electrode connection structure 620 of adjacent sub-pixel aperture regions 700 in the first direction X can be located on the same side or on different sides. The staggered arrangement of the gate 430 or pixel electrode connection structure 620 of adjacent sub-pixel aperture regions 700 in the first direction X can achieve a more reasonable distribution of vias and signal lines, and can make the film structure of sub-pixels in the same column obtained by translating and replicating the film structure of a single sub-pixel in the second direction, providing consistency of the sub-pixel structure in the column direction.

[0101] For example, refer to Figure 1 The pixel electrode 610 extends in two directions within a sub-pixel opening region 700, which can obtain a pseudo-dual-domain sub-pixel, enabling a larger viewing angle display, similar to a panel.

[0102] In some implementations, reference Figure 1The sub-pixel opening regions in the same row have the same size in the second direction Y. Without dividing the sub-pixel opening region 700 by the scan signal line 220, the consistency of the sub-pixel opening region 700 in the first direction X can be further improved, thus enhancing the display effect.

[0103] In some implementations, reference Figure 1 The sub-pixel opening regions 700 in the same row have the same size in the first direction X. Without dividing the sub-pixel opening regions 700 by the scan signal line 220, the consistency of the sub-pixel opening regions 700 in the second direction Y can be further improved, thus enhancing the display effect.

[0104] In some implementations, reference Figure 1 If the size of the sub-pixel opening regions 700 in the same row is the same in the second direction Y, and the size of the sub-pixel opening regions 700 in the same row is the same in the first direction X, then the consistency of the sub-pixel opening regions 700 in the same row in the first direction X and the second direction Y can be improved, and the degree of consistency is higher.

[0105] In some implementations, the areas of the sub-pixel opening regions in the same row are the same, or the shapes and sizes of the sub-pixel opening regions in the same row are the same. This means that the sub-pixel opening regions in the same row are all the same size, and the higher the degree of consistency, the better the uniformity of the display effect.

[0106] Figure 6 This is a schematic partial structural diagram of another display panel provided in an embodiment of the present disclosure.

[0107] In some implementations, reference Figure 6 In the second direction, the area between two adjacent rows of sub-pixel opening regions 700 is the interval region 800; the M scan signal lines 220 connected to the pixel circuits corresponding to the same row of sub-pixel opening regions are located in different adjacent interval regions 800, such as... Figure 6 As shown, M is set to 4. The two interval regions 800 on either side of the sub-pixel opening region 700 in the second direction Y are respectively the first interval region 810 and the second interval region 820. The first interval region 810 can be located on the first side Y1 of the sub-pixel opening region 700, and the second interval region 820 can be located on the second side Y2 of the sub-pixel opening region 700. The pixel circuits corresponding to the sub-pixel opening region are electrically connected to the two scan signal lines 220 of the first interval region 810 and the two scan signal lines 220 of the second interval region 820, respectively.

[0108] refer to Figure 6The scan signal line 220 is electrically connected to the gate 430. The gate of the pixel circuit corresponding to the first sub-pixel opening region 710 is the first gate 431, the gate of the pixel circuit corresponding to the second sub-pixel opening region 720 is the second gate 432, the gate of the pixel circuit corresponding to the third sub-pixel opening region 730 is the third gate 433, and the gate of the pixel circuit corresponding to the fourth sub-pixel opening region 740 is the fourth gate 434.

[0109] refer to Figure 6 The scanning signal lines 220 in the first interval region 810 are the eleventh sub-scanning signal line 11, the twelfth sub-scanning signal line 12, the thirteenth sub-scanning signal line 13, and the fourteenth sub-scanning signal line 14, respectively; the scanning signal lines 220 in the second interval region 820 are the twenty-first sub-scanning signal line 21, the twenty-second sub-scanning signal line 22, the twenty-third sub-scanning signal line 23, and the twenty-fourth sub-scanning signal line 24, respectively. The first gate 431 is located in the second interval region 820. The first gate 431 is used to connect the twenty-second sub-scan signal line 22, that is, the pixel circuit corresponding to the first sub-pixel opening region 710 is electrically connected to the twenty-second sub-scan signal line 22. The second gate 432 is located in the second interval region 820. The second gate 432 is used to connect the twenty-first sub-scan signal line 21, that is, the pixel circuit corresponding to the second sub-pixel opening region 720 is electrically connected to the twenty-first sub-scan signal line 21. The third gate 433 is located in the first interval region 810. The third gate 433 is used to connect the thirteenth sub-scan signal line 13, that is, the pixel circuit corresponding to the third sub-pixel opening region 730 is electrically connected to the thirteenth sub-scan signal line 13. The fourth gate 434 is located in the first interval region 810. The fourth gate 434 is used to connect the fourteenth sub-scan signal line 14, that is, the pixel circuit corresponding to the fourth sub-pixel opening region 740 is electrically connected to the fourteenth sub-scan signal line 14. The eleventh sub-scan signal line 11 and the twelfth sub-scan signal line 12 of the first interval region 810 are used to connect to the previous row of pixel circuits, and the twenty-third sub-scan signal line 23 and the twenty-fourth sub-scan signal line 24 of the second interval region 820 are used to connect to the next row of pixel circuits. The first pixel electrode connection structure 621 and the second pixel electrode connection structure 622 are both located in the second interval region 820, that is, on the second side Y2; the third pixel electrode connection structure 623 and the fourth pixel electrode connection structure 624 are both located in the first interval region 810, that is, on the first side Y1.

[0110] refer to Figure 6 The region between the opening regions of two adjacent rows of sub-pixels in the second direction Y is an interval region of 800. (Reference) Figure 5The substrate includes a display area AA and a non-display area NA; the scan driving circuit 220 can pass through the non-display area NA and the display area AA. The pixel circuit 101 is disposed in the display area AA, and the scan driving circuit 102 is disposed in the non-display area NA.

[0111] refer to Figure 6 Within the display area, the two boundaries of the interval region 800 in the second direction Y are defined by two scan signal lines, namely, the first scan signal line 221 and the fourth scan signal line 224. The two scan signal lines 220 defining the boundaries of the interval region 800 are symmetrical about the first center line 801, which is the center line of the interval region 800 extending along the first direction X. That is, the symmetry between the first scan signal line 221 and the fourth scan signal line 224 about the first center line 801 ensures that the boundary shape of the interval region 800 is consistent, which is more conducive to the consistency of the boundary of the sub-pixel opening region 700 in the second direction Y. Since the boundary of the interval region 800 in the second direction Y is shared with the boundary of the sub-pixel opening region 700, the improved shape consistency of the interval region 800 also improves the shape consistency of the sub-pixel opening region 700, further enhancing the display uniformity of the display panel and eliminating bright and dark stripe defects.

[0112] In some embodiments, at least two scan signal lines are provided between the two scan signal lines used to define the boundary of the interval region, so that at least four scan signal lines can be provided in each interval region. The scan signal lines between the two scan signal lines used to define the boundary of the interval region have a bend, and the scan signal lines at both ends of the bend extend in different directions.

[0113] refer to Figure 6 Within the same interval region 800, there are first scan signal lines 221 to fourth scan signal lines 224. The first scan signal line 221, fourth scan signal line 224, and data signal line 230 are used to define the boundary of the sub-pixel opening region 700. The second scan signal line 222 and the third scan signal line 223 are both located between the first scan signal line 221 and the fourth scan signal line 224, and the second scan signal line 222 and the third scan signal line 223 have bending segments 201.

[0114] refer to Figure 6 Two scanning signal lines are provided between the first scanning signal line 221 and the fourth scanning signal line 224, namely the second scanning signal line 222 and the third scanning signal line 223.

[0115] It should be noted that, Figure 6The four scan signal lines 220 shown in the interval region 800 are merely illustrative. Each interval region 800 may also contain four, five, six, or more scan signal lines; this disclosure does not impose any specific limitations.

[0116] refer to Figure 6 Both the second scan signal line 222 and the third scan signal line 223 have a bent section 201. Figure 6 The bending segment 201 shown is a right-angle bend. The bending segment can also be an arc bend, a wavy bend, or a circular arc bend, etc.

[0117] refer to Figure 6 The setting of the bend section 201 can be used to avoid vias, and the scan signal line 220 can be set at a position away from the via. The distance between the scan signal line and the via can be increased to avoid parasitic capacitance or signal crosstalk and improve the reliability of the scan signal line transmission signal.

[0118] refer to Figure 6 The pixel circuit and data signal line 230 are electrically connected through the first via 401. The gate 430 of the pixel circuit is electrically connected to the scan signal line 220. The pixel circuit and pixel electrode 610 are electrically connected through the second via 601. The orthogonal projections of the scan signal line 220 and the second via 601 on the substrate do not overlap. The orthogonal projections of the first via 401, gate 430, and second via 601 on the substrate all fall within the spacing region 800. The scan signal line 220 partially surrounds the first via 401, gate 430, and second via 601. The first via 401, gate 430, and second via 601 are all located between the two scan signal lines 220 connected to the gate 430. That is, the first gate 431 and the second gate 432 are both located between the twenty-first sub-scan signal line 21 and the twenty-second sub-scan signal line 22, and the third gate 433 and the fourth gate 434 are both located between the thirteenth sub-scan signal line 13 and the fourteenth sub-scan signal line 14.

[0119] In some examples, a portion of the first via is located between the bends of two adjacent scan signal lines.

[0120] refer to Figure 6 The second scan signal line 222 and the third scan signal line 223 bend twice each after passing through two sub-pixel opening regions 700. That is, for every two sub-pixel opening regions 700, there are two first vias 401 set between the second scan signal line 222 and the third scan signal line 223, and some of the first vias 401 are located in the area enclosed by the four bend segments 201 of the second scan signal line 222 and the third scan signal line 223.

[0121] refer to Figure 1 and Figure 6 The second scan signal line 222 and the third scan signal line 223 do not overlap with the orthographic projection of the first via 401 on the substrate. The scan signal line 220 avoids the first via 401, the gate 430 and the second via 601, which can prevent signal interference or parasitic capacitance caused by the via being too close to the scan signal line, thus affecting the stability of signal transmission.

[0122] In some implementations, the line connecting the center points of the first via, the gate, and the second via within the same spacing region is called the first connecting line. The orthogonal projection of the first connecting line onto the substrate is a straight line, which can improve the uniformity and consistency of the via distribution within the spacing region and is more conducive to the consistent setting of the sub-pixel opening region.

[0123] In some implementations, the orthographic projections of the first via, the gate, and the second via in the same spacing region onto the substrate can all fall on the same straight line, which can improve the uniformity and consistency of the via distribution in the spacing region to a certain extent, and further facilitate the consistent setting of the sub-pixel opening region.

[0124] In some embodiments, the line connecting the center points of the first via, the gate, and the second via within the same spaced region is called the first connection line. The maximum offset angle of the orthogonal projection of the first connection line onto the substrate relative to the first direction is greater than 0° and less than or equal to 60°. (Exemplary reference) Figure 6 If the angle between the first connecting line 802 and the first direction X is the first angle α, then 0°<α≤60°. This can reduce the positional deviation between vias to a certain extent, which helps to improve the consistency of the sub-pixel opening area.

[0125] In some implementations, multiple sub-pixel opening regions can be divided into multiple first repeating units; the distribution positions of the scan driving signal lines corresponding to the multiple first repeating units are consistent, and the connection relationship of the pixel circuits of the scan driving signal lines corresponding to the multiple first repeating units is consistent, which facilitates further improvement of the consistency of the pixel structure within the display panel.

[0126] refer to Figure 6The first sub-pixel opening region 710 to the fourth sub-pixel opening region 740 can constitute a minimum first repeating unit. The pixel circuit corresponding to a first repeating unit is connected to the thirteenth sub-scan signal line 13 and the fourteenth sub-scan signal line 14 located in the first interval region 810, and to the twenty-first sub-scan signal line 21 and the twenty-second sub-scan signal line 22 connected to the second interval region 820. The second scan signal line 222 on one side corresponding to the first repeating unit has four bends 201, and the third scan signal line 223 on one side corresponding to the first repeating unit also has four bends 201. The first via 401, gate 430, and second via 601 corresponding to the first sub-pixel opening region 710 and the second sub-pixel opening region 720 are all located between the first scan signal line 221 and the second scan signal line 222; the first via 401, gate 430, and second via 601 corresponding to the third sub-pixel opening region 730 and the fourth sub-pixel opening region 740 are all located between the third scan signal line 223 and the fourth scan signal line 224.

[0127] refer to Figure 6 The first repeating unit includes a first sub-pixel opening region 710, a second sub-pixel opening region 720, a third sub-pixel opening region 730, and a fourth sub-pixel opening region 740 arranged sequentially in the first direction. The pixel circuit corresponding to the first sub-pixel opening region 710 is a first pixel circuit, the pixel circuit corresponding to the second sub-pixel opening region 720 is a second pixel circuit, the pixel circuit corresponding to the third sub-pixel opening region 730 is a third pixel circuit, and the pixel circuit corresponding to the fourth sub-pixel opening region 740 is a fourth pixel circuit. The first pixel circuit is electrically connected to the twenty-second sub-scan signal line 22, the second pixel circuit is electrically connected to the twenty-first sub-scan signal line 21, the third pixel circuit is electrically connected to the thirteenth sub-scan signal line 13, and the fourth pixel circuit is electrically connected to the fourteenth sub-scan signal line 14.

[0128] refer to Figure 6 The first via 401, gate 430, and second via 601 corresponding to the first pixel circuit are all located between the twenty-first sub-scan signal line 21 and the twenty-second sub-scan signal line 22. The first via 401, gate 430, and second via 601 corresponding to the second pixel circuit are all located between the twenty-first sub-scan signal line 21 and the twenty-second sub-scan signal line 22. The first via 401, gate 430, and second via 601 corresponding to the third pixel circuit are all located between the thirteenth sub-scan signal line 13 and the fourteenth sub-scan signal line 14. The first via 401, gate 430, and second via 601 corresponding to the fourth pixel circuit are all located between the thirteenth sub-scan signal line 13 and the fourteenth sub-scan signal line 14.

[0129] refer to Figure 6With the boundary of a first repeating unit in the first direction X as the limit, the second scan signal line 222 and the third scan signal line 223 on one side each have four bends 201, that is, the second scan signal line 222 of an interval region 800 has four bends 201, and the third scan signal line 223 of an interval region 800 has four bends, for a total of eight bends. Some bends 201 are close to the boundaries of the adjacent second sub-pixel opening region 720 and the third sub-pixel opening region 730 in the first direction X, and some bends 201 are close to the boundaries of the adjacent first sub-pixel opening region 710 and the fourth sub-pixel opening region 740 in the first direction X.

[0130] refer to Figure 1 The first via 401 is located on the side of the bend 201 of the second scan signal line 222 away from the bend 201 of the third scan signal line 223.

[0131] refer to Figure 6 The first via 401 is located between the bend 201 of the second scan signal line 222 and the bend 201 of the third scan signal line 223. The first via 401 is located within the space enclosed by the bend 201 of the second scan signal line 222 and the third scan signal line 223.

[0132] In some implementations, the first via, gate, and second via corresponding to some pixel circuits are all located between the third scan signal line and the fourth scan signal line. (See reference) Figure 6 The first via, gate 430 and second via 601 corresponding to the third sub-pixel opening region 730 and the fourth sub-pixel opening region 740 are all located between the third scan signal line 223 and the fourth scan signal line 224.

[0133] In some embodiments, the first via, gate, and second via corresponding to a portion of the pixel circuit are all located between the first scan signal line and the second scan signal line. The first via, gate 430, and second via 601 corresponding to the first sub-pixel opening region 710 and the second sub-pixel opening region 720 are all located between the first scan signal line 221 and the second scan signal line 222.

[0134] In some implementations, multiple sub-pixel opening regions are arranged in columns in the second direction, and multiple columns of sub-pixel opening regions are arranged along the first direction. The distance between the second via with the same column and the first scan signal line is the same, and the distance between the second via with the same column and the fourth scan signal line is the same, which can improve the consistency of the via and scan signal line positions.

[0135] In some implementations, arranging the first vias in the same column along a straight line can improve the consistency of the arrangement of the first vias corresponding to different sub-pixels in the same column.

[0136] In some implementations, second vias in the same column are arranged in a straight line, which can improve the consistency of the arrangement of second vias corresponding to different sub-pixels in the same column.

[0137] In some implementations, gates in the same column are arranged in a straight line, which can improve the consistency of gate arrangement for different sub-pixels in the same column.

[0138] In some implementations, the gates of pixel circuits in the same column are arranged in a straight line, which can improve the consistency of the gate arrangement corresponding to different sub-pixels in the same column.

[0139] In some implementations, arranging the first vias in the same row along a straight line can improve the consistency of the arrangement of the first vias corresponding to different sub-pixels in the same row.

[0140] In some implementations, second vias in the same row are arranged in a straight line, which can improve the consistency of the arrangement of second vias corresponding to different sub-pixels in the same row.

[0141] In some implementations, the first scan signal line and the fourth scan signal line are parallel to each other within the same interval area.

[0142] For example, refer to Figure 6 Within the first interval region 810, the first scan signal line 221 and the fourth scan signal line 224 are parallel, and both the first scan signal line 221 and the fourth scan signal line 224 are straight lines.

[0143] In other examples, the first scan signal line 221 and the fourth scan signal line 224 may have bent or curved segments, such as wavy segments, arc segments, or bend segments.

[0144] In some examples, the second scan signal line and the third scan signal line are parallel to each other within the same interval area.

[0145] For example, refer to Figure 6 Within the first interval region 810, the second scan signal line 222 and the third scan signal line 223 are parallel; within the second interval region 820, the second scan signal line 222 and the third scan signal line 223 are parallel.

[0146] In some examples, the first scan signal lines in different interval regions are parallel to each other, the second scan signal lines in different interval regions are parallel to each other, the third scan signal lines in different interval regions are parallel to each other, and the fourth scan signal lines in different interval regions are parallel to each other.

[0147] For example, refer to Figure 6The eleventh sub-scan signal line 11 is parallel to the twenty-first sub-scan signal line 21, the twelfth sub-scan signal line 12 is parallel to the twenty-second sub-scan signal line 22, the thirteenth sub-scan signal line 13 is parallel to the twenty-third sub-scan signal line 23, and the fourteenth sub-scan signal line 14 is parallel to the twenty-fourth sub-scan signal line 24.

[0148] Parallelism of the scan signal lines on the display panel makes the shape of the sub-pixel opening area more regular and consistent, thus improving uniformity.

[0149] Figure 7 This is a schematic partial structural diagram of another display panel provided in an embodiment of the present disclosure.

[0150] In some implementations, reference Figure 7 The first repeating unit includes a first sub-pixel opening region 710, a second sub-pixel opening region 720, a third sub-pixel opening region 730, and a fourth sub-pixel opening region 740 arranged sequentially in the first direction X. The pixel circuit corresponding to the first sub-pixel opening region 710 is a first pixel circuit, the pixel circuit corresponding to the second sub-pixel opening region 720 is a second pixel circuit, the pixel circuit corresponding to the third sub-pixel opening region 730 is a third pixel circuit, and the pixel circuit corresponding to the fourth sub-pixel opening region 740 is a fourth pixel circuit. The first pixel circuit is electrically connected to the thirteenth sub-scan signal line 13, the second pixel circuit is electrically connected to the twenty-second sub-scan signal line 22, the third pixel circuit is electrically connected to the fourteenth sub-scan signal line 14, and the fourth pixel circuit is electrically connected to the twenty-first sub-scan signal line 21. The first pixel electrode connection structure 621 and the third pixel electrode connection structure 623 are both located in the first interval region 810, and the second pixel electrode connection structure 622 and the fourth pixel electrode connection structure 624 are both located in the second interval region 820. The first gate 431 and the third gate 433 are both located between the thirteenth sub-scan signal line 13 and the fourteenth sub-scan signal line 14. The second gate 432 and the fourth gate 434 are both located between the twenty-first sub-scan signal line 21 and the twenty-second sub-scan signal line 22.

[0151] refer to Figure 7With the boundary of a first repeating unit in the first direction X as the boundary, the second scan signal line 222 and the third scan signal line 223 of an interval region each have 8 bends 201, with the bends 201 close to the boundary of two adjacent sub-pixel opening regions in the first direction X. With the boundary of a first repeating unit in the first direction X as the boundary, the second scan signal line 222 of an interval region has 8 bends 201, and the third scan signal line 223 of an interval region has 8 bends 201, for a total of 16 bends 201. Four bends 201 are provided in the boundary region corresponding to each pair of adjacent sub-pixel opening regions 700 in the first direction X. Each second scan signal line 222 has 2 bends 201 in the boundary region corresponding to each pair of adjacent sub-pixel opening regions 700 in the first direction X, and each third scan signal line 223 has 2 bends 201 in the boundary region corresponding to each pair of adjacent sub-pixel opening regions 700 in the first direction X. The second scan signal line 222 is parallel to the third scan signal line 223.

[0152] In some examples, the first via, gate, and second via corresponding to the first pixel circuit are all located between the thirteenth sub-scan signal line 13 and the fourteenth sub-scan signal line 14; the first via, gate, and second via corresponding to the second pixel circuit are all located between the twenty-first sub-scan signal line 21 and the twenty-second sub-scan signal line 22; the first via, gate, and second via corresponding to the third pixel circuit are all located between the thirteenth sub-scan signal line 13 and the fourteenth sub-scan signal line 14; and the first via, gate, and second via corresponding to the fourth pixel circuit are all located between the twenty-first sub-scan signal line 21 and the twenty-second sub-scan signal line 22.

[0153] For example, refer to Figure 7 The thirteenth sub-scan signal line 13 and the twenty-second sub-scan signal line 22 corresponding to a first repeating unit are parallel to each other, the twelfth sub-scan signal line 12 and the twenty-second sub-scan signal line 22 corresponding to a first repeating unit are parallel to each other, and the fourteenth sub-scan signal line 14 and the twenty-first sub-scan signal line 21 corresponding to a first repeating unit are parallel to each other.

[0154] Figure 8 This is a schematic partial structural diagram of another display panel provided in an embodiment of the present disclosure.

[0155] In some implementations, reference Figure 8The first repeating unit includes eight sub-pixel opening regions arranged sequentially in a first direction, namely, the first sub-pixel opening region 710, the second sub-pixel opening region 720, the third sub-pixel opening region 730, the fourth sub-pixel opening region 740, the fifth sub-pixel opening region 750, the sixth sub-pixel opening region 760, the seventh sub-pixel opening region 770, and the eighth sub-pixel opening region 780. The first sub-pixel opening region 710 to the eighth sub-pixel opening region 780 correspond to eight pixel circuits, namely, the first pixel circuit to the eighth pixel circuit. The pixel circuits corresponding to the eight sub-pixel opening regions are electrically connected sequentially to the twenty-second sub-scan signal line 22, the fourteenth sub-scan signal line 14, the twenty-first sub-scan signal line 21, the thirteenth sub-scan signal line 13, and the thirteenth sub-scan signal line 13. Specifically, the first pixel circuit is electrically connected to the twenty-second sub-scan signal line 22, the second pixel circuit is electrically connected to the twenty-second sub-scan signal line 22, the third pixel circuit is electrically connected to the fourteenth sub-scan signal line 14, the fourth pixel circuit is electrically connected to the fourteenth sub-scan signal line 14, the fifth pixel circuit is electrically connected to the twenty-first sub-scan signal line 21, the sixth pixel circuit is electrically connected to the twenty-first sub-scan signal line 21, the seventh pixel circuit is electrically connected to the thirteenth sub-scan signal line 13, and the eighth pixel circuit is electrically connected to the thirteenth sub-scan signal line 13.

[0156] refer to Figure 8 The first gate 431, the first pixel electrode connection structure 621, the second gate 432, the second pixel electrode connection structure 622, the fifth gate 435, the fifth pixel electrode connection structure 625, the sixth gate 436, and the sixth pixel electrode connection structure 626 are all located between the twenty-first sub-scan signal line 21 and the twenty-second sub-scan signal line 22. The third gate 433, the third pixel electrode connection structure 623, the fourth gate 434, the fourth pixel electrode connection structure 624, the seventh gate 437, the seventh pixel electrode connection structure 627, the eighth gate 438, and the eighth pixel electrode connection structure 628 are all located between the thirteenth sub-scan signal line 13 and the fourteenth sub-scan signal line 14.

[0157] refer to Figure 8With the boundary of a first repeating unit in the first direction X as the boundary, the second scan signal line 222 and the third scan signal line 223 each have eight bend segments 201. With the boundary of a first repeating unit in the first direction X as the boundary, the twelfth sub-scan signal line 12 has eight bend segments 201, the thirteenth sub-scan signal line 13 has eight bend segments, the twenty-second sub-scan signal line 22 has eight bend segments 201, and the twenty-third sub-scan signal line 23 has eight bend segments. The second scan signal line 222 and the third scan signal line 223 are parallel.

[0158] In some embodiments, the first repeating unit includes 12 sub-pixel opening regions arranged sequentially in a first direction, each corresponding to one of the 12 pixel circuits. The pixel circuits corresponding to the 12 sub-pixel opening regions are respectively the first pixel circuit to the twelfth pixel circuit. The first pixel circuit to the twelfth pixel circuit are sequentially electrically connected to the twentieth sub-scan signal line 22, the fourteenth sub-scan signal line 14, the twenty-first sub-scan signal line 21, the thirteenth sub-scan signal line 13, and the thirteenth sub-scan signal line 13. Taking the boundary of a first repeating unit in the first direction X as a boundary, the second scan signal line and the third scan signal line each have 8 bends.

[0159] In some embodiments, the first repeating unit includes 16 sub-pixel opening regions arranged sequentially in a first direction, each corresponding to a pixel circuit. The 16 pixel circuits are respectively the first pixel circuit to the sixteenth pixel circuit. The first pixel circuit to the sixteenth pixel circuit are sequentially electrically connected to the twenty-second sub-scan signal line 22, the fourteenth sub-scan signal line 14, the twenty-first sub-scan signal line 21, the thirteenth sub-scan signal line 13, and the thirteenth sub-scan signal line 13.

[0160] In some implementations, the sub-pixel opening region corresponds to sub-pixels of three colors; multiple sub-pixel opening regions are divided into multiple second repeating units, each second repeating unit comprising N sub-pixel opening regions; a first repeating unit comprises K sub-pixel opening regions, where N is the least common multiple of 3 and K; the number of scan signal lines connected to the first repeating unit is M; the number of data signal connection lines connected to the second repeating unit is N÷M; wherein M, N, and K are all greater than 1.

[0161] For example, if K is 4, M is 4, then N is 12, and the number of data signal connection lines connected to the second repeating unit is 4.

[0162] For example, in the pixels of a liquid crystal display panel, the number of sub-pixels of the second repeating unit also needs to take into account the sub-pixel polarity. The sub-pixel polarity includes positive polarity and negative polarity. Then the number of sub-pixels of the second repeating unit is the least common multiple of 3, K and 2. When K is 4, N is 24.

[0163] Figure 9 This is a schematic partial structural diagram of a display panel provided in an embodiment of the present disclosure.

[0164] refer to Figure 9 Taking the second repeating unit, which includes 24 sub-pixels, as an example, they are, in order: red positive sub-pixel R+, green negative sub-pixel G-, blue positive sub-pixel B+, red negative sub-pixel R-, green positive sub-pixel G+, blue negative sub-pixel B-, red positive sub-pixel R+, green negative sub-pixel G-, blue positive sub-pixel B+, red negative sub-pixel R-, green positive sub-pixel G+, blue negative sub-pixel B-, red positive sub-pixel R-, green negative sub-pixel G-, blue positive sub-pixel B+, red negative sub-pixel R-, green positive sub-pixel G+, blue negative sub-pixel B-, red positive sub-pixel R-, green negative sub-pixel G-, blue positive sub-pixel B+, red negative sub-pixel R-, green positive sub-pixel G+, and blue negative sub-pixel B-.

[0165] refer to Figure 9 The red positive sub-pixel R+, the green negative sub-pixel G-, the blue positive sub-pixel B+, the red negative sub-pixel R-, the green positive sub-pixel G+, the blue negative sub-pixel B-, the red positive sub-pixel R+, and the green negative sub-pixel G- are connected in sequence to the twenty-first sub-scan signal line 21, the thirteenth sub-scan signal line 13, the thirteenth sub-scan signal line 13, the twenty-second sub-scan signal line 22, the twenty-second sub-scan signal line 22, the fourteenth sub-scan signal line 14, and the fourteenth sub-scan signal line 14.

[0166] refer to Figure 9 There are 6 data signal connection lines connected to a second repeating unit, namely red positive connection line DR+, red negative connection line DR-, green positive connection line DG+, green negative connection line DG-, blue positive connection line DB+, and blue negative connection line DB-.

[0167] refer to Figure 9 The red positive polarity connecting line DR+ is connected to the red positive polarity sub-pixel R+, the red negative polarity connecting line DR- is connected to the red negative polarity sub-pixel R-, the green positive polarity connecting line DG+ is connected to the green positive polarity sub-pixel G+, the green negative polarity connecting line DG- is connected to the green negative polarity sub-pixel G-, the blue positive polarity connecting line DB+ is connected to the blue positive polarity sub-pixel B+, and the blue negative polarity connecting line DB- is connected to the blue negative polarity sub-pixel B-.

[0168] This disclosure provides a display device, including: a display panel as described in any of the foregoing embodiments.

[0169] Figure 10 This is a schematic structural diagram of a display device provided in an embodiment of this disclosure. Figure 10 As shown, the display device includes a display panel 1000, which has the structural features of any of the embodiments included in the foregoing scope.

[0170] It should be noted that the display devices provided in this disclosure may include smartphones, tablets, laptops, televisions, and smart wearable display devices, etc. Smart wearable display devices may include smartwatches, VR (augmented reality) displays, and AR (virtual reality) displays, etc. The embodiments of this disclosure are not specifically limited.

[0171] The above embodiments are only used to illustrate the technical solutions of this disclosure, and are not intended to limit it. Although this disclosure has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some of the technical features. Such modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the spirit and scope of the technical solutions of the embodiments of this disclosure.

[0172] Although preferred embodiments have been described in this specification, those skilled in the art, upon learning the basic inventive concept, can make other changes and modifications to these embodiments. Therefore, the appended claims are intended to be interpreted as including the preferred embodiments as well as all changes and modifications falling within the scope of this specification.

[0173] Obviously, those skilled in the art can make various modifications and variations to this specification without departing from its spirit and scope. Therefore, if such modifications and variations fall within the scope of the claims and their equivalents, this specification is also intended to include such modifications and variations.

Claims

1. A display panel, characterized in that, include: A substrate, on one side of which are arranged multiple scan signal lines, multiple data signal lines and multiple data signal connection lines, wherein the multiple data signal lines are arranged at intervals along a first direction and the multiple scan signal lines are arranged at intervals along a second direction, and the first direction and the second direction intersect. One end of one of the multiple data signal connection lines is electrically connected to M of the multiple data signal lines, where M is a natural number greater than or equal to 4, and the other end of one of the multiple data signal connection lines is electrically connected to the data driving circuit. The display panel includes multiple sub-pixel opening areas, which are arranged in rows in the first direction. The multiple rows of sub-pixel opening areas are arranged along the second direction. Pixel electrodes are disposed in the sub-pixel opening areas, and pixel circuits are connected to the pixel electrodes. The pixel circuits corresponding to the sub-pixel opening areas in the same row are electrically connected to M of the multiple scan signal lines. The M scanning signal lines are located between two adjacent rows of the sub-pixel opening regions in the second direction, and do not overlap with the sub-pixel opening regions.

2. The display panel according to claim 1, characterized in that, The sub-pixel opening regions in the same row have the same size in the second direction; and / or, The sub-pixel opening regions in the same row have the same size in the first direction.

3. The display panel according to claim 1, characterized in that, The areas of the sub-pixel opening regions in the same row are the same, or the shapes and sizes of the sub-pixel opening regions in the same row are the same.

4. The display panel according to claim 1, characterized in that, The region between the opening regions of two adjacent rows of sub-pixels in the second direction is a gap region; The M scanning signal lines connected to the pixel circuit corresponding to the sub-pixel opening region in the same row are respectively located in adjacent different interval regions.

5. The display panel according to claim 1, characterized in that, The area between two adjacent rows of sub-pixel opening areas in the second direction is a gap region. The substrate includes a display area and a non-display area. In the display area, the two boundaries of the gap region in the second direction are defined by two scan signal lines. The two scan signal lines used to define the boundaries of the gap region are symmetrical about a first center line, which is the center line of the gap region extending along the first direction.

6. The display panel according to claim 4 or 5, characterized in that, At least two scanning signal lines are provided between the two scanning signal lines used to define the boundary of the interval region. The scanning signal lines between the two scanning signal lines used to define the boundary of the interval region have a bent section, and the scanning signal lines at both ends of the bent section extend in different directions.

7. The display panel according to claim 6, characterized in that, Within the display area, the bent scan signal lines in two adjacent interval areas in the second direction are parallel to each other, and the bent scan signal lines are the scan signal lines with bent segments.

8. The display panel according to claim 6, characterized in that, The pixel circuit is electrically connected to the data signal line through a first via, the gate of the pixel circuit is electrically connected to the scan signal line, and the pixel circuit is electrically connected to the pixel electrode through a second via. The orthographic projection of the scanning signal line on the substrate does not overlap with the orthographic projections of the first via and the second via on the substrate; The orthogonal projections of the first via, the gate, and the second via on the substrate all fall into the spacing region; The scan signal line portion surrounds the first via, the gate, and the second via.

9. The display panel according to claim 8, characterized in that, Part of the first via is located between the bends of two adjacent scan signal lines; and / or, The line connecting the center points of the first via, the gate and the second via in the same interval region is a first connecting line, and the orthogonal projection of the first connecting line on the substrate is a straight line. or, The maximum offset angle of the orthogonal projection of the first connection line on the substrate relative to the first direction is greater than 0° and less than or equal to 60°.

10. The display panel according to claim 8, characterized in that, A first scan signal line, a second scan signal line, a third scan signal line, and a fourth scan signal line are provided within the same interval region. The second scan signal line and the third scan signal line are located between the first scan signal line and the fourth scan signal line. The first scan signal line, the fourth scan signal line, and the data signal line are used to define the sub-pixel opening region. The first scan signal line and the fourth scan signal line are used to form the boundary of the interval region in the second direction. The second scan signal line and the third scan signal line have the bent section.

11. The display panel according to claim 10, characterized in that, The interval regions on both sides of the sub-pixel opening region in the second direction are respectively a first interval region and a second interval region. The pixel circuits corresponding to the sub-pixel opening regions in the row are respectively electrically connected to two scan signal lines of the first interval region and two scan signal lines of the second interval region; and / or, The first scan signal line and the fourth scan signal line within the same interval region are parallel to each other; and / or, The second scan signal line and the third scan signal line within the same interval region are parallel to each other.

12. The display panel according to claim 10, characterized in that, The first via, the gate, and the second via corresponding to a portion of the pixel circuit are all located between the third scan signal line and the fourth scan signal line; and / or, The first via, the gate, and the second via corresponding to a portion of the pixel circuit are all located between the first scan signal line and the second scan signal line; and / or, Multiple sub-pixel opening regions are arranged in columns along the second direction, and multiple columns of sub-pixel opening regions are arranged along the first direction. Second vias in the same column are equidistant from the first scan signal line, and second vias in the same column are equidistant from the fourth scan signal line; and / or, The first vias in the same column are arranged in a straight line; and / or, The second vias in the same column are arranged in a straight line; and / or, The gates in the same column are arranged in a straight line; and / or, The first vias in the same row are arranged in a straight line; and / or, The second vias in the same row are arranged in a straight line.

13. The display panel according to claim 10, characterized in that, The multiple sub-pixel opening regions are divided into multiple first repeating units; The interval regions on both sides of the sub-pixel opening region in the second direction are respectively the first interval region and the second interval region; In the direction from the first interval region to the second interval region, the eleventh sub-scan signal line, the twelfth sub-scan signal line, the thirteenth sub-scan signal line and the fourteenth sub-scan signal line are arranged sequentially in the first interval region, and the twenty-first sub-scan signal line, the twenty-second sub-scan signal line, the twenty-third sub-scan signal line and the twenty-fourth sub-scan signal line are arranged sequentially in the second interval region. The plurality of pixel circuits corresponding to the first repeating unit are electrically connected to the thirteenth sub-scan signal line, the fourteenth sub-scan signal line, the twenty-first sub-scan signal line, and the twenty-second sub-scan signal line, respectively.

14. The display panel according to claim 13, characterized in that, The first repeating unit includes a first sub-pixel opening region, a second sub-pixel opening region, a third sub-pixel opening region and a fourth sub-pixel opening region arranged sequentially in the first direction. The pixel circuit corresponding to the first sub-pixel opening region is a first pixel circuit, the pixel circuit corresponding to the second sub-pixel opening region is a second pixel circuit, the pixel circuit corresponding to the third sub-pixel opening region is a third pixel circuit, and the pixel circuit corresponding to the fourth sub-pixel opening region is a fourth pixel circuit. The first pixel circuit is electrically connected to the thirteenth sub-scan signal line, the second pixel circuit is electrically connected to the twenty-second sub-scan signal line, the third pixel circuit is electrically connected to the fourteenth sub-scan signal line, and the fourth pixel circuit is electrically connected to the twenty-first sub-scan signal line.

15. The display panel according to claim 14, characterized in that, With the boundary of the first repeating unit in the first direction as a limit, the second scan signal line and the third scan signal line each have 8 bending segments, the bending segments being close to the boundary of two adjacent sub-pixel opening regions in the first direction.

16. The display panel according to claim 13, characterized in that, The first repeating unit includes a first sub-pixel opening region, a second sub-pixel opening region, a third sub-pixel opening region and a fourth sub-pixel opening region arranged sequentially in the first direction. The pixel circuit corresponding to the first sub-pixel opening region is a first pixel circuit, the pixel circuit corresponding to the second sub-pixel opening region is a second pixel circuit, the pixel circuit corresponding to the third sub-pixel opening region is a third pixel circuit, and the pixel circuit corresponding to the fourth sub-pixel opening region is a fourth pixel circuit. The first pixel circuit is electrically connected to the 22nd sub-scan signal line, the second pixel circuit is electrically connected to the 21st sub-scan signal line, the third pixel circuit is electrically connected to the 13th sub-scan signal line, and the fourth pixel circuit is electrically connected to the 14th sub-scan signal line.

17. The display panel according to claim 16, characterized in that, With the boundary of the first repeating unit in the first direction as the limit, the second scan signal line and the third scan signal line each have four bending segments, some of which are close to the boundary of the second sub-pixel opening region and the third sub-pixel opening region adjacent in the first direction, and some of which are close to the boundary of the first sub-pixel opening region and the fourth sub-pixel opening region adjacent in the first direction.

18. The display panel according to claim 13, characterized in that, The first repeating unit includes eight sub-pixel opening regions arranged in a single sequence in the first direction, each corresponding to an eight pixel circuit. The pixel circuits corresponding to the eight sub-pixel opening regions are sequentially electrically connected to the twenty-second sub-scan signal line, the twenty-second sub-scan signal line, the fourteenth sub-scan signal line, the fourteenth sub-scan signal line, the twenty-first sub-scan signal line, the twenty-first sub-scan signal line, the thirteenth sub-scan signal line, and the thirteenth sub-scan signal line. or, The first repeating unit includes 12 sub-pixel opening regions arranged sequentially in the first direction, each corresponding to one of the 12 pixel circuits. The pixel circuits corresponding to the 12 sub-pixel opening regions are sequentially electrically connected to the 22nd sub-scan signal line, the 22nd sub-scan signal line, the 22nd sub-scan signal line, the 14th sub-scan signal line, the 14th sub-scan signal line, the 14th sub-scan signal line, the 21st sub-scan signal line, the 21st sub-scan signal line, the 21st sub-scan signal line, the 13th sub-scan signal line, the 13th sub-scan signal line, and the 13th sub-scan signal line. or, The first repeating unit includes 16 sub-pixel opening regions arranged sequentially in the first direction, each corresponding to a pixel circuit. The pixel circuits corresponding to the 16 sub-pixel opening regions are sequentially electrically connected to the 22nd sub-scan signal line, ...

19. The display panel according to claim 18, characterized in that, With the boundary of the first repeating unit in the first direction as a limit, the second scan signal line and the third scan signal line each have 8 of the bending segments.

20. The display panel according to claim 13, characterized in that, The sub-pixel opening area corresponds to sub-pixels of three colors; The plurality of sub-pixel opening regions are divided into a plurality of second repeating units, and the second repeating unit includes N sub-pixel opening regions; The first repeating unit includes K sub-pixel opening regions, where N is the least common multiple of 3 and K; The number of scan signal lines connected to the first repeating unit is M; The number of data signal connection lines connected to the second repeating unit is N÷M; Among them, M, N and K are all greater than 1.

21. A display device, characterized in that, include: The display panel as described in any one of claims 1 to 19.

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