Digital energy management system
By designing communication buffers and multi-power domain isolation hardware circuits for the digital energy management system, the communication security and bus compatibility issues of the EMS-BMS system were solved, achieving stable and secure multi-channel communication and module power supply isolation, thus meeting the parallel data interaction requirements of multiple cluster BMS.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Utility models(China)
- Current Assignee / Owner
- GUANGZHOU RAILWAY (GROUP) CORPORATION
- Filing Date
- 2025-10-10
- Publication Date
- 2026-07-14
AI Technical Summary
The existing EMS-BMS communication architecture has shortcomings in communication security, signal immunity, multi-protocol compatibility and power domain isolation, resulting in communication instability and module power supply interference.
A digital energy management system is adopted to design hardware circuits for communication buffering and multi-power domain isolation control, including FPGA, SRAM buffer, EEPROM, power module, uplink and downlink isolation units. Signal isolation is achieved through optocouplers, and the power supply of each communication module is controlled by MOSFETs to form independent power domains.
It improves the communication security of the EMS-BMS system, enhances bus compatibility, and reduces module power supply interference. It supports parallel data interaction among multiple BMS clusters, avoids bus conflicts and module power supply coupling interference, and ensures stable system operation.
Smart Images
Figure CN224501189U_ABST
Abstract
Description
Technical Field
[0001] This utility model belongs to the field of railway ferry energy storage technology, and in particular relates to a digital energy management system. Background Technology
[0002] With the rapid popularization of new energy storage systems, photovoltaic power plants and electric vehicle charging infrastructure, real-time communication and coordinated control between energy management systems (EMS) and battery management systems (BMS) have become the key to ensuring the safe and stable operation of the system.
[0003] Existing EMS-BMS communication architectures typically exchange data directly via CAN or RS-485 buses. While this approach is simple, it still has the following shortcomings:
[0004] Poor communication security and weak signal immunity: Uplink and downlink communication links often lack complete electrical isolation, making them susceptible to surges, electromagnetic interference and ground potential differences, which can lead to damage to the main control system or communication interruption.
[0005] Insufficient multi-protocol compatibility: Traditional EMS systems mostly use a single CAN or RS-485 interface, which cannot support communication between multiple BMS groups at the same time, thus limiting the unified access and centralized management of multiple battery clusters and systems from multiple manufacturers.
[0006] Low communication efficiency and high latency: Due to the lack of an independent hardware caching mechanism, the uplink and downlink data share the bus, which is prone to bus conflicts, data frame loss and latency, making it unsuitable for high real-time application scenarios.
[0007] Insufficient power domain isolation and control: Most systems use a unified power structure, which makes it impossible to independently control the power-on / power-off of different communication modules, resulting in complex maintenance and easy power coupling interference. Utility Model Content
[0008] The purpose of this invention is to provide a digital energy management system that solves the technical problems of poor communication security, low communication bus compatibility, and module power supply interference in EMS-BMS systems by designing a hardware circuit for communication buffering and multi-power domain isolation control.
[0009] To achieve the above objectives, the present invention adopts the following technical solution:
[0010] The digital energy management system includes an EMS system and a communication buffer board. The communication buffer board includes an FPGA, an SRAM buffer, an EEPROM, a power module, an uplink isolation unit, a downlink isolation unit, an uplink unit, and a downlink unit. The SRAM buffer, EEPROM, power module, uplink isolation unit, and downlink isolation unit are all connected to the FPGA. The uplink unit is connected to the uplink isolation unit, and the downlink unit is connected to the downlink isolation unit.
[0011] The uplink unit includes a CAN1 module and an Ethernet module, both of which are connected to and communicate with the EMS system.
[0012] The downlink unit includes a 485 module and a CAN2 module, both of which are connected to and communicate with an external BMS system.
[0013] The power module's input is connected to an external Vin power supply, and its outputs provide power to the Vcc power supply, Vcan1 power supply, Vphy power supply, Vcan2 power supply, and V485 power supply, respectively. The Vcc power supply powers the FPGA, uplink isolation unit, downlink isolation unit, SRAM buffer, and EEPROM; the Vcan1 power supply powers the CAN1 module; the Vphy power supply powers the Ethernet module; the Vcan2 power supply powers the CAN2 module; and the V485 power supply powers the 485 module.
[0014] The power module contains a MOSFET control unit, which includes multiple MOSFETs. Each MOSFET is connected to an I / O port of the FPGA. The external output circuits of the Vcan1 power supply, Vphy power supply group, Vcan2 power supply and V485 power supply are controlled by different MOSFETs.
[0015] Preferably, the power supply module specifically includes an AC-DC module, a DC-DC1 module, a TVS / filter unit A, a 3.3V regulator, a 1.2V regulator, a 1.8V regulator, a DC-DC2 module, a TVS / filter unit B, a 3.3V power supply module A, a 1.2V power supply module, MOSFETs A1, A2, A3, and A4, a DC-DC3 module, a TVS / filter unit C, a 3.3V power supply module B, MOSFETs A5 and A6, a Darlington transistor IC10, and optocouplers IC1, IC2, IC4, IC5, and IC6.
[0016] The input terminal of the AC-DC module is connected to an external AC power supply, and the output terminal outputs VIN-DC power.
[0017] The DC-DC1 module's input is connected to the VIN-DC power supply, and its output is connected to TVS / filter unit A. The 3.3V, 1.2V, and 1.8V regulators are all connected to TVS / filter unit A. The 3.3V regulator outputs Vcc-3.3V, the 1.2V regulator outputs Vcc-1.2V, and the 1.8V regulator outputs Vcc-1.8V. These Vcc-3.3V, Vcc-1.2V, and Vcc-1.8V power supplies constitute the Vcc power supply group. The Vcc-3.3V power supply powers the FPGA, SRAM buffer, EEPROM, uplink isolation unit, and downlink isolation unit, respectively. The Vcc-1.2V and Vcc-1.8V power supplies power the FPGA.
[0018] The input terminal of the DC-DC2 module is connected to the VIN-DC power supply, and the output terminal is connected to TVS / filter unit B. The input terminals of both the 3.3V power supply module A and the 1.2V power supply module are connected to TVS / filter unit B. The output terminal of the 3.3V power supply module A is connected to the drain (D) of MOSFET A1. The source (S) of MOSFET A1 outputs Vcan1 power, and the gate (G) is connected to pin OUT4 of Darlington transistor IC10. The output terminal of the 3.3V power supply module A is also connected to the drain (D) of MOSFET A2. The source (S) of MOSFET A2 outputs Vphy-3.3V power, and the gate (G) is connected to pin OUT1 of Darlington transistor IC10. The output terminal of the 1.2V power supply module is connected to the drain (D) of MOSFET A3. The source (S) of MOSFET A3 outputs Vphy-1.2V power, and the gate (G) is connected to pin OUT2 of Darlington transistor IC10.
[0019] The Vphy-3.3V power supply and the Vphy-1.2V power supply together constitute the Vphy power supply group, both of which power the Ethernet module;
[0020] The input terminal of the DC-DC3 module is connected to the VIN-DC power supply, and the output terminal is connected to the TVS / filter unit C. The input terminal of the 3.3V power supply module B is connected to the TVS / filter unit C. The output terminal of the 3.3V power supply module B is connected to the drain of MOSFET A5. The source terminal of MOSFET A5 outputs the Vcan2 power supply, and the gate terminal is connected to the OUT5 pin of Darlington transistor IC10. The output terminal of the 3.3V power supply module B is also connected to the drain of MOSFET A6. The source terminal of MOSFET A6 outputs the V485 power supply, and the gate terminal is connected to the OUT6 pin of Darlington transistor IC10.
[0021] The IN1, IN2, IN4, IN5 and IN6 pins of Darlington transistor IC10 are connected to a different set of I / O ports of the FPGA through optocoupler IC1, optocoupler IC2, optocoupler IC4, optocoupler IC5 and optocoupler IC6 respectively.
[0022] Preferably, the uplink isolation unit includes multiple optocouplers. The CAN1 module is isolated by one set of optocouplers in the uplink isolation unit and then connected to and communicates with the FPGA. The Ethernet module is isolated by another set of optocouplers in the uplink isolation unit and then connected to and communicates with the FPGA.
[0023] The downlink isolation unit includes multiple optocouplers. The 485 module is isolated by one set of optocouplers in the downlink isolation unit and then connected to and communicates with the FPGA. The CAN2 module is isolated by another set of optocouplers in the downlink isolation unit and then connected to and communicates with the FPGA.
[0024] Preferably, the FPGA signal is XC7S25-1FTGB196C; the SRAM buffer is IS61WV51216BLL-10TLI; and the EEPROM is AT24C64C.
[0025] The CAN1 module is model number SN65HVD230DR; the Ethernet module is model number LAN8720A; the 485 module is model number ADM2582E; and the CAN2 module is model number SN65HVD1040QDRQ1.
[0026] Preferably, the AC-DC module is model HLK-PM24; the DC-DC1 module is model LM2596S-ADJ; the DC-DC2 and DC-DC3 modules are both model TPS5430DDAR; the 3.3V regulator, 3.3V power module A, and 3.3V power module B are all model AMS1117-3.3; the 1.2V regulator and 1.2V power module are both model TPS7A7001; and the 1.8V regulator is model TLV1117LV18DCYR.
[0027] The Darlington transistor IC10 is model ULN2003A, and the optocouplers IC1, IC2, IC4, IC5 and IC6 are all model PC817.
[0028] TVS / filter unit A, TVS / filter unit B, and TVS / filter unit C are all composed of an LC filter network and TVS diodes, with the TVS diodes all being SMBJ24A.
[0029] Preferably, all optocouplers in the uplink isolation unit are of model PC817, and all optocouplers in the downlink isolation unit are of model PC817.
[0030] The digital energy management system described in this utility model solves the technical problems of poor communication security, low communication bus compatibility, and module power supply interference in EMS-BMS systems by designing a hardware circuit with communication buffering and multi-power domain isolation control. This utility model achieves optocoupler isolation for both uplink and downlink, completely blocking the ground potential coupling channel between EMS and BMS, while supporting dual CAN and RS-485 multi-channel communication to meet the parallel data interaction of multiple BMS clusters. The FPGA implements independent uplink / downlink channel control and buffering to avoid bus conflicts. The power supply of each communication module is controlled by MOSFET grouping, supporting dynamic start / stop and protection isolation. Attached Figure Description
[0031] Figure 1 This is a schematic diagram of the system architecture of this utility model;
[0032] Figure 2 This is a block diagram of the communication buffer board of this utility model;
[0033] Figure 3 This is a block diagram of the DC-DC1 module in the power supply module of this utility model.
[0034] Figure 4 This is a block diagram of the DC-DC2 module in the power supply module of this utility model.
[0035] Figure 5 This is a block diagram of the DC-DC3 module in the power supply module of this utility model.
[0036] Figure 6 This is the circuit wiring diagram of the Darlington transistor of this utility model. Detailed Implementation
[0037] Depend on Figures 1-6 The digital energy management system shown includes an EMS system and a communication buffer board. The communication buffer board includes an FPGA, an SRAM buffer, an EEPROM, a power module, an uplink isolation unit, a downlink isolation unit, an uplink unit, and a downlink unit. The SRAM buffer, EEPROM, power module, uplink isolation unit, and downlink isolation unit are all connected to the FPGA. The uplink unit is connected to the uplink isolation unit, and the downlink unit is connected to the downlink isolation unit.
[0038] The uplink unit includes a CAN1 module and an Ethernet module, both of which are connected to and communicate with the EMS system.
[0039] The downlink unit includes a 485 module and a CAN2 module, both of which are connected to and communicate with an external BMS system.
[0040] The uplink isolation unit includes multiple optocouplers. The CAN1 module is isolated by one set of optocouplers in the uplink isolation unit and then connected to and communicates with the FPGA. The Ethernet module is isolated by another set of optocouplers in the uplink isolation unit and then connected to and communicates with the FPGA.
[0041] The downlink isolation unit includes multiple optocouplers. The 485 module is isolated by one set of optocouplers in the downlink isolation unit and then connected to and communicates with the FPGA. The CAN2 module is isolated by another set of optocouplers in the downlink isolation unit and then connected to and communicates with the FPGA.
[0042] The FPGA signal is XC7S25-1FTGB196C; the SRAM buffer model is IS61WV51216BLL-10TLI; the EEPROM model is AT24C64C.
[0043] The CAN1 module is model number SN65HVD230DR; the Ethernet module is model number LAN8720A; the 485 module is model number ADM2582E; and the CAN2 module is model number SN65HVD1040QDRQ1.
[0044] All optocouplers in the uplink isolation unit are of model PC817, and all optocouplers in the downlink isolation unit are of model PC817.
[0045] In this embodiment, the external BMS system inputs the monitoring data to the FPGA through the CAN2 module and RS-485 module of the downlink unit, respectively, after optical isolation by the downlink isolation unit. The FPGA can be responsible for data buffering and signal scheduling, and outputs the processed data to the CAN1 module and Ethernet module through the uplink isolation unit, respectively, and then transmits it to the EMS system.
[0046] Meanwhile, control commands issued by EMS can also be transmitted via the reverse path of uplink unit → FPGA → downlink unit to achieve bidirectional secure communication.
[0047] In this embodiment, the specific logic executed in the FPGA can be customized according to user requirements.
[0048] The power module's input is connected to an external Vin power supply, and its outputs provide power to the Vcc power supply, Vcan1 power supply, Vphy power supply, Vcan2 power supply, and V485 power supply, respectively. The Vcc power supply powers the FPGA, uplink isolation unit, downlink isolation unit, SRAM buffer, and EEPROM; the Vcan1 power supply powers the CAN1 module; the Vphy power supply powers the Ethernet module; the Vcan2 power supply powers the CAN2 module; and the V485 power supply powers the 485 module.
[0049] The power module contains a MOSFET control unit, which includes multiple MOSFETs. Each MOSFET is connected to an I / O port of the FPGA. The external output circuits of the Vcan1 power supply, Vphy power supply group, Vcan2 power supply and V485 power supply are controlled by different MOSFETs.
[0050] The power supply module specifically includes an AC-DC module, a DC-DC1 module, a TVS / filter unit A, a 3.3V regulator, a 1.2V regulator, a 1.8V regulator, a DC-DC2 module, a TVS / filter unit B, a 3.3V power supply module A, a 1.2V power supply module, MOSFETs A1, A2, A3, and A4, a DC-DC3 module, a TVS / filter unit C, a 3.3V power supply module B, MOSFETs A5 and A6, a Darlington transistor IC10, and optocouplers IC1, IC2, IC4, IC5, and IC6.
[0051] The input terminal of the AC-DC module is connected to an external AC power supply, and the output terminal outputs VIN-DC power.
[0052] The DC-DC1 module's input is connected to the VIN-DC power supply, and its output is connected to TVS / filter unit A. The 3.3V, 1.2V, and 1.8V regulators are all connected to TVS / filter unit A. The 3.3V regulator outputs Vcc-3.3V, the 1.2V regulator outputs Vcc-1.2V, and the 1.8V regulator outputs Vcc-1.8V. These Vcc-3.3V, Vcc-1.2V, and Vcc-1.8V power supplies constitute the Vcc power supply group. The Vcc-3.3V power supply powers the FPGA, SRAM buffer, EEPROM, uplink isolation unit, and downlink isolation unit, respectively. The Vcc-1.2V and Vcc-1.8V power supplies power the FPGA.
[0053] The input terminal of the DC-DC2 module is connected to the VIN-DC power supply, and the output terminal is connected to TVS / filter unit B. The input terminals of both the 3.3V power supply module A and the 1.2V power supply module are connected to TVS / filter unit B. The output terminal of the 3.3V power supply module A is connected to the drain (D) of MOSFET A1. The source (S) of MOSFET A1 outputs Vcan1 power, and the gate (G) is connected to pin OUT4 of Darlington transistor IC10. The output terminal of the 3.3V power supply module A is also connected to the drain (D) of MOSFET A2. The source (S) of MOSFET A2 outputs Vphy-3.3V power, and the gate (G) is connected to pin OUT1 of Darlington transistor IC10. The output terminal of the 1.2V power supply module is connected to the drain (D) of MOSFET A3. The source (S) of MOSFET A3 outputs Vphy-1.2V power, and the gate (G) is connected to pin OUT2 of Darlington transistor IC10.
[0054] The Vphy-3.3V power supply and the Vphy-1.2V power supply together constitute the Vphy power supply group, both of which power the Ethernet module;
[0055] The input terminal of the DC-DC3 module is connected to the VIN-DC power supply, and the output terminal is connected to the TVS / filter unit C. The input terminal of the 3.3V power supply module B is connected to the TVS / filter unit C. The output terminal of the 3.3V power supply module B is connected to the drain of MOSFET A5. The source terminal of MOSFET A5 outputs the Vcan2 power supply, and the gate terminal is connected to the OUT5 pin of Darlington transistor IC10. The output terminal of the 3.3V power supply module B is also connected to the drain of MOSFET A6. The source terminal of MOSFET A6 outputs the V485 power supply, and the gate terminal is connected to the OUT6 pin of Darlington transistor IC10.
[0056] The IN1, IN2, IN4, IN5 and IN6 pins of Darlington transistor IC10 are connected to a different set of I / O ports of the FPGA through optocoupler IC1, optocoupler IC2, optocoupler IC4, optocoupler IC5 and optocoupler IC6 respectively.
[0057] The AC-DC module is model HLK-PM24; the DC-DC1 module is model LM2596S-ADJ; the DC-DC2 and DC-DC3 modules are both model TPS5430DDAR; the 3.3V regulator, 3.3V power module A, and 3.3V power module B are all model AMS1117-3.3; the 1.2V regulator and 1.2V power module are both model TPS7A7001; and the 1.8V regulator is model TLV1117LV18DCYR.
[0058] The Darlington transistor IC10 is model ULN2003A, and the optocouplers IC1, IC2, IC4, IC5 and IC6 are all model PC817.
[0059] TVS / filter unit A, TVS / filter unit B, and TVS / filter unit C are all composed of an LC filter network and TVS diodes, with the TVS diodes all being SMBJ24A.
[0060] In this embodiment, the external power supply (AC input or DC Vin) is converted into a stable DC power supply by the AC-DC module, and then sequentially passes through a DC-DC multiplexer and voltage regulator unit to form multiple independent power domains, specifically including:
[0061] The Vcc power supply mainly provides logic and control voltages for FPGA, SRAM, EEPROM and isolation units.
[0062] The Vcan1 / Vcan2 power supplies are mainly used to independently power the two CAN communication modules.
[0063] The Vphy power supply unit primarily provides 1.2V and 3.3V multi-stage power to Ethernet modules.
[0064] The V485 power supply is primarily designed for RS-485 communication modules.
[0065] The power output of each communication module is controlled by an array of MOSFETs and Darlington transistors, enabling independent start-up and shutdown according to FPGA instructions.
[0066] In this embodiment, the power supply is also protected against surges and EMI suppression by a TVS / filter unit to ensure stable operation of the entire communication buffer board in a complex electromagnetic environment.
[0067] The digital energy management system described in this utility model solves the technical problems of poor communication security, low communication bus compatibility, and module power supply interference in EMS-BMS systems by designing a hardware circuit with communication buffering and multi-power domain isolation control. This utility model achieves optocoupler isolation for both uplink and downlink, completely blocking the ground potential coupling channel between EMS and BMS, while supporting dual CAN and RS-485 multi-channel communication to meet the parallel data interaction of multiple BMS clusters. The FPGA implements independent uplink / downlink channel control and buffering to avoid bus conflicts. The power supply of each communication module is controlled by MOSFET grouping, supporting dynamic start / stop and protection isolation.
Claims
1. A digital energy management system, characterized in that: It includes an EMS system and a communication buffer board. The communication buffer board includes an FPGA, an SRAM buffer, an EEPROM, a power module, an uplink isolation unit, a downlink isolation unit, an uplink unit, and a downlink unit. The SRAM buffer, EEPROM, power module, uplink isolation unit, and downlink isolation unit are all connected to the FPGA. The uplink unit is connected to the uplink isolation unit, and the downlink unit is connected to the downlink isolation unit. The uplink unit includes a CAN1 module and an Ethernet module, both of which are connected to and communicate with the EMS system. The downlink unit includes a 485 module and a CAN2 module, both of which are connected to and communicate with an external BMS system. The power module's input is connected to an external Vin power supply, and its outputs provide power to the Vcc power supply, Vcan1 power supply, Vphy power supply, Vcan2 power supply, and V485 power supply, respectively. The Vcc power supply powers the FPGA, uplink isolation unit, downlink isolation unit, SRAM buffer, and EEPROM; the Vcan1 power supply powers the CAN1 module; the Vphy power supply powers the Ethernet module; the Vcan2 power supply powers the CAN2 module; and the V485 power supply powers the 485 module. The power module contains a MOSFET control unit, which includes multiple MOSFETs. Each MOSFET is connected to an I / O port of the FPGA. The external output circuits of the Vcan1 power supply, Vphy power supply group, Vcan2 power supply and V485 power supply are controlled by different MOSFETs.
2. The digital energy management system as described in claim 1, characterized in that: The power supply module specifically includes an AC-DC module, a DC-DC1 module, a TVS / filter unit A, a 3.3V regulator, a 1.2V regulator, a 1.8V regulator, a DC-DC2 module, a TVS / filter unit B, a 3.3V power supply module A, a 1.2V power supply module, MOSFETs A1, A2, A3, and A4, a DC-DC3 module, a TVS / filter unit C, a 3.3V power supply module B, MOSFETs A5 and A6, a Darlington transistor IC10, and optocouplers IC1, IC2, IC4, IC5, and IC6. The input terminal of the AC-DC module is connected to an external AC power supply, and the output terminal outputs VIN-DC power. The DC-DC1 module's input is connected to the VIN-DC power supply, and its output is connected to TVS / filter unit A. The 3.3V, 1.2V, and 1.8V regulators are all connected to TVS / filter unit A. The 3.3V regulator outputs Vcc-3.3V, the 1.2V regulator outputs Vcc-1.2V, and the 1.8V regulator outputs Vcc-1.8V. These Vcc-3.3V, Vcc-1.2V, and Vcc-1.8V power supplies constitute the Vcc power supply group. The Vcc-3.3V power supply powers the FPGA, SRAM buffer, EEPROM, uplink isolation unit, and downlink isolation unit, respectively. The Vcc-1.2V and Vcc-1.8V power supplies power the FPGA. The input terminal of the DC-DC2 module is connected to the VIN-DC power supply, and the output terminal is connected to the TVS / filter unit B. The input terminals of the 3.3V power supply module A and the 1.2V power supply module are both connected to the TVS / filter unit B. The output terminal of the 3.3V power supply module A is connected to the drain of MOSFET A1. The source terminal of MOSFET A1 outputs the Vcan1 power supply, and the gate terminal is connected to the OUT4 pin of Darlington transistor IC10. The output terminal of the 3.3V power supply module A is also connected to the drain of MOSFET A2. The source terminal of MOSFET A2 outputs the Vphy-3.3V power supply, and the gate terminal is connected to the OUT1 pin of Darlington transistor IC10. The output terminal of the 1.2V power module is connected to the drain (D) of MOSFET A3. The source (S) of MOSFET A3 outputs Vphy-1.2V power, and the gate (G) is connected to the OUT2 pin of Darlington transistor IC10. The Vphy-3.3V power supply and the Vphy-1.2V power supply together constitute the Vphy power supply group, both of which power the Ethernet module; The input terminal of the DC-DC3 module is connected to the VIN-DC power supply, and the output terminal is connected to the TVS / filter unit C. The input terminal of the 3.3V power supply module B is connected to the TVS / filter unit C. The output terminal of the 3.3V power supply module B is connected to the drain of MOSFET A5. The source terminal of MOSFET A5 outputs the Vcan2 power supply, and the gate terminal is connected to the OUT5 pin of Darlington transistor IC10. The output terminal of the 3.3V power supply module B is also connected to the drain of MOSFET A6. The source terminal of MOSFET A6 outputs the V485 power supply, and the gate terminal is connected to the OUT6 pin of Darlington transistor IC10. The IN1, IN2, IN4, IN5 and IN6 pins of Darlington transistor IC10 are connected to a different set of I / O ports of the FPGA through optocoupler IC1, optocoupler IC2, optocoupler IC4, optocoupler IC5 and optocoupler IC6 respectively.
3. The digital energy management system as described in claim 1, characterized in that: The uplink isolation unit includes multiple optocouplers. The CAN1 module is isolated by one set of optocouplers in the uplink isolation unit and then connected to and communicates with the FPGA. The Ethernet module is isolated by another set of optocouplers in the uplink isolation unit and then connected to and communicates with the FPGA. The downlink isolation unit includes multiple optocouplers. The 485 module is isolated by one set of optocouplers in the downlink isolation unit and then connected to and communicates with the FPGA. The CAN2 module is isolated by another set of optocouplers in the downlink isolation unit and then connected to and communicates with the FPGA.
4. The digital energy management system as described in claim 1, characterized in that: The FPGA signal is XC7S25-1FTGB196C; the SRAM buffer model is IS61WV51216BLL-10TLI; the EEPROM model is AT24C64C. The CAN1 module is model number SN65HVD230DR; the Ethernet module is model number LAN8720A; the 485 module is model number ADM2582E; and the CAN2 module is model number SN65HVD1040QDRQ1.
5. The digital energy management system as described in claim 2, characterized in that: The AC-DC module is model HLK-PM24; the DC-DC1 module is model LM2596S-ADJ; the DC-DC2 and DC-DC3 modules are both model TPS5430DDAR; the 3.3V regulator, 3.3V power module A, and 3.3V power module B are all model AMS1117-3.3; the 1.2V regulator and 1.2V power module are both model TPS7A7001; and the 1.8V regulator is model TLV1117LV18DCYR. The Darlington transistor IC10 is model ULN2003A, and the optocouplers IC1, IC2, IC4, IC5 and IC6 are all model PC817. TVS / filter unit A, TVS / filter unit B, and TVS / filter unit C are all composed of an LC filter network and TVS diodes, with the TVS diodes all being SMBJ24A.
6. The digital energy management system as described in claim 3, characterized in that: All optocouplers in the uplink isolation unit are of model PC817, and all optocouplers in the downlink isolation unit are of model PC817.