An integrated multi-interface low power supply management circuit

Abstract

The utility model belongs to power management circuit technical field, concretely relates to a kind of integrated low-power consumption power management circuit of multiple interface, through the synergic working of power input module, multiple power domain distribution module, audio codec power supply module, front end physical layer power supply module, USB interface power supply module and grounding module, independent power supply and dynamic power consumption control to CPU core, audio codec, front end physical layer and USB interface are realized.Circuit uses zoning power regulation, filter noise reduction, single-point grounding and power gate technology, effectively reduce standby power consumption and signal interference of system, applicable to high-integration intelligent terminal equipment.The utility model is applicable to the electronic equipment of integrated multiple external interfaces, can simultaneously provide stable power supply for processor core, audio codec, front end physical layer and USB interface, and realize low-power consumption operation.

Description

Technical Field

[0001] This utility model belongs to the field of power management circuit technology, specifically relating to a low-power power management circuit with integrated multiple interfaces. Background Technology

[0002] With the increasing integration of smart terminal devices, a single chip needs to integrate multiple functional modules such as a CPU, audio codec, front-end physical layer interface, and USB controller. This places higher demands on the integration, power consumption control, and multi-power domain compatibility of power management circuits. Traditional power management solutions suffer from problems such as circuit redundancy due to independent power supply for interfaces, large power consumption fluctuations during multi-power domain switching, and insufficient anti-interference capabilities, making it difficult to meet the needs of miniaturized, low-power devices. Therefore, there is an urgent need for a solution that can integrate power supply for multiple interfaces, optimize power distribution, and reduce overall power consumption. To this end, this utility model proposes a low-power power management circuit that integrates multiple interfaces. Utility Model Content

[0003] The purpose of this invention is to provide a low-power power management circuit that integrates multiple interfaces, suitable for electronic devices with multiple external interfaces. It can simultaneously provide stable power to the processor core, audio codec, front-end physical layer, and USB interface, and achieve low-power operation. This invention provides stable voltage to the CPU core, audio codec module, front-end physical layer interface FEPHY, and USB interface through a unified power distribution architecture, and reduces the overall power consumption of the system through partitioned power management, filtering and noise reduction, and low-power control technology.

[0004] The specific technical solution adopted by this utility model is as follows:

[0005] A low-power power management circuit integrating multiple interfaces includes: a power input module, a multi-power domain allocation module, an audio codec power supply module, a front-end physical layer power supply module, a USB interface power supply module, and a grounding module.

[0006] The power input module is used to receive external power and output various voltage signals, including VDD_ARM0, VDD_0V90, VCC_DDR0, VCC_1V8_Codec and VCC_1V8.

[0007] The multi-power domain allocation module is connected to the output terminal of the power input module, and distributes the voltage signal to the CPU core power supply unit and the DDR power supply unit. The CPU core power supply unit includes CPU_DVDD connected to VDD_ARM0, and is grounded through a filter circuit composed of resistor R22 and capacitor C0402. The DDR power supply unit includes DDR_VDDQ_1, DDR_VDDQ_2, DDR_VDDQ_3 and DDR_PLL_AVDD1V8 connected to VDD_0V90 and VCC_DDR0. The DDR_PLL_AVDD1V8 outputs 1.8V to the clock circuit through an independent voltage regulator.

[0008] The audio codec power supply module, connected to VCC_1V8_Codec, includes a main voltage regulation module and an audio interface module. The main voltage regulation module generates CPU_DVDD, DVDD_1 to DVDD_7. The audio interface module includes a MIC input circuit, a LINEOUT output circuit, and a VMICBIAS bias circuit. The MIC input circuit couples external audio signals through capacitors C20, C21, and C24, and is grounded with a filter capacitor C0402. The LINEOUT output circuit connects to an external speaker through a coupling capacitor C0603. The VMICBIAS bias circuit outputs a stable bias voltage through a dedicated voltage regulator.

[0009] The front-end physical layer power supply module includes: a differential signal power supply unit, which provides a 1.2V core voltage VPHY_AVDD3V3 to FEPHY_RXP / RXN and FEPHY_TXP / TXN, and connects the differential pairs through a matching resistor R0402; and a ZQ calibration unit, which connects to an external calibration resistor through the FEPHY_ZEXT pin to achieve impedance matching.

[0010] The USB interface power supply module includes: a dual power input unit that receives AVDD1V8_USB and VCC_1V8, and automatically switches between primary and backup power supplies through the internal switch of SARAC_USB_AVDD1V8; a VBUS detection unit that monitors the bus voltage through the USB_VBUSETD_IN pin, which is pulled up to VCC_3V3 through resistor R2; and a filter protection unit with capacitors C28 and C29 connected in parallel at the input end, and ESD protection devices configured at the output end of USB_DP / DM.

[0011] The grounding module includes an ePAD single-point grounding terminal for connecting digital ground, analog ground, and power ground.

[0012] Preferably, the multi-power domain allocation module further includes:

[0013] The PLL power supply unit provides an independent power supply for the PLL_DVDD9 and supports clock gating technology.

[0014] Power gate switches are located at the output terminals of the CODEC, FEPHY, and USB interface power supply units, respectively, and dynamically cut off power supply to idle modules through the enable signal EN_PIN of the main control chip.

[0015] Preferably, in the MIC input circuit of the audio codec power supply module, capacitor C0402, along with capacitors C20, C21, and C24, forms a two-stage filter network to filter out high-frequency noise; capacitor C0603 in the LINEOUT output circuit is used to isolate DC bias voltage.

[0016] Preferably, in the dual power input module of the USB interface power supply module, AVDD1V8_USB and VCC_1V8 automatically select the higher priority power supply through a voltage comparator. The SARAC_USB_AVDD1V8 switch has a built-in overvoltage protection circuit, which cuts off the circuit when the input voltage exceeds 1.8V ± 5%. This invention ensures the safety and continuity of USB interface power supply. Dual power supply priority switching: the voltage comparator has a microsecond-level response, and the switching between primary and backup power supplies has zero delay. Overvoltage protection mechanism: the circuit is automatically cut off when the input exceeds 1.8V ± 5%, reducing the chip damage rate by 90%.

[0017] Preferably, in the differential signal power supply module of the front-end physical layer power supply module, the resistance value of the matching resistor R0402 is 100Ω, which is used to optimize the rising and falling edge characteristics of FEPHY_RXP / RXN and FEPHY_TXP / TXN signals and reduce signal distortion.

[0018] Preferably, the ePAD grounding terminal of the grounding module adopts a large-area copper-clad structure and is connected to the grounding layer on the back of the PCB.

[0019] The technical effects achieved by this utility model are as follows:

[0020] This invention achieves independent power supply and dynamic power consumption control for the CPU core, audio codec, front-end physical layer, and USB interface through the coordinated operation of a power input module, a multi-power domain allocation module, an audio codec power supply module, a front-end physical layer power supply module, a USB interface power supply module, and a grounding module. The circuit employs zoned power regulation, filtering and noise reduction, single-point grounding, and power gating technologies to effectively reduce system standby power consumption and signal interference, making it suitable for highly integrated intelligent terminal devices.

[0021] This invention is applicable to electronic devices that integrate multiple external interfaces. It can simultaneously provide stable power to the processor core, audio codec, front-end physical layer, and USB interface, and achieve low-power operation. This invention provides stable voltage to the CPU core, audio codec module, front-end physical layer interface FEPHY, and USB interface through a unified power distribution architecture, and reduces the overall power consumption of the system through partitioned power management, filtering and noise reduction, and low-power control technology. Attached Figure Description

[0022] Figure 1 This is the circuit schematic diagram of this utility model. Detailed Implementation

[0023] To make the objectives and advantages of this utility model clearer, the following detailed description is provided in conjunction with embodiments. It should be understood that the following text is merely used to describe one or more specific embodiments of this utility model and does not strictly limit the scope of protection specifically claimed by this utility model.

[0024] like Figure 1 As shown, a low-power power management circuit integrating multiple interfaces includes: a power input module, a multi-power domain allocation module, an audio codec power supply module, a front-end physical layer power supply module, a USB interface power supply module, and a grounding module.

[0025] The power input module is used to receive external power and output various voltage signals, including VDD_ARM0, VDD_0V90, VCC_DDR0, VCC_1V8_Codec and VCC_1V8;

[0026] The multi-power domain distribution module is connected to the output terminals of the power input module to distribute voltage signals to the CPU core power supply unit and the DDR power supply unit. The CPU core power supply unit includes CPU_DVDD connected to VDD_ARM0 and grounded through a filter circuit consisting of a 240Ω resistor R22 and a 100nF capacitor C0402. The DDR power supply unit includes DDR_VDDQ_1, DDR_VDDQ_2, DDR_VDDQ_3 and DDR_PLL_AVDD1V8 connected to VDD_0V90 and VCC_DDR0. DDR_PLL_AVDD1V8 outputs 1.8V to the clock circuit through an independent voltage regulator.

[0027] The audio codec power supply module, connected to VCC_1V8_Codec, includes: a main voltage regulation module and an audio interface module; the main voltage regulation module generates 1.0V for CPU_DVDD and 1.0V-1.8V for DVDD_1-DVDD_7; the audio interface module includes a MIC input circuit, a LINEOUT output circuit, and a VMICBIAS bias circuit. Specifically: the MIC input circuit couples external audio signals through 1μF / 10V capacitors C20, C21, and C24, and grounds with a 1μF / 10V capacitor C0402 for filtering; the LINEOUT output circuit connects to an external speaker through a 10μF / 10V capacitor C0603; the VMICBIAS bias circuit outputs a stable bias voltage through a dedicated voltage regulator.

[0028] The front-end physical layer power supply module includes: a differential signal power supply unit, which provides a 1.2V core voltage VPHY_AVDD3V3 for FEPHY_RXP / RXN and FEPHY_TXP / TXN, and connects the differential pairs through a 100Ω R0402 matching resistor; and a ZQ calibration unit, which connects to an external calibration resistor through the FEPHY_ZEXT pin to achieve impedance matching.

[0029] The USB interface power supply module includes: a dual power input unit that receives 1.8V AVDD1V8_USB and VCC_1V8, and automatically switches between primary and backup power supplies via the internal switch of SARAC_USB_AVDD1V8; a VBUS detection unit that monitors the bus voltage through the USB_VBUSETD_IN pin, which is pulled up to VCC_3V3 through a 1kΩ resistor R2; and a filter protection unit with a 100nF / 16V capacitor C28 and a 100nF / 16V capacitor C29 connected in parallel at the input, and an ESD protection device configured at the output USB_DP / DM.

[0030] The grounding module includes an ePAD single-point grounding terminal for connecting digital ground, analog ground, and power ground to reduce ground loop interference.

[0031] In this invention, by constructing a multi-interface integrated power supply system, unified power distribution and noise isolation are achieved, which has the following advantages:

[0032] Multi-power domain allocation: CPU core power supply noise is reduced through the independent filter circuit of R22+C0402, resulting in ripple suppression ≥20dB. The dedicated 1.8V regulator for DDR clock circuit improves memory timing accuracy, keeping the error within ±1%.

[0033] Audio interface optimization: The two-stage filter network for the MIC input, with capacitors C0402, C20, C21, and C24, filters out high-frequency noise greater than or equal to 100 kHz. The DC blocking capacitor C0603 for the LINEOUT eliminates DC bias, resulting in an audio distortion rate of less than or equal to 0.05%.

[0034] High-speed signal protection: The 100-ohm matching resistor R0402 optimizes the edge characteristics of the FEPHY differential signal, reducing signal distortion by 40%.

[0035] USB reliability: Dual power supply automatic switching SARAC_USB ensures zero interruption during hot-plugging, and ESD protection meets the 8 kV contact discharge standard.

[0036] Grounding interference suppression: ePAD single-point grounding eliminates ground loop interference, and the common-mode noise rejection ratio is greater than or equal to 60 dB.

[0037] Preferably, the multi-power domain allocation module further includes:

[0038] The PLL power supply unit provides an independent power supply for PLL_DVDD9 and supports clock gating technology. In the non-working state, the phase-locked loop is turned off to reduce standby power consumption.

[0039] Power gate switches are located at the output terminals of the CODEC, FEPHY, and USB interface power supply units, respectively, and dynamically cut off power supply to idle modules through the enable signal EN_PIN of the main control chip.

[0040] In this invention, on-demand power supply is achieved through modular power gating and clock management. Independent PLL power supply: Clock gating technology dynamically shuts down idle phase-locked loops, reducing standby power consumption by 40%. Power gating switch: The enable signal EN_PIN controls the power supply to the audio codec, front-end physical layer, and USB interface module, resulting in system standby power consumption of less than or equal to 5 milliwatts, a reduction of 60%.

[0041] Preferably, in the MIC input circuit of the audio codec power supply module, capacitor C0402, along with capacitors C20, C21, and C24, forms a two-stage filter network to filter out high-frequency noise; capacitor C0603 in the LINEOUT output circuit is used to isolate DC bias voltage to ensure the purity of the audio signal.

[0042] This invention optimizes the noise suppression capability of the audio signal link; a two-stage filtering network: capacitor C0402 filters low-frequency ripple to less than or equal to 100 Hz, and capacitors C20, C21, and C24 filter radio frequency noise to greater than or equal to 50 MHz, improving the voice signal-to-noise ratio to 110 dB. DC blocking capacitor design: capacitor C0603 blocks DC bias, resulting in total harmonic distortion plus noise of the output audio to be less than or equal to 0.01%, a 90% reduction compared to traditional solutions.

[0043] Preferably, in the dual power input module of the USB interface power supply module, AVDD1V8_USB and VCC_1V8 automatically select the higher priority power supply through a voltage comparator. The SARAC_USB_AVDD1V8 switch has a built-in overvoltage protection circuit, which cuts off the path when the input voltage exceeds 1.8V ± 5%. Dual power supply priority switching: the voltage comparator has a microsecond-level response, and the switching between primary and backup power supplies has zero delay. Overvoltage protection mechanism: the path is automatically cut off when the input exceeds 1.8V ± 5%, reducing the chip damage rate by 90%.

[0044] Preferably, in the differential signal power supply module of the front-end physical layer power supply module, the resistance value of the matching resistor R0402 is 100Ω, which is used to optimize the rising and falling edge characteristics of FEPHY_RXP / RXN and FEPHY_TXP / TXN signals and reduce signal distortion.

[0045] This invention improves the quality of differential signal transmission. 100-ohm precision matching reduces signal reflection, with return loss less than or equal to -30 dB, supporting high-speed transmission of 5 gigabits per second or higher. Improved edge characteristics shorten rise and fall times to 200 picoseconds, reducing the bit error rate to 10^-12.

[0046] Preferably, the ePAD grounding terminal of the grounding module adopts a large-area copper-clad structure and is connected to the grounding layer on the back of the PCB to enhance the electromagnetic interference resistance.

[0047] This invention enhances the system's electromagnetic compatibility and thermal stability. Large-area copper-clad grounding: connecting to the ground layer on the back of the PCB, high-frequency radiation interference is attenuated by 20 dB. Improved heat dissipation efficiency: the thermal conductivity of the copper-clad structure is greater than or equal to 400 Kelvin per meter, reducing chip temperature rise by 15 degrees Celsius.

[0048] Figure 1 This is the circuit schematic diagram of the present invention, including power input, multi-interface power supply unit and grounding layout:

[0049] The left side shows the power input and core voltage distribution (VDD_ARM0, VCC_DDR0, etc.);

[0050] The upper middle section houses the CODEC power supply unit (including MIC input and LINEOUT output);

[0051] The lower center section houses the FEPHY differential signal power supply and ZQ calibration.

[0052] The right side contains the USB interface power supply and VBUS detection circuit;

[0053] Each module is isolated from the voltage regulator through independent filter capacitors (C0402, C0603), and the ePAD has a unified ground terminal.

[0054] This invention achieves independent power supply and dynamic power consumption control for the CPU core, audio codec, front-end physical layer, and USB interface through the coordinated operation of a power input module, a multi-power domain allocation module, an audio codec power supply module, a front-end physical layer power supply module, a USB interface power supply module, and a grounding module. The circuit employs zoned power regulation, filtering and noise reduction, single-point grounding, and power gating technologies to effectively reduce system standby power consumption and signal interference, making it suitable for highly integrated intelligent terminal devices.

[0055] This invention is applicable to electronic devices that integrate multiple external interfaces. It can simultaneously provide stable power to the processor core, audio codec, front-end physical layer, and USB interface, and achieve low-power operation. This invention provides stable voltage to the CPU core, audio codec module, front-end physical layer interface FEPHY, and USB interface through a unified power distribution architecture, and reduces the overall power consumption of the system through partitioned power management, filtering and noise reduction, and low-power control technology.

[0056] The above description is merely a preferred embodiment of this utility model. It should be noted that those skilled in the art can make various improvements and modifications without departing from the principle of this utility model, and these improvements and modifications should also be considered within the scope of protection of this utility model. Structures, devices, and operating methods not specifically described or explained in this utility model, unless otherwise specified or limited, shall be implemented using conventional methods in the field.

Claims

1. A low-power power management circuit integrating multiple interfaces, characterized in that: include: Power input module, multi-power domain distribution module, audio codec power supply module, front-end physical layer power supply module, USB interface power supply module, and grounding module; The power input module is used to receive external power and output various voltage signals, including VDD_ARM0, VDD_0V90, VCC_DDR0, VCC_1V8_Codec and VCC_1V8. The multi-power domain allocation module is connected to the output terminal of the power input module, and distributes the voltage signal to the CPU core power supply unit and the DDR power supply unit. The CPU core power supply unit includes CPU_DVDD connected to VDD_ARM0, and is grounded through a filter circuit composed of resistor R22 and capacitor C0402. The DDR power supply unit includes DDR_VDDQ_1, DDR_VDDQ_2, DDR_VDDQ_3 and DDR_PLL_AVDD1V8 connected to VDD_0V90 and VCC_DDR0. The DDR_PLL_AVDD1V8 outputs 1.8V to the clock circuit through an independent voltage regulator. The audio codec power supply module, connected to VCC_1V8_Codec, includes a main voltage regulation module and an audio interface module. The main voltage regulation module generates CPU_DVDD, DVDD_1 to DVDD_7. The audio interface module includes a MIC input circuit, a LINEOUT output circuit, and a VMICBIAS bias circuit. The MIC input circuit couples external audio signals through capacitors C20, C21, and C24, and is grounded with a filter capacitor C0402. The LINEOUT output circuit connects to an external speaker through a coupling capacitor C0603. The VMICBIAS bias circuit outputs a stable bias voltage through a dedicated voltage regulator. The front-end physical layer power supply module includes: a differential signal power supply unit, which provides a 1.2V core voltage VPHY_AVDD3V3 to FEPHY_RXP / RXN and FEPHY_TXP / TXN, and connects the differential pairs through a matching resistor R0402; and a ZQ calibration unit, which connects to an external calibration resistor through the FEPHY_ZEXT pin to achieve impedance matching. The USB interface power supply module includes: a dual power input unit that receives AVDD1V8_USB and VCC_1V8, and automatically switches between primary and backup power supplies through the internal switch of SARAC_USB_AVDD1V8; a VBUS detection unit that monitors the bus voltage through the USB_VBUSETD_IN pin, which is pulled up to VCC_3V3 through resistor R2; and a filter protection unit with capacitors C28 and C29 connected in parallel at the input end, and ESD protection devices configured at the output end of USB_DP / DM. The grounding module includes an ePAD single-point grounding terminal for connecting digital ground, analog ground, and power ground.

2. The low-power power management circuit integrating multiple interfaces according to claim 1, characterized in that: The multi-power domain allocation module also includes: The PLL power supply unit provides an independent power supply for the PLL_DVDD9 and supports clock gating technology. Power gate switches are located at the output terminals of the CODEC, FEPHY, and USB interface power supply units, respectively, and dynamically cut off power supply to idle modules through the enable signal EN_PIN of the main control chip.

3. The low-power power management circuit integrating multiple interfaces according to claim 1, characterized in that: In the MIC input circuit of the audio codec power supply module, capacitor C0402, along with capacitors C20, C21, and C24, forms a two-stage filter network to filter out high-frequency noise; capacitor C0603 in the LINEOUT output circuit is used to isolate DC bias voltage.

4. The low-power power management circuit integrating multiple interfaces according to claim 1, characterized in that: In the dual power input module of the USB interface power supply module, AVDD1V8_USB and VCC_1V8 automatically select the high-priority power supply through a voltage comparator. The SARAC_USB_AVDD1V8 switch has a built-in overvoltage protection circuit that cuts off the circuit when the input voltage exceeds 1.8V±5%.

5. The low-power power management circuit integrating multiple interfaces according to claim 1, characterized in that: In the differential signal power supply module of the front-end physical layer power supply module, the resistance value of the matching resistor R0402 is 100Ω, which is used to optimize the rising and falling edge characteristics of FEPHY_RXP / RXN and FEPHY_TXP / TXN signals and reduce signal distortion.

6. The low-power power management circuit integrating multiple interfaces according to claim 1, characterized in that: The grounding module's ePAD grounding terminal adopts a large-area copper-clad structure and is connected to the grounding layer on the back of the PCB.

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