Logic board compatible with multiple refresh rates
By adding a connector subunit and a function switching unit to the logic board, the limitation that the logic board can only match one refresh rate is solved, and the logic board can be adapted to multiple refresh rates, thus improving its versatility.
Patent Information
- Authority / Receiving Office
- CN Β· China
- Patent Type
- Utility models(China)
- Current Assignee / Owner
- HUIZHOU GAOSHENGDA DISPLAY TECH CO LTD
- Filing Date
- 2025-06-18
- Publication Date
- 2026-07-14
Smart Images
Figure CN224501471U_ABST
Abstract
Description
Technical Field
[0001] This utility model relates to the field of liquid crystal display technology, and in particular to a logic board compatible with multiple refresh rates. Background Technology
[0002] In LCD displays, the logic board and the System-on-a-Chip (SoC) are two indispensable components. The logic board is the physical platform that carries the SoC and other hardware; the SoC is the core computing unit of the logic board, leading the hardware to cooperate with the logic board, and the two complement each other.
[0003] In related technologies, current logic boards adopt a one-to-one matching SOC mode, meaning that a logic board can only be matched with a SOC of one refresh rate, which has great limitations and is not very versatile. Utility Model Content
[0004] The purpose of this invention is to overcome the shortcomings of the existing technology and provide a logic board that is compatible with multiple refresh rates and can be adapted to SOCs with multiple refresh rates, thereby improving the versatility of the logic board.
[0005] The objective of this utility model is achieved through the following technical solution:
[0006] The first aspect of this application provides a logic board compatible with multiple refresh rates, comprising: a logic chip; a plug-in unit, the plug-in unit including a plurality of connector sub-units, the connector sub-units being provided with a plurality of LVDS signal channels, each of the LVDS signal channels being electrically connected to the logic chip; a function switching unit, the function switching unit being electrically connected to the logic chip; and a register unit, the register unit being electrically connected to the logic chip.
[0007] The number of connector sub-units is greater than or equal to two.
[0008] The logic chip is provided with several transmission pins, which are used to electrically connect to the LVDS signal channel.
[0009] The logic chip is equipped with an identification port.
[0010] The function switching unit includes a switch and a pull-up resistor. The first end of the switch is electrically connected to the identification port, and the second end of the switch is electrically connected to the first end of the pull-up resistor. The second end of the pull-up resistor is used for external power supply connection.
[0011] The switch includes a main body and several positions, with the positions respectively disposed on the main body.
[0012] The register unit includes several adjustment subunits, each of which is electrically connected to the logic chip.
[0013] The number of adjustment subunits is the same as the number of gears.
[0014] Compared with the prior art, the present invention has at least the following advantages:
[0015] By increasing the number of connector sub-units, and with each connector sub-unit having multiple LVDS channels, when the SOC is connected to the logic chip, the corresponding register unit switches the corresponding refresh rate adaptation software through the function switching unit, enabling the logic board to be compatible with multiple SOCs with different refresh rates and improving the versatility of the logic board. Attached Figure Description
[0016] To more clearly illustrate the technical solutions of the embodiments of this utility model, the accompanying drawings used in the embodiments will be briefly described below.
[0017] Figure 1 This is a schematic functional block diagram of a logic board compatible with multiple refresh rates in one embodiment of the present invention.
[0018] Figure 2 This is a circuit diagram of a logic board compatible with multiple refresh rates according to one embodiment of the present invention.
[0019] Figure 3 This is a schematic diagram of the switch in one embodiment of the present invention. Detailed Implementation
[0020] Embodiments of this application will now be described in more detail with reference to the accompanying drawings. While embodiments of this application are shown in the drawings, it should be understood that this application may be implemented in various forms and should not be limited to the embodiments set forth herein. Rather, these embodiments are provided to make this application more thorough and complete, and to fully convey the scope of this application to those skilled in the art.
[0021] It should be understood that although the terms "first," "second," "third," etc., may be used in this application to describe various information, this information should not be limited to these terms. These terms are only used to distinguish information of the same type from one another. For example, without departing from the scope of this application, first information may also be referred to as second information, and similarly, second information may also be referred to as first information. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more of that feature. In the description of this application, "multiple" means two or more, unless otherwise explicitly specified.
[0022] Unless otherwise expressly specified and limited, the terms "installation," "connection," "linking," and "fixing," etc., should be interpreted broadly. For example, they can refer to a fixed connection, a detachable connection, or an integral part; they can refer to a mechanical connection or an electrical connection; they can refer to a direct connection or an indirect connection through an intermediate medium; they can refer to the internal communication of two components or the interaction between two components. Those skilled in the art can understand the specific meaning of the above terms in this application according to the specific circumstances.
[0023] The current logic boards adopt a one-to-one matching SOC mode, that is, one logic board can only match one refresh rate SOC, which has great limitations and is not very universal.
[0024] To address the aforementioned issues, this application provides a logic board compatible with multiple refresh rates, capable of adapting to SOCs with various refresh rates, thereby improving the versatility of the logic board.
[0025] The technical solutions of the embodiments of this application are described in detail below with reference to the accompanying drawings.
[0026] See Figure 1 and Figure 2 A logic board compatible with multiple refresh rates includes: a logic chip 100, a plug-in unit 200, a function switching unit 300, and a register unit 400. The plug-in unit 200 includes several connector sub-units, each of which is provided with several LVDS signal channels, and each LVDS signal channel is electrically connected to the logic chip. The function switching unit 300 is electrically connected to the logic chip 100. The register unit 400 is electrically connected to the logic chip 100.
[0027] It should be noted that the logic chip 100 is a U902. The logic chip 100 uses hardware logic circuits and programmable logic to process display signals, control timing, and perform protocol conversion. The connector sub-units in the plug-in unit are connectors; the number of connector sub-units is greater than or equal to two, depending on the number of compatible SOCs. The function switching unit 300 performs switching functions. The register unit 400 stores the adapter software corresponding to different SOCs.
[0028] This application increases the number of connector sub-units, and each connector sub-unit has multiple LVDS channels. When the SOC is connected to the logic chip 100, the function switching unit 300 switches the corresponding register unit's adaptation software for different refresh rates, enabling the logic board to be compatible with multiple SOCs with different refresh rates and improving the logic board's versatility.
[0029] See Figure 2 In one embodiment, the logic chip 100 is provided with a plurality of transmission pins, which are used for electrical connection with the LVDS signal channel.
[0030] It should be noted that the transmission pin is used to match the LVDS signal channel, thereby enabling the transmission of LVDS signals. The transmission pin can be... Figure 2 CLV0N, CLV0P, etc.
[0031] See Figure 2 In one embodiment, the logic chip 100 is provided with an identification port.
[0032] It should be noted that the identification port is Figure 2 GPIO13 in the middle.
[0033] See Figure 2 and Figure 3 In one embodiment, the function switching unit 300 includes a switch K1 and a pull-up resistor. The first end of the switch K1 is electrically connected to the identification port, and the second end of the switch K1 is electrically connected to the first end of the pull-up resistor. The second end of the pull-up resistor is used for external power supply connection.
[0034] Specifically, the switch K1 includes a body 310 and several positions 320, with the positions 320 respectively disposed on the body 310.
[0035] Specifically, the register unit 400 includes several adjustment subunits, each of which is electrically connected to the logic chip.
[0036] Specifically, the number of adjustment sub-units is the same as the number of gears.
[0037] It should be noted that the adjustment subunit is designed to adapt to different refresh rate SOC software. Users can manually adjust the 320 level and switch the corresponding adjustment subunit by identifying the port to run the SOC software for that refresh rate, thus achieving compatibility of the same logic board with different refresh rates. For example, the adjustment subunit can be... Figure 2 CN304 and CN305.
[0038] The solution of this application has been described in detail above with reference to the accompanying drawings. In the above embodiments, the descriptions of each embodiment have different focuses; for parts not described in detail in a certain embodiment, please refer to the relevant descriptions of other embodiments. Those skilled in the art should also understand that the actions and modules involved in the specification are not necessarily essential to this application. Furthermore, it is understood that the steps in the method of this application embodiment can be adjusted, combined, and deleted according to actual needs, and the modules in the device of this application embodiment can be combined, divided, and deleted according to actual needs.
[0039] The various embodiments of this application have been described above. These descriptions are exemplary and not exhaustive, nor are they limited to the disclosed embodiments. Many modifications and variations will be apparent to those skilled in the art without departing from the scope and spirit of the described embodiments. The terminology used herein is chosen to best explain the principles, practical application, or improvement of the technology in the market, or to enable others skilled in the art to understand the embodiments disclosed herein.
Claims
1. A logic board compatible with multiple refresh rates, characterized in that, include: Logic chip; The plug-in unit includes several connector sub-units, each connector sub-unit being provided with several LVDS signal channels, and each LVDS signal channel being electrically connected to the logic chip. A function switching unit, which is electrically connected to the logic chip; A register unit, which is electrically connected to the logic chip.
2. The logic board compatible with multiple refresh rates according to claim 1, characterized in that, The number of connector sub-units is greater than or equal to two.
3. The logic board compatible with multiple refresh rates according to claim 1, characterized in that, The logic chip is provided with several transmission pins, which are used to electrically connect to the LVDS signal channel.
4. The logic board compatible with multiple refresh rates according to claim 2, characterized in that, The logic chip is equipped with an identification port.
5. The logic board compatible with multiple refresh rates according to claim 1, characterized in that, The function switching unit includes a switch and a pull-up resistor. The first end of the switch is electrically connected to the identification port, and the second end of the switch is electrically connected to the first end of the pull-up resistor. The second end of the pull-up resistor is used for external power supply connection.
6. The logic board compatible with multiple refresh rates according to claim 5, characterized in that, The switch includes a main body and several positions, with the positions respectively disposed on the main body.
7. The logic board compatible with multiple refresh rates according to claim 6, characterized in that, The register unit includes several adjustment subunits, each of which is electrically connected to the logic chip.
8. The logic board compatible with multiple refresh rates according to claim 7, characterized in that, The number of adjustment subunits is the same as the number of gears.