A semiconductor device and an electric appliance

Abstract

This application discloses a semiconductor device and an electrical appliance. The semiconductor device includes: a substrate; a first inverter section, a second inverter section, a power factor corrector, and a rectifier bridge disposed on the substrate; a carrier section disposed on the outer side of the substrate and spaced apart from the substrate in a first direction, the carrier section being a frame or a PCB; a first driver integrated circuit disposed on the carrier section and electrically connected to the first inverter section; a second driver integrated circuit disposed on the carrier section and electrically connected to the second inverter section; a PFC driver integrated circuit disposed on the carrier section and electrically connected to the power factor corrector; the substrate includes an insulating layer and a first conductive metal layer and a second conductive metal layer located on both sides of the insulating layer; the thickness of the insulating layer is H, the thickness of the first conductive metal layer is G1, the thickness of the second conductive metal layer is G2, and the thickness of the substrate is K; wherein, K = H + G1 + G2; H / G1 = 3.5~4.5, and / or, H / G2 = 3.5~4.5; H / K = 0.58~0.78. According to the technical solution of this application, the substrate has sufficient strength and is not easily cracked.

Description

Technical Field

[0001] This application relates to the field of semiconductor technology, and more specifically to a semiconductor device and electrical equipment. Background Technology

[0002] Currently, air conditioning control boards typically use discrete components, which may include components such as rectifier bridges, power factor correction (PFC), intelligent power modules (IPM) for compressors, and fan IPMs. These discrete components occupy a large layout area on the control board, resulting in a large overall size of the control board, which is not conducive to the miniaturization and lightweight design of the equipment.

[0003] Furthermore, in highly integrated packaging, the elongated insulating heat dissipation substrate is susceptible to damage such as cracking due to slight inconsistencies in the flatness of its bottom surface, minor stress, or uneven stress during use. Therefore, how to achieve miniaturization, reduce substrate damage rate, and decrease the number of component insertions in semiconductor devices such as power modules has become an urgent problem to be solved. Utility Model Content

[0004] The utility model description section introduces a series of simplified concepts, which will be further explained in detail in the detailed description section. This utility model description section is not intended to limit the key features and essential technical features of the claimed technical solution, nor is it intended to determine the scope of protection of the claimed technical solution.

[0005] To at least partially solve the above problems, according to a first aspect of this application, a semiconductor device is provided, comprising:

[0006] A substrate having a first pad region, a second pad region, a third pad region, and a fourth pad region arranged at intervals in a second direction;

[0007] The system comprises a first inverter section, a second inverter section, a power factor corrector, and a rectifier bridge, wherein the first inverter section, the second inverter section, the power factor corrector, and the rectifier bridge are respectively disposed in the first pad area, the second pad area, the third pad area, and the fourth pad area.

[0008] A support portion is disposed on the outer side of the substrate and spaced apart from at least a portion of the substrate in a first direction. The support portion is a frame or a PCB, and the first direction is perpendicular to the second direction.

[0009] A first driver integrated circuit is disposed on the carrier and electrically connected to the first inverter unit;

[0010] The second drive integrated circuit is disposed on the carrier and electrically connected to the second inverter unit;

[0011] The PFC driver integrated circuit is disposed on the carrier and electrically connected to the power factor corrector;

[0012] The substrate includes an insulating layer and a first conductive metal layer and a second conductive metal layer located on both sides of the insulating layer.

[0013] The thickness of the insulating layer is H, the thickness of the first conductive metal layer is G1, the thickness of the second conductive metal layer is G2, and the thickness of the substrate is K;

[0014] Where K = H + G1 + G2;

[0015] H / G1 = 3.5 to 4.5, and / or H / G2 = 3.5 to 4.5;

[0016] H / K = 0.58 to 0.78.

[0017] The above technical solution has the following advantages and benefits: by not placing the driver integrated circuit on the substrate, the substrate area can be reduced, the thermal impact on the driver integrated circuit can be reduced, and the probability of substrate damage can be reduced, resulting in high integration. In addition, by making H / G1 or G2 equal to 2.2 to 4.5 while H / K equal to 0.58 to 0.78, the substrate can have sufficient strength and is not easy to crack, and the heat dissipation of the substrate can also be avoided from being greatly affected, thereby improving the overall reliability of the semiconductor device.

[0018] In one embodiment, the thickness of the insulating layer is 0.8 mm to 1.2 mm; and / or,

[0019] The thickness of the first conductive metal layer is 0.2 mm to 0.3 mm; and / or,

[0020] The thickness of the second conductive metal layer is 0.2 mm to 0.3 mm; and / or,

[0021] The width of the bearing portion in the first direction is 7.5mm to 9.5mm; and / or,

[0022] The length of the bearing portion in the second direction is 70mm to 80mm.

[0023] The above technical solution has the following advantages and beneficial effects: by setting the thickness of the insulating layer, the thickness of the first conductive metal layer, and the thickness of the second conductive metal layer within the above range, the substrate can have sufficient strength and is not easy to crack; by setting the width of the support portion in the first direction and the length of the support portion in the second direction within the above range, the support portion can have suitable space to set the first driver integrated circuit, the second driver integrated circuit, and the PFC driver integrated circuit, thereby effectively reducing the substrate area.

[0024] In one embodiment, the semiconductor device further includes an encapsulating resin that encapsulates the first inverter, the second inverter, the power factor corrector, the rectifier bridge, at least a portion of the substrate, and a portion of the carrier.

[0025] The aspect ratio of the substrate is A;

[0026] The aspect ratio of the encapsulating resin is B;

[0027] The thickness of the encapsulating resin is M;

[0028] Where 3 < A < 4; and / or,

[0029] 2.2 < B < 3.2; and / or,

[0030] 5.4mm < M < 6.1mm; and / or,

[0031] 0.22 < K / M < 0.3.

[0032] The above technical solution has the following advantages and beneficial effects: the encapsulating resin can provide physical and electrical protection for at least part of the substrate, part of the carrier, the first inverter, the second inverter, the power factor corrector and the rectifier bridge encapsulated therein, so as to prevent damage to the device caused by external environmental impact and ensure the normal operation of the semiconductor device.

[0033] In one embodiment, the circumferential edge of the encapsulating resin is provided with a step, the step having a width of 1.5mm to 1.7mm and a height of 1.5mm to 1.7mm; and / or,

[0034] In the thickness direction of the substrate, the substrate and the support portion are spaced apart.

[0035] 1.1mm~1.65mm.

[0036] The above technical solution has the following advantages and benefits: it can effectively reduce creepage distance and / or effectively reduce interference.

[0037] In one embodiment, the first inverter unit is a wind turbine inverter unit;

[0038] The second inverter section is the compressor inverter section;

[0039] The area of ​​the second pad region is larger than that of the first pad region.

[0040] The above technical solution has the following advantages and beneficial effects: the fan inverter is set in the first pad area and the compressor inverter is set in the second pad area. By designing the area of ​​the second pad area to be larger than that of the first pad area, the current carrying capacity can be improved to meet the greater power requirements of the compressor, reduce line impedance and heat generation, and at the same time enhance heat dissipation performance, saving space and cost.

[0041] In one embodiment, the widths of the first pad region, the second pad region, the third pad region, and the fourth pad region are equal in the first direction;

[0042] The length of the first pad region in the second direction is L9;

[0043] The length of the second pad region in the second direction is L10;

[0044] The length of the third pad region in the second direction is L11;

[0045] The length of the fourth pad region in the second direction is L12;

[0046] Among them, 1.5*(L11+L12)<L9+L10<2*(L11+L12).

[0047] The above technical solution has the following advantages and beneficial effects: Since power factor correctors and rectifier bridges are respectively set on the third and fourth pad areas, and power factor correctors and rectifier bridges are high-temperature operating components, setting the area of ​​the pads where the fan inverter and compressor inverter are located within the above range can meet the requirements of sufficient heat dissipation without creating ineffective heat dissipation areas and wasting space, thereby enabling the miniaturization of semiconductor devices.

[0048] In one embodiment, the widths of the first pad region, the second pad region, the third pad region, and the fourth pad region are equal in the first direction;

[0049] The length of the first pad region in the second direction is L9;

[0050] The length of the second pad region in the second direction is L10;

[0051] The length of the substrate in the second direction is L8;

[0052] Among them, 0.58≤(L9+L10) / L8≤0.65.

[0053] The above technical solution has the following advantages and benefits: the fan inverter is set on the first pad area and the compressor inverter is set on the second pad area. By reasonably allocating the area of ​​the pad area, local heat concentration on the substrate can be avoided, the heat dissipation efficiency of the substrate can be improved, and the layout requirements of power switches and other circuits can be balanced under limited substrate size, so as to achieve a high degree of integration design.

[0054] In one embodiment, the first inverter unit is a fan inverter unit, and the second inverter unit is a compressor inverter unit;

[0055] The widths of the first pad region, the second pad region, the third pad region, and the fourth pad region are equal in the first direction;

[0056] The length of the first pad region in the second direction is L9;

[0057] The length of the second pad region in the second direction is L10;

[0058] The length of the third pad region in the second direction is L11;

[0059] The length of the fourth pad region in the second direction is L12;

[0060] Where L11+L12>L9, and / or L11+L12>L10.

[0061] The above technical solution has the following advantages and beneficial effects: power factor correctors and rectifier bridges are provided on the third and fourth pad areas. By setting the area of ​​the pad area where the power factor corrector and rectifier bridge are located to be larger than the area of ​​the pad area where the fan inverter is located, and also larger than the area of ​​the pad area where the compressor inverter is located, it is possible to ensure uniform heat distribution on the substrate, prevent material aging or performance degradation due to heat concentration, reduce interference to sensitive circuits, and improve the reliability of the device.

[0062] In one embodiment, the widths of the third pad region and the fourth pad region are equal in the first direction;

[0063] The length of the third pad region in the second direction is L11;

[0064] The length of the fourth pad region in the second direction is L12;

[0065] Among them, L12 > L11.

[0066] The above technical solution has the following advantages and beneficial effects: power factor correctors and rectifier bridges are set on the third and fourth pad areas. By setting the area of ​​the pad area where the rectifier bridge is located to be larger than the area of ​​the pad area where the power factor corrector is located, more chips can be set in the pad area where the rectifier bridge is located, thus enabling compatibility with modules of various current specifications.

[0067] This application also provides an electrical device that includes the aforementioned semiconductor device.

[0068] The above technical solution has the following advantages and beneficial effects: Since the electrical device includes the aforementioned semiconductor device, it has the same advantages as the aforementioned semiconductor device. Attached Figure Description

[0069] The following drawings, which are incorporated herein by reference and are used to understand this application, illustrate embodiments of the invention and their descriptions, thereby explaining the apparatus and principles of the invention.

[0070] Figure 1 A top view of the semiconductor device in the Z direction is shown in an embodiment of this application.

[0071] Figure 2 A top view of the semiconductor device with device designations in the Z direction is shown in the embodiment of this application.

[0072] Figure 3 A top view schematic diagram of the first inverter section in the semiconductor device according to an embodiment of this application is shown.

[0073] Figure 4 A top view schematic diagram of the second inverter section in the semiconductor device according to an embodiment of this application is shown.

[0074] Figure 5 A schematic diagram of the structure of a substrate in a semiconductor device according to an embodiment of this application is shown.

[0075] Figure 6 A top view schematic diagram of a driver integrated circuit in a semiconductor device according to an embodiment of this application is shown.

[0076] Figure 7 A top view schematic diagram of a driver integrated circuit in a semiconductor device according to an embodiment of this application is shown.

[0077] Figure 8 A top view schematic diagram of a driver integrated circuit in a semiconductor device according to an embodiment of this application is shown.

[0078] Figure 9 A top view schematic diagram of a driver integrated circuit in a semiconductor device according to an embodiment of this application is shown.

[0079] Figure 10 A schematic diagram of the structure of a semiconductor device in an embodiment of this application is shown.

[0080] Figure 11 A cross-sectional schematic diagram of a semiconductor device in an embodiment of this application is shown.

[0081] Figure 12 A top view schematic diagram of each pad region in the semiconductor device in an embodiment of this application is shown.

[0082] Figure 13 A top view schematic diagram of the first pad region in the semiconductor device according to an embodiment of this application is shown.

[0083] Figure 14 A top view schematic diagram of the second pad region in the semiconductor device according to an embodiment of this application is shown.

[0084] Figure 15 A top view schematic diagram of the third pad region in the semiconductor device according to an embodiment of this application is shown.

[0085] Figure 16 A top view schematic diagram of the fourth pad region in the semiconductor device according to an embodiment of this application is shown.

[0086] Figure label:

[0087] 100. Semiconductor devices;

[0088] 102. First driving integrated circuit; 1021. First low-voltage driving integrated circuit; 1022. First high-voltage driving integrated circuit;

[0089] 103. First inverter section; 1031. First low-voltage power-side inverter circuit element; 1032. First high-voltage power-side inverter circuit element;

[0090] 202. Second driver integrated circuit; 2021. Second low-voltage driver integrated circuit; 2022. Second high-voltage driver integrated circuit;

[0091] 203. Second inverter section; 2031. Second low-voltage power-side inverter circuit element; 2032. Second high-voltage power-side inverter circuit element;

[0092] 302. PFC driver integrated circuit; 303. Power factor corrector;

[0093] 401. Rectifier bridge;

[0094] 500. Substrate;

[0095] 501, First pad area; 5011, First low-voltage power side pad; 5012, First high-voltage side power pad;

[0096] 502, Second pad area; 5021, Second low-voltage power side pad; 5022, Second high-voltage side power pad;

[0097] 503, Third pad area; 504, Fourth pad area;

[0098] 510. Insulating layer; 520. First conductive metal layer; 503. Second conductive metal layer;

[0099] 600. Bearing unit;

[0100] 601, First drive-side pad; 6011, First low-voltage drive-side pad; 6012, First high-voltage drive-side pad;

[0101] 602, First driver-side pin;

[0102] 603, Second drive side pad; 6031, Second low-voltage drive side pad; 6032, Second high-voltage drive side pad;

[0103] 604, Second driver-side pin; 605, Third driver-side pin; 606, Fourth driver-side pin;

[0104] 609. Third drive side pad;

[0105] 700 - Encapsulating resin, 710 - Step. Detailed Implementation

[0106] The following description provides numerous specific details to offer a more thorough understanding of this application. However, it will be apparent to those skilled in the art that this application can be practiced without one or more of these details. In other instances, certain technical features well-known in the art have not been described to avoid confusion with this application.

[0107] It should be understood that this application can be implemented in various forms and should not be construed as being limited to the embodiments set forth herein. Rather, providing these embodiments will make the disclosure thorough and complete, and will fully convey the scope of this application to those skilled in the art. In the drawings, for clarity, the dimensions and relative dimensions of layers and regions may be exaggerated. The same reference numerals denote the same elements throughout.

[0108] It should be understood that although the terms first, second, third, etc., may be used to describe various elements, components, areas, layers, and / or parts, these elements, components, areas, layers, and / or parts should not be limited by these terms. These terms are only used to distinguish one element, component, area, layer, or part from another element, component, area, layer, or part. Therefore, without departing from the teachings of this application, the first element, component, area, layer, or part discussed below may be referred to as the second element, component, area, layer, or part.

[0109] Spatial relation terms such as "below," "under," "below," "under," "above," and "above" are used here for convenience to describe the relationship between one element or feature shown in the figure and other elements or features. It should be understood that, in addition to the orientation shown in the figure, spatial relation terms are intended to also include different orientations of devices in use and operation.

[0110] The terminology used herein is for the purpose of describing particular embodiments only and is not intended to limit the scope of this application. When used herein, the singular forms “a,” “an,” and “ / the” are also intended to include the plural forms unless the context clearly indicates otherwise. It should also be understood that the terms “compose” and / or “comprising,” when used in this specification, identify the presence of features, integers, steps, operations, elements, and / or components, but do not exclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and / or groups. When used herein, the term “and / or” includes any and all combinations of the associated listed items.

[0111] Embodiments of the utility model are described herein with reference to cross-sectional views that serve as schematic diagrams of preferred embodiments (and intermediate structures) of this application. Thus, variations in the shown shape can be anticipated due to, for example, manufacturing techniques and / or tolerances. Therefore, embodiments of this application should not be limited to the specific shapes shown herein, but include shape deviations due to, for example, manufacturing processes. Consequently, the figures are substantially schematic, and their shapes are not intended to show the actual shape of the device and are not intended to limit the scope of this application.

[0112] To fully understand this utility model, detailed steps and structures will be presented in the following description to illustrate the technical solution proposed in this application. Preferred embodiments of this application are described in detail below; however, in addition to these detailed descriptions, this application may have other embodiments.

[0113] Below, we will refer to the appendix. Figures 1 to 16A semiconductor device 100 according to an embodiment of this application will be described. In order to ensure the clarity of the views, some structural reference numerals may be omitted in some of the drawings. These reference numerals can be obtained by referring to other drawings. Without conflict, the various technical features in the embodiments of this application can be combined with each other.

[0114] The semiconductor device 100 includes a substrate 500, a first inverter section 103, a second inverter section 203, a power factor corrector 303, a rectifier bridge 401, a carrier section 600, a first driver integrated circuit 102, a second driver integrated circuit 202, and a PFC driver integrated circuit 302.

[0115] The substrate 500 has a first pad region 501, a second pad region 502, a third pad region 503 and a fourth pad region 504 arranged at intervals in a second direction.

[0116] The first inverter 103, the second inverter 203, the power factor corrector 303, and the rectifier bridge 401 are respectively disposed in the first pad region 501, the second pad region 502, the third pad region 503, and the fourth pad region 504.

[0117] The support portion 600 is disposed on the outer side of the substrate 500 and spaced apart from the substrate 500 in a first direction. For example, the support portion 600 can be a frame or a PCB (Printed Circuit Board), with the first direction perpendicular to the second direction.

[0118] A first driver integrated circuit 102 is disposed on the support portion 600 and electrically connected to the first inverter portion 103. A second driver integrated circuit 202 is disposed on the support portion 600 and electrically connected to the second inverter portion 203. A PFC driver integrated circuit 302 is disposed on the support portion 600 and electrically connected to the power factor corrector 303.

[0119] The substrate 500 includes an insulating layer 510 and a first conductive metal layer 520 and a second conductive metal layer 530 located on both sides of the insulating layer 510. The first inverter 103, the second inverter 203, the power factor corrector 303, and the rectifier bridge 401 can be disposed on the first conductive metal layer 520 or on the second conductive metal layer 530.

[0120] The thickness of the insulating layer 510 is H, the thickness of the first conductive metal layer 520 is G1, the thickness of the second conductive metal layer 530 is G2, and the thickness of the substrate 500 is K. In this embodiment, K = H + G1 + G2; H / G1 = 3.5 ~ 4.5 (that is, 3.5 ≤ H / G1 ≤ 4.5), and / or, H / G2 = 3.5 ~ 4.5 (that is, 3.5 ≤ H / G2 ≤ 45); H / K = 0.58 ~ 0.78 (that is, 0.58 ≤ H / K ≤ 0.78).

[0121] In highly integrated packaging, elongated insulating heat dissipation substrates are susceptible to damage during use, even with slight inconsistencies in the flatness of the substrate's bottom surface or under slight or uneven stress. In this embodiment, by omitting the driver integrated circuit from the substrate 500, the area of ​​the substrate 500 can be reduced, minimizing the thermal impact on the driver integrated circuit and lowering the probability of substrate 500 damage, resulting in high integration. Furthermore, by ensuring that H / G1 or G2 equals 3.5 to 4.5 while H / K equals 0.58 to 0.78, the elongated insulating heat dissipation substrate 500 achieves sufficient strength and is less prone to cracking, while also preventing significant impact on heat dissipation, thereby improving the overall reliability of the semiconductor device 100.

[0122] It should be noted that, Figure 1 The dashed boxes in the diagram are only used to illustrate the relative positional distribution of the first inverter unit 103, the second inverter unit 203, the power factor corrector 303, and the rectifier bridge 401, and are not intended to limit the structural dimensions of each integrated object or the devices contained therein.

[0123] For example, such as Figure 2 As shown, three-dimensional space is represented using a Cartesian coordinate system. The first direction can be the Y-axis, or it can be described as the vertical direction or the width direction. The second direction can be the X-axis, or it can be described as the horizontal direction or the length direction. The first direction is perpendicular to the second direction. Furthermore, as... Figure 2 The dashed line shown in the diagram has the drive side and power side on either side in the first direction. In the following description, the names of various devices will be distinguished from the perspective of the power side and the drive side; these names are not intended to be necessary limitations on the structure or characteristics of the corresponding devices.

[0124] The substrate 500 has a first side and a second side disposed opposite to each other. The first inverter 103, the second inverter 203, the power factor corrector 303, and the rectifier bridge 401 can be disposed on the first side of the substrate 500. Specifically, the first side of the substrate 500 has multiple pad areas, and multiple circuit elements included in the first inverter 103, the second inverter 203, the power factor corrector 303, and the rectifier bridge 401 are disposed on various corresponding pad areas. The substrate 500 can support the first inverter 103, the second inverter 203, the power factor corrector 303, and the rectifier bridge 401, and the substrate 500 has good thermal conductivity, which can improve the heat dissipation effect of the various components on the substrate 500. The pad areas on the first side of the substrate 500 can be used to bring out the various components on the substrate 500 for electrical connection with other components.

[0125] Optionally, the substrate 500 can also be a PCB (printed circuit board). The PCB can be a substrate 500 that forms electrical connections between electronic components by patterning conductive copper foil on the surface of an insulating material (such as fiberglass, epoxy resin, etc.). The PCB achieves electrical connections between electronic components through these copper foil lines and supports the components to be fixed on the board.

[0126] In some embodiments, such as Figure 2 and Figure 12 As shown, the substrate 500 has a first pad region 501, a second pad region 502, a third pad region 503, and a fourth pad region 504 arranged at intervals in a second direction. Specifically, the second direction is the aforementioned X-axis direction, which can also be described as the horizontal direction. The order in which the first pad region 501, the second pad region 502, the third pad region 503, and the fourth pad region 504 are arranged at intervals in the second direction can be arbitrarily adjusted. For example, the arrangement order in the second direction could be the first pad region 501, the second pad region 502, the third pad region 503, and the fourth pad region 504, or the second pad region 502, the first pad region 501, the third pad region 503, and the fourth pad region 504, or the fourth pad region 504, the first pad region 501, the second pad region 502, and the third pad region 503, etc., without specific limitation. The adjustable arrangement order of the different pad regions enhances flexibility and improves usability. For example, the first pad region 501, the second pad region 502, the third pad region 503 and the fourth pad region 504 are located in the first conductive metal layer 520.

[0127] For example, the first inverter 103, the second inverter 203, the power factor corrector 303, and the rectifier bridge 401 are respectively disposed in the first pad region 501, the second pad region 502, the third pad region 503, and the fourth pad region 504. Wherein, as Figure 3 As shown, the first pad area 501 may include a first low-voltage power side pad 5011 and a first high-voltage power side pad 5012, and the first inverter section 103 may include a first low-voltage power side inverter circuit element 1031 and a first high-voltage power side inverter circuit element 1032. Specifically, the first low-voltage power side inverter circuit element 1031 may be disposed on the first low-voltage power side pad 5011, and the first high-voltage power side inverter circuit element 1032 may be disposed on the first high-voltage power side pad 5012.

[0128] Among them, such as Figure 4 As shown, the second pad region 502 may include a second low-voltage power side pad 5021 and a second high-voltage side power pad 5022, and the second inverter section 203 may include a second low-voltage power side inverter circuit element 2031 and a second high-voltage power side inverter circuit element 2032. Specifically, the second low-voltage power side inverter circuit element 2031 may be disposed on the second low-voltage power side pad 5021, and the second high-voltage power side inverter circuit element 2032 may be disposed on the second high-voltage power side pad 5022.

[0129] By partitioning the first inverter unit 103, the second inverter unit 203, the power factor corrector 303, and the rectifier bridge 401, a highly integrated and high-performance power module design can be achieved, which is suitable for efficient power control systems for home appliances such as air conditioners.

[0130] In some embodiments, such as Figure 5 As shown, the substrate 500 includes an insulating layer 510 and a first conductive metal layer 520 and a second conductive metal layer 530 located on both sides of the insulating layer 510. The first conductive metal layer 520 is disposed on a first surface of the insulating layer 510, and the second conductive metal layer 530 is disposed on a second surface of the insulating layer 510. The surface of the first conductive metal layer 520 away from the insulating layer 510 constitutes at least a portion of the first surface of the substrate 500, and the surface of the second conductive metal layer 530 away from the insulating layer 510 constitutes at least a portion of the second surface of the substrate 500. The insulating layer 510 can be a thermally conductive ceramic or polymer material to provide electrical isolation and thermal conductivity; the first conductive metal layer 520 and the second conductive metal layer 530 can be metallic materials, such as one or more of copper, aluminum, silver, gold, tin, etc., for efficient heat dissipation and temperature reduction. For example, the material of the conductive metal layer includes copper.

[0131] For example, the thickness of the insulating layer 510 is set ( Figure 5The thickness of the first conductive metal layer 520 is G1, the thickness of the second conductive metal layer 530 is G2, and the thickness of the substrate 500 is K. Wherein, the thickness K of the substrate 500 is equal to H+G1+G2 (that is, the sum of the thicknesses of the insulating layer 510, the first conductive metal layer 520, and the second conductive metal layer 530), the numerical range of H / G1 (that is, the ratio of the thickness of the insulating layer 510 to the thickness of the first conductive metal layer 520) and H / G2 (that is, the ratio of the thickness of the insulating layer 510 to the thickness of the second conductive metal layer 530) is 3.5 to 4.5, for example, H / G1 is 3.5, 3.8, 4.1 or 4.5, H / G2 is 3.5, 3.8, 4.1 or 4.5, and the numerical range of H / K (that is, the ratio of the thickness of the insulating layer 510 to the thickness of the substrate 500) is 0.58 to 0.78, for example, H / K is 0.58, 0.6, 0.65, 0.7 or 0.78. In highly integrated packaging, the elongated insulating heat dissipation substrate is prone to cracking and damage during use due to slight inconsistencies in the flatness of the substrate bottom surface, slight stress, or uneven stress. At the same time, an excessively thick insulating layer 510 of the substrate 500 can affect heat dissipation. By setting the substrate to meet the range of H / G1 and H / G2 of 3.5 to 4.5, while the value of H / K is 0.58 to 0.78, the elongated insulating heat dissipation substrate 500 can be made strong enough to prevent cracking, and the heat dissipation of the substrate 500 can be prevented from being significantly affected, thereby improving the reliability of the semiconductor device 100.

[0132] For example, the thickness of the insulating layer 510 is 0.8 mm to 1.2 mm; and / or, the thickness of the first conductive metal layer 520 is 0.2 mm to 0.3 mm; and / or, the thickness of the second conductive metal layer 530 is 0.2 mm to 0.3 mm. By setting the thicknesses of the insulating layer 510, the first conductive metal layer 520, and the second conductive metal layer 530 within the aforementioned ranges, the substrate can have sufficient strength and is less prone to cracking. Simultaneously, the bonding between the encapsulating resin 700 and the substrate 500 is ensured, preventing peeling between the two.

[0133] In some embodiments, such as Figure 2As shown, the support portion 600 is disposed on the outer side of the substrate 500 and spaced apart from at least a portion of the substrate 500 in a first direction. Specifically, the first direction is the aforementioned Y-axis direction, which can also be described as the vertical direction. The support portion 600 is independent of the outer side of the substrate 500 and maintains a certain distance from at least a portion of the substrate in the vertical direction. By not disposing of the support portion 600 on the substrate 500, the area of ​​the substrate 500 can be reduced, and the probability of damage to the substrate 500 can be decreased, resulting in high integration. Exemplarily, the support portion 600 can be a frame or a PCB, wherein the material of the frame can be metal or plastic, without specific limitation. Exemplarily, the PCB does not have a ceramic carrier but has a substrate conventional for PCBs, such as FR1 to FR5, where FR4 and FR5 (both are glass fiber reinforced epoxy resins) are commonly used.

[0134] For example, the width of the carrier portion 600 in the first direction (the width at its widest point in the first direction) is 7.5 mm to 9.5 mm; and / or, the length of the carrier portion 600 in the second direction (the length at its longest point in the second direction) is 70 mm to 80 mm. By setting the size of the carrier portion 600 within the above range, on the one hand, the carrier portion 600 can have suitable space to accommodate the first driver integrated circuit 102, the second driver integrated circuit 202, the PFC driver integrated circuit 302, and the fourth driver-side pin 606 electrically connected to the rectifier bridge 401, thereby effectively reducing the area of ​​the substrate 500. On the other hand, the size of the carrier portion 600 is not so large that it would cause the semiconductor device to be too large.

[0135] The support portion 600 includes a first sub-support portion and a second sub-support portion. For example... Figure 2 As shown, dashed box A1 indicates the basic range corresponding to the carrier portion 600, dashed box A2 indicates the basic range corresponding to the first sub-carrier portion, and dashed box A3 indicates the basic range corresponding to the second sub-carrier portion. It should be noted that, since integrated circuits are mostly irregularly shaped, Figure 2 The dashed boxes A1, A2, A3, and other dashed boxes mentioned later are only used to indicate general locations and are not intended to limit the corresponding carrier portions. The carrier portion 600 is disposed on the outer side of the substrate 500 and is spaced apart from the substrate 500 in the first direction. The carrier portion 600 may include a plurality of drive-side pads, and the carrier portion 600 may also include a plurality of drive-side pins.

[0136] Specifically, the first sub-carrier portion may include a first driving-side pad 601 and a plurality of first driving-side pins 602. For example, Figure 2As shown, the first driving-side pad 601 can be two, namely a first low-voltage driving-side pad 6011 and a first high-voltage driving-side pad 6012. The second sub-carrier includes a second driving-side pad 603 and a plurality of second driving-side pins 604. Figure 2 As shown, there can be two second drive side pads 603, namely a second low-voltage drive side pad 6031 and a second high-voltage drive side pad 6032.

[0137] The number of first drive-side pins 602 (such as the pins within the dashed box A2) corresponding to the first inverter unit 103 is multiple. The number of second drive-side pins 604 (such as the pins within the dashed box A3) corresponding to the second inverter unit 203 is multiple. Each pin of the multiple first drive-side pins 602 and each pin of the multiple second drive-side pins 604 are spaced apart in the first direction.

[0138] In some embodiments, such as Figure 2 and Figure 3 As shown, a first driver integrated circuit 102 is disposed on the carrier portion 600 and electrically connected to the first inverter portion 103. The first driver integrated circuit 102 may include a first low-voltage driver integrated circuit 1021 and a first high-voltage driver integrated circuit 1022. The first inverter portion 103 may include a first low-voltage power-side inverter circuit element 1031 and a first high-voltage power-side inverter circuit element 1032. The first driver integrated circuit 102 may be disposed on a first driver-side pad 601. Specifically, the first low-voltage driver integrated circuit 1021 may be disposed on the first low-voltage driver-side pad 6011, and the first high-voltage driver integrated circuit 1022 may be disposed on the second high-voltage driver-side pad 6032.

[0139] For example, the first driver integrated circuit 102 is electrically connected to the first inverter unit 103. Specifically, the first low-voltage driver integrated circuit 1021 and the first low-voltage power-side inverter circuit element 1031 are electrically connected via leads, or via jumper pads; this is not specifically limited. Correspondingly, the first high-voltage driver integrated circuit 1022 and the first high-voltage power-side inverter circuit element 1032 are electrically connected via leads, or via jumper pads; this is not specifically limited.

[0140] Furthermore, the first driver integrated circuit 102 is electrically connected to at least a portion of the pins of a plurality of first driver-side pins 602. For example... Figure 3As shown in the figure, the multiple pins shown within the dashed box A5 are multiple first drive-side pins 602. Specifically, the first high-voltage drive integrated circuit 1022 and the first low-voltage drive integrated circuit 1021 may be connected to at least one of the first drive-side pins 602 via leads.

[0141] In some embodiments, such as Figure 2 and Figure 4 As shown, a second driver integrated circuit 202 is disposed on the carrier portion 600 and electrically connected to the second inverter portion 203. The second driver integrated circuit 202 may include a second low-voltage driver integrated circuit 2021 and a second high-voltage driver integrated circuit 2022. The second inverter portion 203 may include a second low-voltage power-side inverter circuit element 2031 and a second high-voltage power-side inverter circuit element 2032. The second driver integrated circuit 202 may be disposed on the second driver-side pad 603. Specifically, the second low-voltage driver integrated circuit 2021 may be disposed on the second low-voltage driver-side pad 6031, and the second high-voltage driver integrated circuit 2022 may be disposed on the second high-voltage driver-side pad 6032.

[0142] For example, the second driver integrated circuit 202 is electrically connected to the second inverter section 203. Specifically, the second low-voltage driver integrated circuit 2021 and the second low-voltage power-side inverter circuit element 2031 are electrically connected via leads, or via jumper pads; this is not specifically limited. Correspondingly, the second high-voltage driver integrated circuit 2022 and the second high-voltage power-side inverter circuit element 2032 are electrically connected via leads, or via jumper pads; this is not specifically limited.

[0143] Furthermore, the second driver integrated circuit 202 is electrically connected to at least a portion of a plurality of second driver-side pins 604. For example... Figure 4 As shown in the dashed box A6, the multiple pins within the dashed box A6 are the second driver-side pins 604.

[0144] In some embodiments, the carrier 600 is further provided with a PFC driver integrated circuit 302 and electrically connected to a power factor corrector 303. Specifically, the carrier 600 also includes a third sub-carrier (e.g., Figure 2The third sub-carrier portion (within the dashed box A4) includes a third driving-side pad 609, and further includes multiple third driving-side pins 605. A PFC driver integrated circuit 302 is disposed on the third driving-side pad 609. The PFC driver integrated circuit 302 can be directly electrically connected to the power factor corrector 303 via leads, or it can be electrically connected to the power factor corrector 303 via jumper pads; no specific limitation is made in this regard. The multiple third driving-side pins 605 corresponding to the power factor corrector 303 (such as the pins within the dashed box A4) can also be spaced apart in the first direction. Furthermore, the PFC driver integrated circuit 302 is electrically connected to at least a portion of the multiple third driving-side pins 605, for example, via leads.

[0145] In some embodiments, the carrier 600 is further provided with two drive-side pins 606 electrically connected to the rectifier bridge 401.

[0146] By incorporating a driver integrated circuit and driver-side pins in the carrier section 600, high integration can be achieved, the number of components can be reduced, the overall size can be minimized, and the semiconductor device structure can be made more compact. Furthermore, heat dissipation can be enhanced, improving the stability and reliability of the semiconductor device.

[0147] Specifically, such as Figure 6 As shown, in some embodiments, the first driver integrated circuit 102, the second driver integrated circuit 202, and the PFC driver integrated circuit 302 can be integrated onto the same driver chip. The first driver integrated circuit 102 is electrically connected to the first inverter section 103, the second driver integrated circuit 202 is electrically connected to the second inverter section 203, and the PFC driver integrated circuit 302 is electrically connected to the power factor corrector 303. In this case, the first inverter section 103, the second inverter section 203, and the power factor corrector 303 are arranged adjacent to each other in the second direction, and the rectifier bridge 401 can be disposed at the left and right ends in the second direction.

[0148] like Figure 7As shown, in some embodiments, the first driver integrated circuit 102, the second driver integrated circuit 202, and the PFC driver integrated circuit 302 are respectively disposed on different driver chips. For example, the first driver integrated circuit 102 is disposed on the first driver chip, the second driver integrated circuit 202 is disposed on the second driver chip, and the PFC driver integrated circuit 302 is disposed on the third driver chip. The first driver integrated circuit 102 is electrically connected to the first inverter section 103, the second driver integrated circuit 202 is electrically connected to the second inverter section 203, and the PFC driver integrated circuit 302 is electrically connected to the power factor corrector 303. In this case, the arrangement order of the first inverter section 103, the second inverter section 203, the power factor corrector 303, and the rectifier bridge 401 in the second direction can be arbitrarily adjusted.

[0149] like Figure 8 As shown, in some embodiments, the first driver integrated circuit 102 is disposed on the first driver chip, and the second driver integrated circuit 202 and the PFC driver integrated circuit 302 are disposed on the second driver chip. The first driver integrated circuit 102 is electrically connected to the first inverter section 103, the second driver integrated circuit 202 is electrically connected to the second inverter section 203, and the PFC driver integrated circuit 302 is electrically connected to the power factor corrector 303. In this case, the second inverter section 103 and the power factor corrector 303 are arranged adjacent to each other in the second direction, and the arrangement order of the first inverter section 103 and the rectifier bridge 401 in the second direction can be arbitrarily adjusted.

[0150] like Figure 9As shown, in some embodiments, the first driver integrated circuit 102 can be disposed on different driver chips. The first driver integrated circuit 102 may include a first low-voltage driver integrated circuit 1021 and a first high-voltage driver integrated circuit 1022. The first low-voltage driver integrated circuit 1021 is disposed on a first driver chip, and the first high-voltage driver integrated circuit 1022 is disposed on a second driver chip, or multiple first high-voltage driver integrated circuits 1022 are disposed on multiple second driver chips. Similarly, the second driver integrated circuit 202 can also be disposed on different driver chips. The second driver integrated circuit 202 may include a second low-voltage driver integrated circuit 2021 and a second high-voltage driver integrated circuit 2022. The second low-voltage driver integrated circuit 2021 is disposed on a third driver chip, and the second high-voltage driver integrated circuit 2022 is disposed on a fourth driver chip, or multiple second high-voltage driver integrated circuits 2022 are disposed on multiple fourth driver chips. The PFC driver integrated circuit 302 is disposed on a fifth driver chip. The first driver integrated circuit 102 is electrically connected to the first inverter section 103, the second driver integrated circuit 202 is electrically connected to the second inverter section 203, and the PFC driver integrated circuit 302 is electrically connected to the power factor corrector 303. At this time, the arrangement order of the first inverter section 103, the second inverter section 203, the power factor corrector 303, and the rectifier bridge 401 in the second direction can be arbitrarily adjusted.

[0151] In some embodiments, such as Figure 2 , Figure 10 and Figure 11 As shown, the semiconductor device 100 also includes an encapsulating resin 700, which is used to encapsulate the first inverter 103, the second inverter 203, the power factor corrector 303, the rectifier bridge 401, at least a portion of the substrate 500, a portion of the carrier portion 600, and driver integrated circuits (e.g., the first driver integrated circuit 102, the second driver integrated circuit 202, and the PFC driver integrated circuit 302). Exemplarily, the encapsulating resin 700 is obtained by molded encapsulation, which can be generated, for example, using a thermosetting resin through transfer molding. The encapsulating resin can be epoxy resin or other resin materials suitable for semiconductor module encapsulation. The encapsulating resin can provide physical and electrical protection to the first inverter 103, the second inverter 203, the power factor corrector 303, the rectifier bridge 401, at least a portion of the substrate 500, a portion of the carrier portion 600, and the driver integrated circuits encapsulated therein, ensuring the normal operation of the semiconductor device 100. For example, the surface of the second conductive metal layer 530 away from the insulating layer 510 is at least partially exposed to the encapsulating resin 700.

[0152] For example, the main material of the insulating layer 510 can be an AlN ceramic insulating layer, an Al2O3 ceramic insulating layer, or a Si3N4 ceramic insulating layer. The substrate 500 can be a direct-bonded ceramic substrate (DBC).

[0153] In some embodiments, the aspect ratio (the ratio of length in the second direction to width in the first direction) of the substrate 500 is A, the aspect ratio of the encapsulating resin 700 is B, and the thickness of the semiconductor device 100 is M. Wherein, 3 < A < 4, and / or, 2.2 < B < 3.2, and / or, 5.4 mm < M < 6.1 mm; and / or, 0.22 < K / M < 0.3.

[0154] That is, when the aspect ratio A of the substrate 500 and the aspect ratio B of the encapsulation resin 700 module are within the above range, both the substrate 500 and the encapsulation resin 700 are long and thin strips, which are easy to warp and easy to peel off. By controlling the thickness of both within the above range, the strength of the substrate 500 can be ensured, the warping of the substrate 500 can be reduced, the bonding between the substrate 500 and the encapsulation resin 700 can be enhanced, and the heat dissipation requirements can be met.

[0155] See appendix Figure 11 In this embodiment, a step 710 is provided on the circumferential edge of the encapsulating resin 700. The width D1 of the step 710 is 1.5mm to 1.7mm, and the height D2 of the step is 1.5mm to 1.7mm. The width D1 of the step 710 is also the step 710 being perpendicular to the thickness direction of the encapsulating resin (see attached figure). Figure 11 The width of the plane (in the left-right direction) along its extension direction, and the height D2 of the step 710 is the distance of this plane in the thickness direction of the encapsulating resin to the end face of the encapsulating resin 700 adjacent to it. One end of the encapsulating resin 700 exposes a portion of the substrate 500, and the side of the encapsulating resin 700 exposes the pins in the carrier portion 600. The step is located between the exposed substrate 500 and the pins. By setting the step size within the above range, the creepage distance can be effectively increased while ensuring that the semiconductor device has more encapsulating resin 700 to ensure insulation. In the thickness direction of the substrate 500 (i.e., Figure 11 In the left-right direction (as shown in the diagram), the substrate 500 and the support portion 600 are spaced 1.1mm to 1.65mm apart, that is, the distance D3 between the substrate 500 and the support portion 600 is 1.1mm to 1.65mm. For example, the distance D3 between the substrate 500 and the support portion 600 can be 1.1mm, 1.25mm, 1.35mm, 1.45mm, 1.65mm, etc. By setting it to the above-mentioned distance, interference between the two can be effectively reduced, improving the operational stability and reliability of the semiconductor device.

[0156] In some embodiments, the first inverter unit 103 can be a fan inverter unit, and the second inverter unit 203 can be a compressor inverter unit. The first inverter unit 103 is disposed on a first pad region 501, and the second inverter unit 203 is disposed on a second pad region 502. The area of ​​the second pad region 502 is larger than the area of ​​the first pad region 501, meaning the area of ​​the fan inverter unit is smaller than the area of ​​the compressor inverter unit. By designing the area of ​​the compressor inverter unit to be larger than that of the fan inverter unit, the current carrying capacity can be improved to accommodate the greater power requirements of the compressor, reducing line impedance and heat generation, while also enhancing heat dissipation performance and saving space and cost. For example, in this embodiment, the widths of the first pad region 501 and the second pad region 502 in the first direction are equal, and the length of the second pad region 502 in the second direction is greater than the length of the first pad region 501 in the second direction.

[0157] In some embodiments, such as Figure 12 As shown, the widths of the first pad region 501, the second pad region 502, the third pad region 503, and the fourth pad region 504 are equal in the first direction. Exemplarily, the first inverter 103 is disposed in the first pad region 501, the second inverter 203 is disposed in the second pad region 502, the power factor corrector 303 is disposed in the third pad region 503, and the rectifier bridge 401 is disposed in the fourth pad region 504. Specifically, using a Cartesian coordinate system to represent three-dimensional space, the first direction can be the Y-axis direction, or it can be described as the vertical direction or the width direction. In this embodiment, the first inverter 103 can be a fan inverter, and the second inverter 203 can be a compressor inverter; that is, the widths of the pad regions where the fan inverter, compressor inverter, power factor corrector 303, and rectifier bridge 401 are located are the same in the vertical direction.

[0158] For example, such as Figures 13-16As shown, the length of the first pad area 501 in the second direction is set to L9, the length of the second pad area 502 in the second direction is set to L10, the length of the third pad area 503 in the second direction is set to L11, and the length of the fourth pad area 504 in the second direction is set to L12. The second direction can be the X-axis direction, or it can be said to be the horizontal or length direction. The first direction is perpendicular to the second direction. That is, the horizontal lengths of the pad areas of the fan inverter, compressor inverter, power factor corrector 303, and rectifier bridge 401 are respectively L9, L10, L11, and L12, and simultaneously satisfy the condition 1.5*(L11+L12)<L9+L10<2*(L11+L12). Since the power factor corrector 303 and the rectifier bridge 401 are respectively provided on the third pad area 503 and the fourth pad area 504, and the power factor corrector 303 and the rectifier bridge 401 are high-temperature operating components, setting the area of ​​the pads where the fan inverter and the compressor inverter are located within the above range can meet the requirements of sufficient heat dissipation without creating ineffective heat dissipation areas and wasting space, thus enabling the miniaturization of semiconductor devices.

[0159] In some embodiments, such as Figures 12-14 As shown, the widths of the first pad region 501, the second pad region 502, the third pad region 503, and the fourth pad region 504 are equal in the first direction, that is, the widths of the pad regions where the fan inverter, the compressor inverter, the power factor corrector 303, and the rectifier bridge 401 are located are the same in the longitudinal direction. For example, the length of the first pad area 501 in the second direction is set to L9, the length of the second pad area 502 in the second direction is set to L10, and the length of the substrate 500 in the second direction is set to L8. That is, the lengths of the pad areas of the fan inverter, the compressor inverter, and the substrate 500 in the second direction are L9, L10, and L8, respectively, and simultaneously satisfy the condition 0.58≤(L9+L10) / L8≤0.65. By reasonably allocating the pad area of ​​the fan inverter and the compressor inverter, local heat concentration of the substrate 500 can be avoided, the heat dissipation efficiency of the substrate 500 can be improved, and the layout requirements of the power switch and other circuits can be balanced within the limited substrate size, thus achieving a high degree of integration design.

[0160] In some embodiments, such as Figures 12-16As shown, the widths of the first pad region 501, the second pad region 502, the third pad region 503, and the fourth pad region 504 in the first direction are equal. At the same time, the lengths of the first pad region 501, the second pad region 502, the third pad region 503, and the fourth pad region 504 in the second direction are L9, L10, L11, and L12, respectively. That is, the lengths of the pad regions where the fan inverter, the compressor inverter, the power factor corrector 303, and the rectifier bridge 401 are located in the lateral direction are L9, L10, L11, and L12, respectively, and the conditions L11+L12>L9 and L11+L12>L10 are satisfied simultaneously. Power factor correctors and rectifier bridges are installed on the third pad area 503 and the fourth pad area 504. Since the power factor corrector 303 and rectifier bridge 401 are high-temperature operating components, their small area cannot meet the heat dissipation requirements. By setting the area of ​​the pad area where the power factor corrector 303 and rectifier bridge 401 are located to be larger than the area of ​​the pad area where the fan inverter is located, and also larger than the area of ​​the pad area where the compressor inverter is located, it is possible to ensure that the heat of the substrate 500 is evenly distributed, prevent material aging or performance degradation due to heat concentration, reduce interference to sensitive circuits, and improve the reliability of the devices.

[0161] In some embodiments, the widths of the third pad region 503 and the fourth pad region 504 are equal in the longitudinal direction (i.e., the first direction). The length of the third pad region in the transverse direction (i.e., the second direction) is L11, and the length of the fourth pad region 504 in the transverse direction is L12. It is also necessary to satisfy L12 > L11, meaning the area of ​​the pad region where the rectifier bridge 401 is located is greater than the area of ​​the pad region where the power factor corrector 303 is located. By setting the area of ​​the pad region where the rectifier bridge 401 is located to be greater than the area of ​​the pad region where the power factor corrector 303 is located, more chips can be placed in the pad region where the rectifier bridge 401 is located, thus enabling compatibility with modules of various current specifications.

[0162] In some embodiments, the first inverter unit 103 and the second inverter unit 203 may include inverter circuit elements. These inverter circuit elements may include multiple power switching devices. The power switching devices may include metal-oxide-semiconductor field-effect transistors (MOS) or insulated-gate bipolar transistors (IGBTs). The IGBT modules may be reverse-conducting insulated-gate bipolar transistors (RC-IGBTs), or IGBTs and fast recovery diodes (FRDs), or other suitable types of power switching devices. For example, taking RC-IGBTs as the inverter circuit elements, the number of RC-IGBTs may be multiple, such as three high-voltage power-side RC-IGBTs and three low-voltage power-side RC-IGBTs constituting the inverter. Specifically, the number of RC-IGBTs can be reasonably set according to actual needs.

[0163] In some embodiments, the power factor corrector 303 is used to improve the power factor by bringing the current and voltage phases closer together and reducing ineffective power. It includes power switching devices. Specifically, the power factor corrector 303 may include an IGBT module, which can be an RC-IGBT or an IGBT and FRD. The power factor corrector 303 may also include a MOS, or other suitable types of power switching devices, without specific limitation.

[0164] In another aspect of this application, an electrical device is also provided, which includes the aforementioned semiconductor device. This electrical device can include household appliances such as electric fans, air conditioners, kitchen range hoods, high-speed hair dryers, washing machines, etc., and the semiconductor device can be used in the motor drive system of these household appliances. The electrical device can also be a new energy vehicle, industrial automation equipment, switching power supply, etc.

[0165] Semiconductor devices can be used in equipment such as air conditioners, taking air conditioners as an example.

[0166] The rectifier bridge 401 in an air conditioner converts alternating current (AC) to direct current (DC). It is typically used in the power supply section to provide DC voltage to subsequent circuits such as the power factor correction (PFC) unit 303 and the inverter. It includes diodes and other auxiliary components. For example, the input of the rectifier bridge 401 is connected to the AC power supply, and its output is connected to the input of the PFC unit 303. Exemplarily, a rectifier bridge 401 is composed of multiple rectifier diodes, such as four spaced-apart rectifier diodes. This four-diode rectifier bridge converts the input AC power into DC power for output.

[0167] The power factor corrector 303 is used to improve the power factor by bringing the current and voltage phases closer together and reducing ineffective power. It includes power switching devices, such as insulated-gate bipolar transistors (IGBTs), for controlling the current waveform, and diodes for rectification. It receives the DC voltage output from the rectifier bridge 401 and, by controlling the current waveform, makes the input current and voltage in phase, thereby improving the power factor and reducing ineffective power and harmonic interference. The DC voltage output by the PFC is typically boosted to a higher stable value (e.g., 400V DC) to supply power to the subsequent inverter section. The input terminal of the power factor corrector 303 is connected to the output terminal of the rectifier bridge 401, and the output terminal of the power factor corrector 303 is connected to the DC bus of the first inverter section 103 (e.g., a fan inverter section) and the second inverter section 203 (a compressor inverter section). For example, the power factor corrector 303 includes a PFC power switch chip and a PFC diode. The PFC power switch and PFC diode are components of the PFC circuit, which adjusts the power factor of the DC power supply and outputs the adjusted DC power. The PFC power switch chip can be composed of an insulated gate bipolar transistor (IGBT) and a freewheeling diode (FRD), or it can be a metal-oxide-semiconductor field-effect transistor (MOS), or it can be an RC-IGBT (a reverse-conducting IGBT that integrates the IGBT and freewheeling diode onto a single chip).

[0168] The first inverter unit 103 is typically used to drive the indoor and outdoor fan motors of the air conditioner. The first inverter unit 103 may include a fan inverter unit, which includes multiple power switching devices, such as IGBT modules or metal-oxide-semiconductor field-effect transistors (MOSFETs). The input terminal of the fan inverter unit is connected to a DC bus (shared with the output terminal of the PFC and the second inverter unit 203). The output terminal of the fan is connected to the fan motor. The fan converts DC power into variable frequency AC power to drive the indoor and outdoor fan motors of the air conditioner, thereby controlling the fan speed.

[0169] The second inverter unit 203 is used to drive the air conditioner compressor and has a higher power output. The second inverter unit 203 may include a compressor inverter unit, which includes power switching devices, such as IGBT modules. The IGBT module integrates multiple IGBTs and freewheeling diodes, or it may include multiple RC-IGBTs. The compressor inverter unit is connected in parallel with the fan inverter unit and also obtains power from the DC bus. The input terminal of the compressor inverter unit is connected to the DC bus, and the output terminal is connected to the compressor motor. The compressor inverter unit converts DC power into AC power of a variable frequency to drive the air conditioner compressor motor. By controlling the power switching devices (such as IGBT modules) in the inverter unit, the frequency and voltage of the output AC power are adjusted, thereby controlling the compressor speed and cooling / heating capacity. For example, the first inverter unit 103 and the second inverter unit 203 may be composed of multiple inverter power chips; for example, a three-phase inverter bridge circuit may be composed of six inverter power chips. The three-phase inverter bridge circuit includes three-phase upper arm inverter power chips and three-phase lower arm inverter power chips. The inverter power chip can be composed of an insulated gate bipolar transistor (IGBT) and a freewheeling diode (FRD), or it can be a metal-oxide-semiconductor field-effect transistor (MOS), or it can be an RC-IGBT (a reverse-conducting IGBT that integrates the IGBT and the freewheeling diode into a single chip).

[0170] Since the electrical device of this application has the aforementioned semiconductor device, it also has the advantages of the aforementioned semiconductor device.

[0171] Although exemplary embodiments have been described herein with reference to the accompanying drawings, it should be understood that the above exemplary embodiments are merely illustrative and are not intended to limit the scope of this application. Various changes and modifications can be made therein by those skilled in the art without departing from the scope and spirit of this application. All such changes and modifications are intended to be included within the scope of this application as claimed in the appended claims.

[0172] Numerous specific details are set forth in the specification provided herein. However, it will be understood that embodiments of this application may be practiced without these specific details. In some instances, well-known methods, structures, and techniques have not been shown in detail so as not to obscure the understanding of this specification.

[0173] Similarly, it should be understood that, in order to streamline this application and aid in understanding one or more of the various inventive aspects, features of this application may sometimes be grouped together in a single embodiment, figure, or description thereof in the description of exemplary embodiments of this application. However, this approach should not be construed as reflecting an intention that the claimed application requires more features than are expressly recited in each claim. Rather, as reflected in the corresponding claims, its inventive point lies in solving the corresponding technical problem with features fewer than all features of a single disclosed embodiment. Therefore, the claims following the detailed description are hereby expressly incorporated into that detailed description, wherein each claim itself is a separate embodiment of this application.

[0174] Those skilled in the art will understand that, apart from the mutual exclusion of features, all features disclosed in this specification (including the accompanying claims, abstract, and drawings) and all processes or elements of any method or apparatus so disclosed can be combined in any combination. Unless otherwise expressly stated, each feature disclosed in this specification (including the accompanying claims, abstract, and drawings) may be replaced by an alternative feature serving the same, equivalent, or similar purpose.

[0175] Furthermore, those skilled in the art will understand that although some embodiments herein include certain features included in other embodiments but not others, combinations of features from different embodiments are intended to be within the scope of this application and form different embodiments. For example, in the claims, any of the claimed embodiments can be used in any combination.

[0176] It should be noted that the above embodiments are illustrative of this application and not restrictive of this application, and that those skilled in the art can devise alternative embodiments without departing from the scope of the appended claims.

Claims

1. A semiconductor device, characterized in that, include: A substrate having a first pad region, a second pad region, a third pad region, and a fourth pad region arranged at intervals in a second direction; The system comprises a first inverter section, a second inverter section, a power factor corrector, and a rectifier bridge, wherein the first inverter section, the second inverter section, the power factor corrector, and the rectifier bridge are respectively disposed in the first pad area, the second pad area, the third pad area, and the fourth pad area. A support portion is disposed on the outer side of the substrate and spaced apart from at least a portion of the substrate in a first direction. The support portion is a frame or a PCB, and the first direction is perpendicular to the second direction. A first driver integrated circuit is disposed on the carrier and electrically connected to the first inverter unit; The second drive integrated circuit is disposed on the carrier and electrically connected to the second inverter unit; The PFC driver integrated circuit is disposed on the carrier and electrically connected to the power factor corrector; The substrate includes an insulating layer and a first conductive metal layer and a second conductive metal layer located on both sides of the insulating layer. The thickness of the insulating layer is H, the thickness of the first conductive metal layer is G1, the thickness of the second conductive metal layer is G2, and the thickness of the substrate is K; Where K = H + G1 + G2; H / G1 = 3.5 to 4.5, and / or H / G2 = 3.5 to 4.5; H / K = 0.58 to 0.

78.

2. The semiconductor device as claimed in claim 1, characterized in that, The thickness of the insulating layer is 0.8 mm to 1.2 mm; and / or, The thickness of the first conductive metal layer is 0.2 mm to 0.3 mm; and / or, The thickness of the second conductive metal layer is 0.2 mm to 0.3 mm; and / or, The width of the bearing portion in the first direction is 7.5mm to 9.5mm; and / or, The length of the bearing portion in the second direction is 70mm to 80mm.

3. The semiconductor device as claimed in claim 1, characterized in that, The semiconductor device further includes an encapsulating resin that encapsulates the first inverter section, the second inverter section, the power factor corrector, the rectifier bridge, at least a portion of the substrate, and a portion of the carrier section. The aspect ratio of the substrate is A; The aspect ratio of the encapsulating resin is B; The thickness of the encapsulating resin is M; Where 3 < A < 4; and / or, 2.2 < B < 3.2; and / or, 5.4mm < M < 6.1mm; and / or, 0.22 < K / M < 0.

3.

4. The semiconductor device as claimed in claim 3, characterized in that, The encapsulating resin has a step along its circumferential edge, the step having a width of 1.5mm to 1.7mm and a height of 1.5mm to 1.7mm; and / or, In the thickness direction of the substrate, the substrate and the support portion are spaced 1.1 mm to 1.65 mm apart.

5. The semiconductor device as claimed in claim 1, characterized in that, The first inverter unit is a wind turbine inverter unit; The second inverter section is a compressor inverter section; The area of ​​the second pad region is larger than the area of ​​the first pad region.

6. The semiconductor device as claimed in claim 1, characterized in that, The widths of the first pad region, the second pad region, the third pad region, and the fourth pad region are equal in the first direction; The length of the first pad region in the second direction is L9; The length of the second pad region in the second direction is L10; The length of the third pad region in the second direction is L11; The length of the fourth pad region in the second direction is L12; Among them, 1.5*(L11+L12)<L9+L10<2*(L11+L12).

7. The semiconductor device as claimed in claim 1, characterized in that, The widths of the first pad region, the second pad region, the third pad region, and the fourth pad region are equal in the first direction; The length of the first pad region in the second direction is L9; The length of the second pad region in the second direction is L10; The length of the substrate in the second direction is L8; Among them, 0.58≤(L9+L10) / L8≤0.

65.

8. The semiconductor device as claimed in claim 1, characterized in that, The first inverter unit is a fan inverter unit, and the second inverter unit is a compressor inverter unit; The widths of the first pad region, the second pad region, the third pad region, and the fourth pad region are equal in the first direction; The length of the first pad region in the second direction is L9; The length of the second pad region in the second direction is L10; The length of the third pad region in the second direction is L11; The length of the fourth pad region in the second direction is L12; Where L11+L12>L9, and / or L11+L12>L10.

9. The semiconductor device as claimed in claim 1, characterized in that, The widths of the third pad region and the fourth pad region are equal in the first direction; The length of the third pad region in the second direction is L11; The length of the fourth pad region in the second direction is L12; Among them, L12 > L11.

10. An electrical appliance, characterized in that, The semiconductor device includes any one of claims 1-9.

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