A synchronous rectification control device and a flyback power charging system

Abstract

The utility model relates to a kind of synchronous rectification control device and flyback power charging system, including the transformer of receiving input voltage and generating output voltage, transformer primary winding connection primary side field effect tube's drain, transformer secondary winding connection secondary side field effect tube's drain, secondary side field effect tube is also connected with the synchronous rectification control device of built-in one sharp peak absorption circuit.The sharp peak absorption circuit is triggered after secondary side field effect tube is turned off, for absorbing the voltage sharp peak energy generated by the drain of secondary side field effect tube.The utility model sets up sharp peak absorption circuit in synchronous rectification control device, the drain voltage sharp peak generated by secondary side field effect tube is absorbed to ground or chip reference ground or absorption conversion other energy, reduce sharp peak voltage, improve reliability and stability.

Description

TECHNICAL FIELD

[0001] The utility model relates to flyback power supply technical field especially is involved in a kind of synchronous rectification control device and flyback power charging system. BACKGROUND

[0002] With the requirement of electronic product to charging power and charging efficiency is higher and higher, flyback power supply topology as common charging solution, more and more support CCM (Continuous Conduction Mode, continuous conduction mode) operating mode. The main advantage of this mode is to reduce system size, improve charging efficiency and power density. In addition, in flyback power supply, more and more in the primary side adopts the third generation power semiconductor device GaN FET (Gallium Nitride Field Effect Transistor, Gallium Nitride Field Effect Transistor), using GaN FET parasitic capacitance smaller advantage than traditional silicon-based MOSFET (Metal Oxide Semiconductor Field Effect Transistor, Metal Oxide Semiconductor Field Effect Transistor), realize higher switching frequency, so as to further reduce the size of transformer, improve power density.

[0003] When flyback system works in CCM mode, as shown in Figure 1 and Figure 2 , primary FET and secondary MOSFET are turned on alternately. When primary MOSFET or GaN FET is turned on, synchronous rectification chip needs to turn off secondary MOSFET in time, otherwise there will be a situation that primary FET and secondary MOSFET are turned on at the same time, when secondary MOSFET is completely turned off, voltage peak stress is too high, and even damages secondary MOSFET and leads to system explosion.

[0004] However, in flyback circuit, due to the isolation of transformer, primary controller chip and secondary synchronous rectification controller chip cannot transmit signals directly. Synchronous rectification controller chip usually adopts the way of detecting VD voltage to turn off secondary MOSFET. When synchronous rectification chip detects that VD voltage is zero or positive, it means that primary MOSFET or GaN FET has been turned on, and after comparison delay and drive transmission delay of comparator, secondary synchronous rectification controller chip turns off secondary MOSFET. Therefore, during comparison delay and drive transmission delay of comparator, there is a situation that primary FET and secondary MOSFET are turned on together, which leads to voltage stress peak after secondary MOSFET is turned off. The longer the above comparison delay and drive delay time is, the higher the voltage peak stress is.

[0005] Therefore, there is an urgent need to design a synchronous rectification control device and a flyback power supply charging system capable of absorbing voltage spikes, improving system reliability and stability. Utility model content

[0006] The utility model wants to solve the technical problem to provide a synchronous rectification control device charging system and flyback power supply charging system, it can absorb voltage spikes, improve system reliability and stability.

[0007] In order to solve the above technical problem, the utility model provides a synchronous rectification control device, including synchronous rectification module and the drive circuit of connecting the synchronous rectification module, the synchronous rectification module includes peak absorption circuit, the peak absorption circuit is triggered after the off of the secondary side field effect tube, for absorbing the voltage peak energy generated by the drain of the secondary side field effect tube, the peak absorption circuit is clamping peak absorption circuit or pulse peak absorption circuit or pulse LDO peak absorption circuit,

[0008] The clamping peak absorption circuit includes the first switch absorption module for opening absorption and disconnecting absorption voltage peak energy and the clamping circuit for clamping the highest voltage of the first switch absorption module and control the opening and disconnection of the first switch absorption module,

[0009] The pulse peak absorption circuit includes the pulse time module for generating periodic pulse signal, the buffer circuit for buffering the pulse signal and the second switch absorption module for opening absorption and disconnecting absorption voltage peak energy according to the pulse signal, which are connected in series,

[0010] The pulse LDO peak absorption circuit includes the pulse time circuit for generating periodic pulse signal and the LDO circuit for absorbing the voltage peak energy and converting into stable output voltage VCC after receiving the pulse signal, which are connected to the pulse time circuit, and the output voltage VCC is in slow decline state.

[0011] Further, the first switch absorption module of the clamping peak absorption circuit includes MOS tube M1, and the clamping circuit includes capacitor C1, resistor R1 and clamping diode D1.

[0012] The gate of the MOS tube M1 is connected to one end of the capacitor C1, the resistor R1 and the negative electrode of the clamping diode D1, the drain is connected to the drain of the secondary side field effect tube and the other end of the capacitor C1, and the source is grounded or connected to the chip reference ground and the positive electrode of the resistor R1 and the clamping diode D1.

[0013] Further, the buffer circuit of the pulse peak absorption circuit includes buffer BUF1 and buffer BUF2, and the second switch absorption module includes MOS tube M4.

[0014] One end of the pulse time module is connected to the gate of the secondary side field effect tube, and the other end is connected to the input end of the buffer BUF1;

[0015] The output end of the buffer BUF1 is connected to the input end of the buffer BUF2;

[0016] The output end of the buffer BUF2 is connected to the gate of the MOS tube M4;

[0017] The drain of the MOS tube M4 is connected to the drain of the secondary side field effect tube, and the source is grounded or the chip reference ground.

[0018] Further, the clamping diode D1 can be replaced by the MOS tube M2;

[0019] The source of the MOS tube M2 is connected to the gate of the MOS tube M1 and one end of the resistor R1, the drain is grounded or the chip reference ground and connected to the source of the MOS tube M1 and the other end of the resistor R1, and the gate is connected to the first reference voltage Vref1; the MOS tube M2 is used to clamp the gate voltage Vg_M1 of the MOS tube M1 at the sum of the first reference voltage Vref1 and the turn-on threshold voltage Vth of the MOS tube M2.

[0020] Further, the pulse time module includes a buffer BUF3, a resistor R4, a NOT gate NOT1, a NOR gate NOR1 and a capacitor C2;

[0021] The input end of the buffer BUF3 is connected to the gate of the secondary side field effect tube and one input end of the NOR gate NOR1, and the output end is connected to the resistor R4;

[0022] One end of the resistor R4 is connected to the buffer BUF3, and the other end is connected to the capacitor C2 and the input end of the NOT gate NOT1;

[0023] The input end of the NOT gate NOT1 is connected to the resistor R4 and the capacitor C2, and the output end is connected to the other input end of the NOR gate NOR1;

[0024] One input end of the NOR gate NOR1 is connected to the input end of the buffer BUF3 and the gate of the secondary side field effect tube, the other input end is connected to the output end of the NOT gate NOT1, and the output end is connected to the input end of the buffer BUF1.

[0025] Further, the pulse time circuit comprises a pulse time unit connected to the gate of the secondary side field effect tube, and an OR gate OR1 connected to the LDO circuit; an output end of the pulse time unit is connected to one input end of the OR gate OR1; an output end and another input end of the OR gate OR1 are connected to the LDO circuit;

[0026] The LDO circuit comprises an LDO gate voltage module connected to the output end of the OR gate OR1, a MOS tube M3, a diode D2, a resistor R2, a resistor R3, and a comparator CMP1;

[0027] The gate of the MOS tube M3 is connected to the output end of the LDO gate voltage module, the drain is connected to the drain of the secondary side field effect tube, and the source is connected to the anode of the diode D2;

[0028] The cathode of the diode D2 is connected to one end of the resistor R2; the output voltage VCC is output between the cathode of the diode D2 and the resistor R2;

[0029] One end of the resistor R2 is connected to the output voltage VCC and the cathode of the diode D2, and the other end is connected to the resistor R3 and the inverting input end of the comparator CMP1;

[0030] One end of the resistor R3 is connected to the resistor R2 and the inverting input end of the comparator CMP1, and the other end is grounded;

[0031] The non-inverting input end of the comparator CMP1 is connected to a second reference voltage Vref2, the inverting input end is connected to the resistor R2 and the resistor R3, and the output end is connected to the other input end of the OR gate OR1; the second reference voltage Vref2 serves as a reference comparison voltage for turning on the LDO gate voltage module.

[0032] Further, the pulse time unit comprises a buffer BUF3, a resistor R4, a NOT gate NOT1, a NOR gate NOR1, and a capacitor C2;

[0033] The input end of the buffer BUF3 is connected to the gate of the secondary side field effect tube FET2 and one input end of the NOR gate NOR1, and the output end is connected to the resistor R4;

[0034] One end of the resistor R4 is connected to the buffer BUF3, and the other end is connected to the capacitor C2 and the NOT gate NOT1;

[0035] The input end of the NOT gate NOT1 is connected to the resistor R4 and the capacitor C2, and the output end is connected to the other input end of the NOR gate NOR1;

[0036] One input terminal of the NOR gate NOR1 is connected with the input terminal of the buffer BUF3 and the gate of the secondary side field effect transistor FET2, the other input terminal is connected with the output terminal of the NOT gate NOT1, and the output terminal is connected with one input terminal of the OR gate OR1.

[0037] Further, the capacitor C1 is the parasitic capacitor of the MOS transistor M1, or the sum of the parasitic capacitor and other equivalent capacitors.

[0038] Further, the clamping peak absorption circuit and the pulse peak absorption circuit absorb the voltage peak generated by the drain of the secondary side field effect transistor to the ground or the chip reference ground.

[0039] The pulse LDO peak absorption circuit transfers the voltage peak generated by the drain of the secondary side field effect transistor to the output voltage VCC.

[0040] To solve the above technical problems, the utility model also provides a flyback power charging system including the synchronous rectification control device, including receiving input voltage Vin and generating output voltage Vout transformer, the transformer primary winding connects the drain of the primary side field effect transistor, the transformer secondary winding connects the drain of the secondary side field effect transistor;

[0041] The gate of the primary side field effect transistor is connected with the primary side controller, and the source is grounded.

[0042] The gate of the secondary side field effect transistor is connected with the synchronous rectification control device, and the source is grounded and connected with the load module.

[0043] One end of the load module is connected with the source of the secondary side field effect transistor, and the other end is connected with the transformer secondary winding and the output voltage Vout.

[0044] Compared with the prior art, the utility model has the beneficial effects that: the utility model sets up the peak absorption circuit in the synchronous rectification control device, absorbs the drain voltage peak generated by the secondary side field effect transistor to the ground or the chip reference ground or absorbs and converts into other energy, reduces the peak voltage, improves the reliability and stability. BRIEF DESCRIPTION OF DRAWINGS

[0045] In order to further disclose the specific technical content of the case, first, please refer to the drawings, wherein:

[0046] Figure 1 It is the flyback power charging system circuit structure diagram of prior art;

[0047] Figure 2 It is the primary side controller and secondary side synchronous rectification key signal schematic diagram of prior art in CCM mode;

[0048] Figure 3 is a synchronous rectification control device circuit structure diagram of the embodiment of the utility model;

[0049] Figure 4 is the structure diagram of the first kind of clamping peak absorption circuit of the first embodiment of the utility model;

[0050] Figure 5 is the structure diagram of the second kind of clamping peak absorption circuit of the first embodiment of the utility model;

[0051] Figure 6 is Figure 4 and Figure 5 the peak absorption waveform schematic diagram of the clamping peak absorption circuit of

[0052] Figure 7 is the structure diagram of the pulse peak absorption circuit of the second embodiment of the utility model;

[0053] Figure 8 is Figure 7 the peak absorption waveform schematic diagram of the pulse peak absorption circuit of

[0054] Figure 9 is the structure diagram of the pulse LDO peak absorption circuit of the third embodiment of the utility model;

[0055] Figure 10 is Figure 9 the circuit structure diagram of the pulse time circuit and LDO circuit of

[0056] Figure 11 is Figure 7 the circuit structure diagram of the pulse time module of Figure 10 and the pulse time unit of

[0057] Figure 12 is the peak absorption waveform schematic diagram of the pulse LDO peak absorption circuit of the third embodiment of the utility model. DETAILED DESCRIPTION

[0058] The technical scheme in the embodiments of the utility model will be described below with reference to the drawings of the utility model.

[0059] The flyback power supply charging system provided by the embodiment of the utility model comprises a transformer T1 receiving an input voltage Vin and generating an output voltage Vout, a primary winding of the transformer T1 is connected with a drain of a primary side field effect transistor FET1, and a secondary winding of the transformer T1 is connected with a drain of a secondary side field effect transistor FET2.

[0060] Specifically, a gate of the primary side field effect transistor FET1 is connected with a primary side controller, and a source is grounded.

[0061] The gate of the secondary side field effect transistor FET2 is connected with the synchronous rectification control device, and the source is grounded and connected with the load module.

[0062] One end of the load module is connected with the source of the secondary side field effect transistor FET2, and the other end is connected with the secondary side winding of the transformer T1 and the output voltage Vout.

[0063] Reference Figure 3 The synchronous rectification control device comprises a synchronous rectification module and a driving circuit connected with the synchronous rectification module.

[0064] The synchronous rectification module comprises a spike absorption circuit, which is triggered after the secondary side field effect transistor FET2 is turned off, and is used for absorbing the voltage spike energy generated by the drain of the secondary side field effect transistor FET2.

[0065] The driving circuit is used for receiving the turn-off signal output by the synchronous rectification module, generating a turn-off driving signal capable of controlling the turn-off of the secondary side field effect transistor of the controllable flyback power supply charging system, and receiving the turn-on signal output by the synchronous rectification module, generating a turn-on driving signal capable of controlling the turn-on of the secondary side field effect transistor of the controllable flyback power supply charging system.

[0066] The utility model embodiment provides three kinds of spike absorption circuits, which are clamping spike absorption circuit, pulse spike absorption circuit and pulse LDO (Low Dropout Regulator, low dropout regulator) spike absorption circuit.

[0067] Reference Figure 4 In the embodiment, the first clamping spike absorption circuit comprises a first switch absorption module for turning on and turning off the absorption of the voltage spike energy and a clamping circuit for clamping the maximum voltage of the first switch absorption module and controlling the turning on and turning off of the first switch absorption module. The first switch absorption module comprises a MOS tube M1, and the clamping circuit comprises a capacitor C1, a resistor R1 and a clamping diode D1.

[0068] The gate of the MOS tube M1 is connected with one end of the capacitor C1, the resistor R1 and the negative electrode of the clamping diode D1, the drain is connected with the drain of the secondary side field effect transistor FET2 and the other end of the capacitor C1, and the source is grounded or connected with the chip reference ground and the positive electrode of the resistor R1 and the clamping diode D1.

[0069] Specifically, the clamping diode D1 in the circuit is used for clamping the maximum voltage Vg_M1 of the gate of the MOS tube M1, so as to avoid that the voltage Vg_M1 is coupled too high and damages the gate of the MOS tube M1.

[0070] In addition, in the circuit, the capacitor C1 can be the parasitic capacitance of the MOS tube M1, or the sum of the parasitic capacitance and other equivalent capacitances.

[0071] When the synchronous rectification control device works in CCM mode and the secondary side field effect tube FET2 is also turned off, the drain voltage VD_SR rises rapidly to generate a voltage spike, as shown in Fig. Figure 6 At this time, the capacitor C1 of the spike absorption circuit couples the voltage spike to a high level, turns on the MOS tube M1, absorbs the voltage spike energy, and thus reduces the influence of the voltage spike. When the drain voltage VD_SR of the secondary side field effect tube FET2 no longer rises rapidly, the gate voltage of the MOS tube M1 is always low through the pull-down action of the resistor R1 of the spike absorption circuit, and then the MOS tube M1 is turned off, so that the energy of the drain voltage VD_SR of the secondary side field effect tube FET2 cannot be absorbed.

[0072] Referring to Figure 5 , the second clamping spike absorption circuit of the embodiment replaces the clamping diode D1 with a MOS tube M2. The source of the MOS tube M2 is connected to the gate of the MOS tube M1 and one end of the resistor R1, the drain is grounded or connected to the chip reference ground and the other end of the resistor R1 connected to the source of the MOS tube M1, and the gate is connected to the first reference voltage Vref1; the MOS tube M2 is used to clamp the gate voltage Vg_M1 of the MOS tube M1 to the sum of the first reference voltage Vref1 and the turn-on threshold voltage Vth of the MOS tube M2, so as to avoid damage to the gate of the MOS tube M1.

[0073] The circuit has the same principle of absorbing voltage spikes as the first spike absorption circuit described above, and the MOS tube M1 is turned on and off through the action of the capacitor C1 and the resistor R1, so as to absorb the energy of the drain voltage spike of the secondary side field effect tube FET2 when the voltage spike is generated, and not to absorb the energy of the drain voltage VD_SR of the secondary side field effect tube FET2 when the voltage spike subsides.

[0074] Referring to Figure 6 , the first and second clamping spike absorption circuits of the embodiment are shown in the spike absorption waveform diagram. When the VD_SR generates a voltage spike, the Vg_M1 is high, the MOS tube M1 is turned on, and the voltage spike energy is absorbed to the ground or the chip reference ground.

[0075] Referring to Figure 7 , the pulse spike absorption circuit of the second embodiment of the utility model comprises a pulse time module for generating a periodic pulse signal, a buffer circuit for buffering the pulse signal, and a second switch absorption module for opening and closing the absorption of voltage spike energy according to the pulse signal.

[0076] The pulse time module has one end connected to the gate of the secondary side field effect transistor FET2 and the other end connected to the input of the buffer BUF1. The output of the buffer BUF1 is connected to the input of the buffer BUF2. The output of the buffer BUF2 is connected to the gate of the MOS transistor M4. The drain of the MOS transistor M4 is connected to the drain of the secondary side field effect transistor FET2 and the source is connected to the ground or the chip reference ground.

[0077] In particular, referring to Figure 11 In this embodiment, the pulse time module includes the buffer BUF3, the resistor R4, the NOT gate NOT1, the NOR gate NOR1 and the capacitor C2.

[0078] The input of the buffer BUF3 is connected to the gate of the secondary side field effect transistor FET2 and one input of the NOR gate NOR1, and the output is connected to the resistor R4. One end of the resistor R4 is connected to the buffer BUF3, and the other end is connected to the capacitor C2 and the input of the NOT gate NOT1. The input of the NOT gate NOT1 is connected to the resistor R4 and the capacitor C2, and the output is connected to the other input of the NOR gate NOR1. One input of the NOR gate NOR1 is connected to the input of the buffer BUF3 and the gate of the secondary side field effect transistor FET2, and the other input is connected to the output of the NOT gate NOT1, and the output is connected to the input of the buffer BUF1.

[0079] In this circuit, the time when the pulse signal Pluse is high is controlled by the resistor R4 and the capacitor C2. By reasonably designing the values of the resistor R4 and the capacitor C2, the time when Pluse is high can be reasonably controlled, so that the voltage spike energy can be completely absorbed within the time when the voltage spike is formed. In addition, in this circuit, the input signal of the pulse time module can be the gate voltage VG_SR of the secondary side field effect transistor FET2, or other logic signals in the synchronous rectification controller chip that determine the turn-off of the secondary side field effect transistor FET2.

[0080] When the secondary side field effect transistor FET2 is turned off and the gate voltage VG_SR is low, the circuit generates a periodic pulse signal Pluse through the pulse time module. When the Pluse signal is high, the MOS transistor M4 is turned on, and the peak energy of the drain voltage VD_SR of the secondary side field effect transistor FET2 is absorbed to the ground or the chip reference ground. When the Pluse signal is low, the MOS transistor M4 is turned off and does not absorb the drain voltage energy of the secondary side field effect transistor FET2.

[0081] In particular, referring to Figure 8, the pulse time module generates a high level pulse signal to turn on the MOS tube M4 when the drain voltage VD_SR of the secondary side field effect tube FET2 generates a voltage spike, and the voltage spike energy is absorbed to the ground or the chip reference ground. Then the pulse signal Pluse turns to low level, making the MOS tube M4 cut off, and no longer absorbing the drain voltage energy of the secondary side field effect tube FET2.

[0082] Reference Figure 9 , the pulse time module generates a high level pulse signal to turn on the MOS tube M4 when the drain voltage VD_SR of the secondary side field effect tube FET2 generates a voltage spike, and the voltage spike energy is absorbed to the ground or the chip reference ground. Then the pulse signal Pluse turns to low level, making the MOS tube M4 cut off, and no longer absorbing the drain voltage energy of the secondary side field effect tube FET2.

[0083] Reference Figure 10 , the pulse time module generates a high level pulse signal to turn on the MOS tube M4 when the drain voltage VD_SR of the secondary side field effect tube FET2 generates a voltage spike, and the voltage spike energy is absorbed to the ground or the chip reference ground. Then the pulse signal Pluse turns to low level, making the MOS tube M4 cut off, and no longer absorbing the drain voltage energy of the secondary side field effect tube FET2.

[0084] The LDO circuit includes an LDO gate voltage module connected to the output end of the OR gate OR1, a MOS tube M3, a diode D2, a resistor R2, a resistor R3 and a comparator CMP1.

[0085] The gate of the MOS tube M3 is connected to the output end of the LDO gate voltage module, the drain is connected to the drain of the secondary side field effect tube, and the source is connected to the anode of the diode D2.

[0086] The negative electrode of the diode D2 is connected to one end of the resistor R2. The output voltage VCC is output between the negative electrode of the diode D2 and the resistor R2.

[0087] One end of the resistor R2 is connected to the negative electrode of the diode D2, the other end is connected to the resistor R3, and the inverting input end of the comparator CMP1.

[0088] One end of the resistor R3 is connected to the resistor R2 and the inverting input end of the comparator CMP1, and the other end is grounded.

[0089] The non-inverting input end of the comparator CMP1 is connected to the second reference voltage Vref2, the inverting input end is connected to the resistor R2 and the resistor R3, and the output end is connected to the other input end of the OR gate OR1; the second reference voltage Vref2 is used as a reference comparison voltage for turning on the LDO gate voltage module.

[0090] See again Figure 11 In this embodiment, the pulse timing unit includes a buffer BUF3, a resistor R4, a NOT gate NOT1, a NOR gate NOR1, and a capacitor C2.

[0091] The input of buffer BUF3 is connected to the gate of secondary-side field-effect transistor FET2 and one input of NOR gate NOR1, and the output is connected to resistor R4.

[0092] One end of resistor R4 is connected to buffer BUF3, and the other end is connected to capacitor C2 and NOT gate NOT1.

[0093] The NOT gate's input is connected to resistor R4 and capacitor C2, and its output is connected to the other input of the NOR gate.

[0094] One input of the NOR gate NOR1 is connected to the input of the buffer BUF3 and the gate of the secondary-side field-effect transistor FET2, the other input is connected to the output of the NOT gate NOT1, and the output is connected to one input of the OR gate OR1.

[0095] In this circuit, by properly designing the values ​​of resistor R4 and capacitor C2, the duration of the pulse's high level can be controlled, thus completely absorbing the voltage spike energy during its formation time. Furthermore, in this circuit, the input signal to the pulse timing module can be the gate voltage VG_SR of the secondary-side FET2, or other logic signals from the synchronous rectification controller chip that determine the turn-off of the secondary-side FET2.

[0096] Specifically, in this circuit, when the synchronous rectification control device operates in CCM mode and the secondary-side field-effect transistor FET2 is turned off, the gate voltage VG_SR of FET2 is low, and the drain voltage VD_SR generates a voltage spike. At this time, the pulse timing unit generates a high-level pulse signal, which is then passed through the OR gate OR1 to turn on the LDO gate voltage module. This allows the voltage spike energy to be transferred to the output voltage VCC through the LDO gate voltage module. The energy generated by the voltage spike from the drain voltage VD_SR of the secondary-side field-effect transistor FET2 can then be used in other modules through the voltage release of the output voltage VCC. Then, the pulse signal Puse transitions to a low level, and the LDO gate voltage module no longer absorbs the drain voltage energy from the secondary-side field-effect transistor FET2.

[0097] See again Figure 12This is a schematic diagram of the spike absorption waveform in this embodiment. When the drain voltage VD_SR of the secondary-side field-effect transistor FET2 generates a voltage spike, the pulse time unit generates a high-level pulse signal, turning on the LDO gate voltage module and absorbing the voltage spike energy into the output voltage VCC. The output voltage VCC then releases the voltage spike energy to other modules, gradually decreasing. Then, the pulse signal Puse turns low, turning off the LDO gate voltage module and preventing it from absorbing the drain voltage energy of the secondary-side field-effect transistor FET2.

[0098] In summary, this invention incorporates a spike absorption circuit within the synchronous rectification control device to absorb the drain voltage spikes generated by the secondary-side field-effect transistor to ground or the chip reference ground, or to convert them into other forms of energy, thereby reducing spike voltage and improving reliability and stability.

[0099] The embodiments described above are merely illustrative of several implementation methods of this application, and while the descriptions are specific and detailed, they should not be construed as limiting the scope of this patent application. It should be noted that those skilled in the art can make various modifications and improvements without departing from the concept of this application, and these all fall within the protection scope of this application. Therefore, the protection scope of this patent application should be determined by the appended claims.

Claims

1. A synchronous rectification control device, characterized in that, The system includes a synchronous rectification module and a drive circuit connected to the synchronous rectification module. The synchronous rectification module includes a spike absorption circuit, which is triggered after the secondary-side MOSFET of the flyback power supply charging system is turned off, and is used to absorb the voltage spike energy generated at the drain of the secondary-side MOSFET. The spike absorption circuit is a clamping spike absorption circuit, a pulse spike absorption circuit, or a pulse LDO spike absorption circuit. The clamping spike absorption circuit includes a first switching absorption module for turning on and off the absorption of voltage spike energy, and a clamping circuit for clamping the highest voltage of the first switching absorption module and controlling the turning on and off of the first switching absorption module. The pulse spike absorption circuit includes a pulse timing module for generating periodic pulse signals, a buffer circuit for buffering the pulse signals, and a second switching absorption module for turning on and off the absorption of voltage spike energy according to the pulse signals, connected in series. The pulsed LDO spike absorption circuit includes a pulse timing circuit for generating periodic pulse signals and an LDO circuit connected to the pulse timing circuit for absorbing the voltage spike energy after receiving the pulse signal and converting it into a stable output voltage VCC; the output voltage VCC is in a slowly decreasing state.

2. The synchronous rectification control device as described in claim 1, characterized in that, The first switch absorption module includes a MOSFET M1, and the clamping circuit includes a capacitor C1, a resistor R1, and a clamping diode D1. The gate of the MOS transistor M1 is connected to one end of the capacitor C1, the resistor R1 and the negative terminal of the clamping diode D1, and the drain is connected to the drain of the secondary-side field-effect transistor and the other end of the capacitor C1. The source is grounded or chip reference ground and connected to the positive terminal of the resistor R1 and the clamping diode D1.

3. The synchronous rectification control device as described in claim 1, characterized in that, The buffer circuit of the pulse spike absorption circuit includes buffer BUF1 and buffer BUF2; the second switch absorption module includes MOSFET M4; One end of the pulse timing module is connected to the gate of the secondary-side field-effect transistor, and the other end is connected to the input of the buffer BUF1. The output of buffer BUF1 is connected to the input of buffer BUF2; The output terminal of the buffer BUF2 is connected to the gate of the MOS transistor M4; The drain of the MOS transistor M4 is connected to the drain of the secondary-side field-effect transistor, and the source is grounded or the chip reference ground.

4. The synchronous rectification control device as described in claim 2, characterized in that, The clamping diode D1 can be replaced by a MOSFET M2; The source of the MOS transistor M2 is connected to the gate of the MOS transistor M1 and one end of the resistor R1, and the drain is grounded or the chip reference ground and connected to the source of the MOS transistor M1 and the other end of the resistor R1. The gate is connected to the first reference voltage Vref1. The MOS transistor M2 is used to clamp the gate voltage Vg_M1 of the MOS transistor M1 to the sum of the first reference voltage Vref1 and the turn-on threshold voltage Vth of the MOS transistor M2.

5. The synchronous rectification control device as described in claim 3, characterized in that, The pulse timing module includes a buffer BUF3, a resistor R4, a NOT gate NOT1, an NOR gate NOR1, and a capacitor C2. The input terminal of the buffer BUF3 is connected to the gate of the secondary-side field-effect transistor and one input terminal of the NOR gate NOR1, and the output terminal is connected to the resistor R4. One end of the resistor R4 is connected to the buffer BUF3, and the other end is connected to the capacitor C2 and the input terminal of the NOT gate NOT1; The input terminal of the NOT gate is connected to the resistor R4 and the capacitor C2, and the output terminal is connected to the other input terminal of the NOR gate NOR1. One input of the NOR gate NOR1 is connected to the input of the buffer BUF3 and the gate of the secondary-side field-effect transistor, and the other input is connected to the output of the NOT gate NOT1, the output of which is connected to the input of the buffer BUF1.

6. The synchronous rectification control device as described in claim 1, characterized in that, The pulse timing circuit includes a pulse timing unit connected to the gate of the secondary-side field-effect transistor, and an OR gate OR1 connected to the LDO circuit; the output terminal of the pulse timing unit is connected to one input terminal of the OR gate OR1; the output terminal and the other input terminal of the OR gate OR1 are connected to the LDO circuit. The LDO circuit includes an LDO gate voltage module connected to the output of the OR gate OR1, a MOSFET M3, a diode D2, a resistor R2, a resistor R3, and a comparator CMP1. The gate of the MOS transistor M3 is connected to the output terminal of the LDO gate voltage module, the drain is connected to the drain of the secondary-side field-effect transistor, and the source is connected to the positive terminal of the diode D2. The negative terminal of diode D2 is connected to one end of resistor R2; the output voltage VCC is output between the negative terminal of diode D2 and resistor R2. One end of the resistor R2 is connected to the negative terminal of the diode D2, and the other end is connected to the resistor R3 and the inverting input terminal of the comparator CMP1; One end of the resistor R3 is connected to the resistor R2 and the inverting input of the comparator CMP1, and the other end is grounded; The non-inverting input of the comparator CMP1 is connected to the second reference voltage Vref2, the inverting input is connected to the resistors R2 and R3, and the output is connected to the other input of the OR gate OR1; the second reference voltage Vref2 serves as the reference comparison voltage for turning on the LDO gate voltage module.

7. The synchronous rectification control device as described in claim 6, characterized in that, The pulse timing unit includes a buffer BUF3, a resistor R4, a NOT gate NOT1, an NOR gate NOR1, and a capacitor C2. The input terminal of the buffer BUF3 is connected to the gate of the secondary-side field-effect transistor FET2 and one input terminal of the NOR gate NOR1, and the output terminal is connected to the resistor R4. One end of the resistor R4 is connected to the buffer BUF3, and the other end is connected to the capacitor C2 and the NOT gate NOT1; The input terminal of the NOT gate is connected to the resistor R4 and the capacitor C2, and the output terminal is connected to the other input terminal of the NOR gate NOR1. One input of the NOR gate NOR1 is connected to the input of the buffer BUF3 and the gate of the secondary-side field-effect transistor FET2, the other input is connected to the output of the NOT gate NOT1, and the output is connected to one input of the OR gate OR1.

8. The synchronous rectification control device as described in claim 2, characterized in that, The capacitor C1 is the parasitic capacitance of the MOS transistor M1, or the sum of the parasitic capacitance and other equivalent capacitances.

9. The synchronous rectification control device as described in claim 1, characterized in that, The clamping spike absorption circuit and the pulse spike absorption circuit absorb the voltage spike generated at the drain of the secondary-side field-effect transistor to ground or chip reference ground; The pulsed LDO spike absorption circuit transfers the voltage spike generated at the drain of the secondary-side field-effect transistor to the output voltage VCC.

10. A flyback power charging system comprising the synchronous rectification control device according to any one of claims 1-9, characterized in that, The transformer includes a transformer that receives an input voltage Vin and generates an output voltage Vout, wherein the primary winding of the transformer is connected to the drain of a primary field-effect transistor, and the secondary winding of the transformer is connected to the drain of the secondary field-effect transistor. The gate of the primary-side field-effect transistor is connected to the primary-side controller, and the source is grounded; The gate of the secondary-side field-effect transistor is connected to the synchronous rectification control device, and the source is grounded and connected to the load module. One end of the load module is connected to the source of the secondary-side field-effect transistor, and the other end is connected to the secondary winding of the transformer and the output voltage Vout.

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