Buck synchronous rectification circuit and LED device

Abstract

This application relates to a Buck synchronous rectification circuit and an LED device. The circuit includes a synchronous rectification module, a comparator module, and a driver module. The synchronous rectification module includes an input capacitor, a first switching transistor, a second switching transistor, an inductor, an output capacitor, and a sampling resistor. The first input terminal of the comparator module is connected to both ends of the output capacitor, and the second input terminal is connected to both ends of the sampling resistor. The output terminal is connected to the input terminal of the driver module. When the voltage across the output capacitor is greater than a first output threshold and the voltage across the sampling resistor is less than a first feedback threshold, a first signal is output. When the first signal is output and the output voltage is greater than a second output threshold, a second signal is output. The output terminal of the driver module is connected to the first and second switching transistors. The driver module responds to the first signal to turn off the first and second switching transistors, and responds to the second signal to turn on either the first or second switching transistor. Open-circuit protection can be achieved at low cost using the Buck synchronous rectification circuit.

Description

Technical Field

[0001] This application relates to the field of electronic circuits, and in particular to a Buck synchronous rectifier circuit and an LED device. Background Technology

[0002] In recent years, more and more products have incorporated LED driver solutions, greatly facilitating people's daily lives. However, in practical applications, if an LED device malfunctions and becomes open-circuited, the output voltage of the Buck synchronous rectifier circuit will continuously increase. Therefore, open-circuit protection measures are needed to prevent excessive voltage from damaging other circuit components, such as the output capacitor. Furthermore, if the open-circuit fault is cleared and power-on restoration is required, directly connecting the LED device with an excessively high output voltage will instantly generate a very large inrush current, which could potentially damage the LED device, causing economic losses and threatening the safety of operators.

[0003] Traditional technologies often achieve open-circuit protection by adding external hardware circuits such as transistors and current transformers, but these circuits are complex and have high implementation costs. Buck synchronous rectifier circuits themselves have a simple structure; if the open-circuit protection circuit is complex, the component and size costs of the Buck synchronous rectifier circuit will be too high.

[0004] There is currently no effective solution to the problem of how to achieve open-circuit protection for Buck synchronous rectifier circuits at low cost in related technologies. Utility Model Content

[0005] Therefore, it is necessary to provide a Buck synchronous rectifier circuit that can achieve open-circuit protection at low cost.

[0006] Firstly, this embodiment provides a Buck synchronous rectification circuit, which includes: a synchronous rectification module, a comparator module, and a driver module;

[0007] The synchronous rectification module includes an input capacitor, an output capacitor, an inductor, a first switching transistor, a second switching transistor, and a sampling resistor. The input capacitor, the first switching transistor, the inductor, and the output capacitor are connected in series. One end of the second switching transistor is connected to the inductor and the first switching transistor, and the other end of the second switching transistor is connected to the output capacitor and the input capacitor. The sampling resistor is connected in series with the load, and the series-connected sampling resistor and the load are connected in parallel with the output capacitor.

[0008] The first input terminal of the comparison module is connected to both ends of the output capacitor, the second input terminal of the comparison module is connected to both ends of the sampling resistor, and the output terminal of the comparison module is connected to the input terminal of the driving module. The comparison module outputs a first signal when the output voltage across the output capacitor is greater than a first output threshold and the feedback voltage across the sampling resistor is less than a first feedback threshold, and stops outputting the first signal and outputs a second signal when the first signal is output and the output voltage is greater than a second output threshold, wherein the first output threshold is greater than the second output threshold.

[0009] The output terminal of the driving module is connected to the first switch and the second switch; the driving module is used to turn off the first switch and the second switch in response to the first signal, or the driving module is used to turn on the first switch or the second switch in response to the second signal.

[0010] In some embodiments, the output terminal of the driving module is connected to the gate of the first switching transistor and the gate of the second switching transistor, respectively;

[0011] The driving module is used to output a first driving signal to the gate of the first switching transistor and to output a second driving signal to the gate of the second switching transistor.

[0012] In some embodiments, the voltage of the second drive signal is within a first voltage range; wherein, when the gate voltage of the second switch is within the first voltage range, the second switch is in a fully on state; or...

[0013] The voltage of the second drive signal is within the second voltage range; wherein, when the gate voltage of the second switch is within the second voltage range, the second switch is in a linear conduction state.

[0014] In some embodiments, the level of the second drive signal varies based on a specified period.

[0015] In some embodiments, the comparison module includes: a first comparator, a second comparator, a third comparator, a first AND gate circuit, and a second AND gate circuit;

[0016] The input terminal of the first comparator is connected to both ends of the sampling resistor and a first voltage source for outputting the first feedback threshold, and the output terminal of the first comparator is connected to the input terminal of the first AND gate circuit.

[0017] The input terminal of the second comparator is connected to both ends of the output capacitor and a second voltage source for outputting the first output threshold, and the output terminal of the second comparator is connected to the input terminal of the first AND gate circuit.

[0018] The input terminal of the third comparator is connected to both ends of the output capacitor and a third voltage source for outputting the second output threshold. The output terminal of the third comparator is connected to the input terminal of the second AND gate circuit.

[0019] The output of the first AND gate is connected to the input of the driving module and the second AND gate;

[0020] The output of the second AND gate is connected to the driving module.

[0021] In some embodiments, the output of the first comparator is also connected to the input of the second AND gate circuit;

[0022] When the comparison module outputs the first signal, and the output voltage is greater than the second output threshold, and the feedback voltage across the sampling resistor is less than the first feedback threshold, the comparison module stops outputting the first signal and outputs the second signal.

[0023] In some embodiments, the comparison module stops outputting the second signal and outputs a third signal when the output voltage is less than or equal to the second output threshold.

[0024] The drive module responds to the third signal by alternately turning on the first switch and the second switch.

[0025] In some embodiments, the comparison module further includes a fourth comparator and a timer. The input of the fourth comparator is connected to both ends of the sampling resistor, a fourth voltage source for outputting a second feedback threshold, and the output of the timer. The output of the fourth comparator is connected to the driving module.

[0026] When the feedback voltage is greater than or equal to the second feedback threshold, the comparison module continuously outputs the fourth signal for a preset time length.

[0027] The driving module is used to turn on the first switch or the second switch in response to the second signal and the fourth signal.

[0028] Secondly, this embodiment provides an LED device, which includes an LED module and the Buck synchronous rectification circuit described in the first aspect above, wherein the LED module is connected to the Buck synchronous rectification circuit.

[0029] In the aforementioned Buck synchronous rectifier circuit and LED device, when the output voltage across the output capacitor is greater than the first output threshold and the feedback voltage is less than the first feedback threshold (i.e., an open-circuit fault), the comparator module outputs a first signal, causing the Buck synchronous rectifier circuit to enter an open-circuit protection state. A discharge circuit consisting of the output capacitor, inductor, first switch, and input capacitor is constructed by turning on the first switch in the synchronous rectifier module. Similarly, a discharge circuit consisting of the output capacitor, inductor, and second switch is constructed by turning on the second switch in the synchronous rectifier module. Thus, in the open-circuit protection state, by changing the operating states of the first and second switches in the Buck synchronous circuit, the internal connection structure of the Buck synchronous circuit is altered, and the voltage on the output capacitor under open-circuit fault conditions is discharged. This avoids the problem of excessive inrush current damaging components in the drive circuit during power recovery of the target load, while also achieving low cost. Attached Figure Description

[0030] To more clearly illustrate the technical solutions in the embodiments of this application or the conventional technology, the drawings used in the description of the embodiments or the conventional technology will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0031] Figure 1 This is a basic circuit block diagram of an open-circuit protection circuit in related technologies;

[0032] Figure 2 This is a schematic diagram of a discharge circuit in related technologies;

[0033] Figure 3 This is a circuit diagram based on relay load switching in related technologies;

[0034] Figure 4 This is a schematic diagram of a Buck synchronous rectification circuit in one embodiment of this application;

[0035] Figure 5 This is a schematic diagram of the comparison module and the driving module in one embodiment of this application;

[0036] Figure 6 This is the basic circuit topology of the Buck circuit in one embodiment of this application;

[0037] Figure 7(a) is a schematic diagram of the discharge circuit when the second switch is turned on in one embodiment of this application;

[0038] Figure 7(b) is a simulation diagram of the voltage release on the output capacitor when the second switch is fully turned on and the duty cycle is 0.2 in one embodiment of this application;

[0039] Figure 7(c) is a simulation diagram of the voltage release on the output capacitor when the second switch is fully turned on and the duty cycle is 0.5 in one embodiment of this application;

[0040] Figure 7(d) is a comparison of discharge currents under duty cycles of 0.2 and 0.5 in one embodiment of this application;

[0041] Figure 7(e) is a schematic diagram of the discharge logic when the second switch is fully turned on in one embodiment of this application;

[0042] Figure 8(a) is a schematic diagram of the discharge circuit when the first switching transistor is turned on in one embodiment of this application;

[0043] Figure 8(b) is a simulation diagram of the voltage release on the output capacitor when the first switch is turned on and the duty cycle is 0.2 in one embodiment of this application;

[0044] Figure 8(c) is a simulation diagram of the voltage release on the output capacitor when the first switch is turned on and the duty cycle is 0.3 in one embodiment of this application;

[0045] Figure 8(d) is a comparison of discharge currents under duty cycles of 0.2 and 0.3 in one embodiment of this application;

[0046] Figure 8(e) is a schematic diagram of the discharge logic when the first switching transistor is turned on in one embodiment of this application;

[0047] Figure 9(a) is a schematic diagram of the discharge circuit when the second switch is linearly turned on in one embodiment of this application;

[0048] Figure 9(b) is a simulation diagram of the voltage release on the output capacitor when the second switch is linearly turned on and the duty cycle is 0.1 in one embodiment of this application;

[0049] Figure 9(c) is a simulation diagram of the voltage release on the output capacitor when the second switch is linearly turned on and the duty cycle is 0.2 in one embodiment of this application;

[0050] Figure 9(d) is a simulation diagram of the voltage release on the output capacitor when the second switch is in a long linear conduction time and the duty cycle is 0.2 in one embodiment of this application;

[0051] Figure 9(e) is a comparison of discharge currents with different duty cycles and linear conduction times in one embodiment of this application;

[0052] Figure 9(f) is a schematic diagram of the discharge logic when the second switch is linearly turned on in one embodiment of this application;

[0053] Figure 10 This is a schematic diagram of the open-circuit recovery control logic in one embodiment of this application;

[0054] Figure 11This is a schematic diagram of an open-circuit recovery control logic in another embodiment of this application.

[0055] Explanation of reference numerals in the attached diagram: 1. Synchronous rectification module; 2. Comparison module; 21. First comparator; 22. Second comparator; 23. Third comparator; 24. Fourth comparator; 25. Fifth comparator; 26. First AND gate circuit; 27. Second AND gate circuit; 3. Driver module; 31. Driver unit; 32. Signal modulation unit; Cin, Input capacitor; Co, Output capacitor; L1, Inductor; M1, First switch transistor; M2, Second switch transistor; RCS, Sampling resistor; DC, Power supply; GATE1, Gate of the first switch transistor; GATE2, Gate of the second switch transistor; M1_GATE, First drive signal; M2_GATE, Second drive signal; Vo, Output voltage; Vm, First output threshold; V, Second output threshold; VFB, Feedback voltage; VFB1, First feedback threshold; VFB2, Second feedback threshold; VREF, Reference voltage; SS, Soft-start signal. Detailed Implementation

[0056] To facilitate understanding of this application, a more complete description will be provided below with reference to the accompanying drawings, which illustrate embodiments of the present application. However, the present application can be implemented in many different forms and is not limited to the embodiments described herein. Rather, these embodiments are provided so that the disclosure of this application will be thorough and complete.

[0057] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this application belongs. The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the application.

[0058] It is understood that the terms "first," "second," etc., used herein may be used to describe various elements, but these elements are not limited by these terms. These terms are only used to distinguish one element from another. For example, without departing from the scope of this application, a first resistor may be referred to as a second resistor, and similarly, a second resistor may be referred to as a first resistor. Both the first resistor and the second resistor are resistors, but they are not the same resistor.

[0059] It is understood that the term "connection" in the following embodiments should be understood as "electrical connection," "communication connection," etc., if the connected circuits, modules, units, etc., have electrical signal or data transmission with each other.

[0060] It is understandable that "at least one" refers to one or more, and "multiple" refers to two or more. "At least a part of an element" refers to part or all of an element.

[0061] When used herein, the singular forms of “a,” “an,” and “the” may also include the plural forms unless the context clearly indicates otherwise. It should also be understood that the terms “comprising / including” or “having,” etc., specify the presence of the stated features, wholes, steps, operations, components, parts, or combinations thereof, but do not preclude the possibility of the presence or addition of one or more other features, wholes, steps, operations, components, parts, or combinations thereof. Meanwhile, the term “and / or” as used in this specification includes any and all combinations of the associated listed items.

[0062] In related technologies, open-circuit protection typically determines whether an LED device is in an open-circuit fault state by detecting the output voltage Vo and the voltage VFB at the FB terminal. Figure 1 A basic circuit block diagram of an open-circuit protection circuit is provided, such as... Figure 1 The system includes a driver chip, an input capacitor Cin, an output capacitor Co, an inductor L1, a sampling resistor RCS, and a DC power supply. The voltage at the FB terminal of the driver chip is VFB, the output voltage is Vo, the input voltage is Vin, and the control terminal is SW. Based on... Figure 1 The circuit system shown determines that the LED device is in an open circuit fault state when it detects that VFB is less than a certain threshold and Vo is greater than the set threshold. It will take certain measures, such as turning off the switching transistor, to prevent the output voltage Vo from rising further, thereby achieving the purpose of open circuit protection.

[0063] Figure 2 A schematic diagram of a discharge circuit is provided, such as... Figure 2 As shown, the components include resistors R10 and R11, and transistors Q30, Q32, Q33, and Q34. To prevent excessively high output voltage Vo from damaging the devices and endangering operator safety during an open-circuit fault, a discharge circuit is established for the output voltage Vo to ensure that it remains within a safe threshold. Figure 2 The discharge circuit shown forms an output discharge loop by adding some components. During the open circuit protection period, it discharges the output voltage Vo. When the voltage Vo drops to the safe threshold, the discharge circuit is shut down, thereby solving the problem of excessively high output voltage Vo during open circuit faults.

[0064] Figure 3 A circuit diagram based on relay load switching is provided. Figure 3 As shown, the circuit includes relay J, transistors Q1 and Q2, and resistors R1, R2, and R3. The relay is used to control a delayed disconnection when the LED device is open-circuited. The connection structure is as follows: Figure 3 The load circuit, consisting of transistors Q1 and Q2 and resistors R1 and R2, releases the energy on the output capacitor Co, thereby achieving open-circuit protection and solving the problem of excessively high output voltage Vo during open-circuit faults.

[0065] The aforementioned related technologies suffer from high implementation costs and increased circuit size. Therefore, in one embodiment, a method is proposed as follows: Figure 4 The Buck synchronous rectifier circuit shown includes: synchronous rectifier module 1, comparator module 2, and driver module 3.

[0066] The synchronous rectification module 1 includes an input capacitor Cin, an output capacitor Co, an inductor L1, a first switch M1, a second switch M2, and a sampling resistor RCS. The input capacitor Cin, the first switch M1, the inductor L1, and the output capacitor Co are connected in series. One end of the second switch M2 is connected to the inductor L1 and the first switch M1, and the other end of the second switch M2 is connected to the output capacitor Co and the input capacitor Cin. The sampling resistor RCS is connected in series with the load, and the series-connected sampling resistor RCS and the load are connected in parallel with the output capacitor Co.

[0067] The synchronous rectification module 1 is the main circuit topology in the Buck synchronous rectification circuit. When the Buck synchronous rectification circuit drives the load, the input capacitor Cin in the synchronous rectification module 1 is connected in parallel with the external input power supply DC, and the output capacitor Co is connected in parallel with the driven load and the sampling resistor. When the Buck synchronous rectification circuit performs synchronous rectification under normal operating conditions, the first switch M1 and the second switch M2 are alternately turned on by the drive module 3 to achieve synchronous rectification. Optionally, under normal operating conditions, the drive module 3 outputs two complementary PWM signals to control the on and off of the first switch M1 and the second switch M2, respectively.

[0068] The first input terminal of the comparison module 2 is connected to both ends of the output capacitor Co, and the second input terminal of the comparison module 2 is connected to both ends of the sampling resistor RCS. The output terminal of the comparison module 2 is connected to the input terminal of the drive module 3. Specifically, the comparison module 2 can output a first signal when the output voltage Vo across the output capacitor Co is greater than a first output threshold Vm and the feedback voltage VFB across the sampling resistor is less than a first feedback threshold VFB1. It then stops outputting the first signal and outputs a second signal when the first output signal is output and the output voltage Vo is greater than a second output threshold V, where the first output threshold Vm is greater than the second output threshold V. Figure 4 FB is the feedback terminal, and the output voltage of FB is the feedback voltage VFB.

[0069] When the LED load connected to the Buck synchronous rectifier circuit experiences an open-circuit fault, the output voltage Vo on the output capacitor Co becomes excessively high. Under open-circuit fault conditions, the output voltage Vo of the Buck synchronous rectifier circuit exceeds the first output threshold Vm; the first output threshold Vm is slightly higher than the normal operating voltage of the load connected to the Buck synchronous rectifier circuit. The sampling resistor RCS is used to sample the load current to obtain the feedback voltage VFB. When the load connected to the Buck synchronous rectifier circuit fails, causing the Buck synchronous rectifier circuit to be in an open-circuit state, not only will the output voltage Vo increase and exceed the first output threshold Vm, but the feedback voltage VFB will also decrease and fall below the first feedback threshold VFB1. Therefore, when the output voltage Vo is greater than the first output threshold Vm and the feedback voltage VFB is less than the first feedback threshold VFB1, the Buck synchronous rectifier circuit is in an open-circuit state and requires open-circuit protection, which involves discharging the output voltage Vo on the output capacitor Co.

[0070] When the output voltage Vo discharges to the second output threshold V, it is determined that it is safe to restore the load to power, and the load can be reconnected to the Buck synchronous rectifier circuit. Therefore, the second output threshold V is less than the normal operating voltage of the load connected to the Buck synchronous rectifier circuit. When the load is in an open-circuit state and the output voltage Vo is greater than the second output threshold V, the Buck synchronous rectifier circuit needs to discharge. The Buck synchronous rectifier circuit is ready for open-circuit restoration until the output voltage Vo across the output capacitor Co is less than or equal to the second output threshold V. Upon detection of the subsequent load connection, it immediately resumes normal operation, and the load connected to the Buck synchronous rectifier circuit will not be damaged by overshoot current caused by excessively high output voltage Vo across the output capacitor Co.

[0071] The comparison module 2 can be composed of one or more existing comparators. Optionally, when implementing circuit comparison through a comparator chip, a first output threshold Vm and a second output threshold V can be obtained through a voltage divider resistor. The first output threshold Vm and the second output threshold V are then compared with the output voltage Vo. Based on the comparison result, a high or low level is output to achieve the output of a first signal or a second signal. Optionally, the comparison module 2 may also include a circuit structure containing timing control, such as a delay circuit. That is, when the duration of outputting the first signal reaches a certain duration, the output voltage Vo and the second output threshold V are compared, and when the output voltage Vo is greater than the second output threshold V, the output of the first signal is stopped and the second signal is output. It is understood that when the output voltage Vo across the output capacitor Co is less than or equal to the first output threshold Vm, the Buck synchronous rectification circuit has not failed, and the comparison module 2 does not output the first signal.

[0072] The output terminal of the drive module 3 is connected to the first switch M1 and the second switch M2; the drive module 3 is used to turn off the first switch M1 and the second switch M2 in response to the first signal, or the drive module 3 is used to turn on the first switch M1 or the second switch M2 in response to the second signal.

[0073] When the drive module 3 responds to the first signal and turns off the first switch M1 and the second switch M2, the downstream load is in an open-circuit fault state, and the Buck synchronous rectifier circuit enters an open-circuit protection state. Subsequently, if the drive module 3 responds to the second signal and turns on the first switch M1 or the second switch M2, the synchronous rectifier module 1 can construct a discharge circuit. Specifically, by turning on the first switch M1 in the Buck synchronous circuit, a discharge circuit consisting of the output capacitor Co, the inductor L1, the first switch M1, and the input capacitor Cin can be constructed. This discharge circuit uses the output to input reverse flow method to discharge the voltage on the output capacitor Co, preparing for open-circuit recovery and preventing the load from receiving excessive current and being damaged after open-circuit recovery. By turning on the second switch M2 in the Buck synchronous circuit, a discharge circuit consisting of the output capacitor Co, the inductor L1, and the second switch M2 can be constructed, so that energy is consumed in the DC impedance DCR of the inductor and the on-resistance Rds_on of the MOSFET, releasing the energy on the output capacitor Co.

[0074] The drive module 3 includes at least a signal output device. Optionally, the drive module 3 may include a PWM controller, which outputs a PWM signal to the first switch M1 and the second switch M2, thereby changing the on / off state of the first switch M1 and the second switch M2. Alternatively, the drive module 3 may also be a combination of a signal output device and a switching device, with the signal from the signal output device being input to the first switch M1 and the second switch M2 through the switching device. The switching device changes its on / off state in response to the first and second signals, thereby adjusting the signal output in the signal output device.

[0075] In this embodiment, considering that an open-circuit fault will occur when the output voltage Vo of the Buck synchronous rectifier circuit is greater than the first output threshold Vm and the FB voltage VFB is less than the first feedback threshold VFB1, and considering that the output voltage Vo of the output capacitor Co of the Buck synchronous rectifier circuit is less than or equal to the second output threshold V during the open-circuit protection state, the load will not be damaged by overcurrent after being connected to the Buck synchronous rectifier circuit, the comparison module 2 compares the output voltage Vo with the first output threshold Vm and the second output threshold V and outputs a signal. Then, the drive module 3 responds to the output signal of the comparison module 2 to change the conduction state of the first switch M1 or the second switch M2, thereby changing the circuit connection structure in the Buck synchronous circuit and constructing a discharge circuit to discharge the voltage of the output capacitor Co. The internal connection structure of the Buck synchronous rectifier circuit in this embodiment is dynamic, which can discharge the voltage of the output capacitor Co under the open-circuit fault state, achieving low cost and mitigating the problem of damage to the components in the drive circuit caused by excessive instantaneous current during target load open-circuit recovery.

[0076] In one embodiment, the output terminal of the driving module 3 is connected to the gate GATE1 of the first switching transistor and the gate GATE2 of the second switching transistor M2, respectively. The driving module 3 is used to output a first driving signal to the gate GATE1 of the first switching transistor and a second driving signal to the gate GATE2 of the second switching transistor M2. Optionally, the driving module 3 responds to the first signal by outputting a first driving signal to the gate GATE1 of the first switching transistor and the gate GATE2 of the second switching transistor M2 to turn off the first switching transistor M1 and the second switching transistor M2; the driving module 3 responds to the second signal by outputting a first driving signal to the gate GATE1 of the first switching transistor to turn on the first switching transistor M1; or, the driving module 3 responds to the second signal by outputting a second driving signal to the gate GATE2 of the second switching transistor M2 to turn on the second switching transistor M2.

[0077] The first switch M1 and the second switch M2 can be MOSFETs (Metal-Oxide-Semiconductor Field-Effect Transistors) or IGBTs (Insulated-Gate Bipolar Transistors). When the first switch M1 and the second switch M2 are different devices, the first drive signal input to the gate GATE1 of the first switch M1 and the second drive signal input to the gate GATE2 of the second switch M2 by the drive module 3 can be different.

[0078] Optionally, when the first switch M1 and the second switch M2 are MOSFETs, by applying a first drive signal and a second drive signal to the gate GATE1 of the first switch M1 and the gate GATE2 of the second switch M2, the voltage between GATE1 and the source, and the voltage between GATE2 and the source, respectively, drops below the threshold voltages corresponding to the first switch M1 and the second switch M2, cutting off the current path from the drain to the source and putting the first switch M1 and the second switch M2 in the off state. By applying a drive signal to the gate GATE2 of the first switch M1 and the second switch M2, a sufficiently high positive voltage is created between the voltage between GATE1 and the source, and between GATE2 and the source, allowing current to flow from the drain to the source, thus turning on the first switch M1 and the second switch M2.

[0079] Optionally, when the first switch M1 and the second switch M2 are IGBTs, by applying a first driving signal and a second driving signal to the gate GATE1 of the first switch and the gate GATE2 of the second switch M2 respectively, the voltage between GATE1 and the source, and the voltage between GATE2 and the source, are reduced and fall below the threshold voltages of the first switch M1 and the second switch M2, respectively, thus turning the first switch M1 and the second switch M2 off. By applying the first driving signal and the second driving signal to the gate GATE1 of the first switch and the gate GATE2 of the second switch M2, a positive voltage is applied, causing the voltage between the gate and the emitter of the first switch M1 and the second switch M2 to be higher than the corresponding threshold voltages, thereby turning on the first switch M1 and the second switch M2.

[0080] In this embodiment, the switching state is managed by precisely controlling the gate voltage by connecting the output terminal of the driving module 3 to the gate GATE1 of the first switching transistor and the gate GATE2 of the second switching transistor M2. The method is simple to implement and low in cost.

[0081] In one embodiment, the voltage of the second drive signal output by the drive module 3 to the gate GATE2 of the second switch M2 is within a first voltage range; wherein, when the voltage of the gate GATE2 of the second switch M2 is within the first voltage range, the second switch M2 is in a fully on state. The first voltage range is determined based on the model of the second switch M2, and the second drive signal can be preset according to the first voltage range.

[0082] In this embodiment, by outputting a second driving signal that enables the second switch M2 to be fully turned on, the energy on the output capacitor Co is discharged through the loop of "output capacitor Co-inductor L1-second switch M2-output capacitor Co", thereby reducing the voltage on the output capacitor Co.

[0083] In one embodiment, the voltage of the second drive signal output by the drive module 3 to the gate GATE2 of the second switch M2 is within a second voltage range; wherein, when the voltage of the gate GATE2 of the second switch M2 is within the second voltage range, the second switch M2 is in a linear conduction state. The second voltage range is determined based on the model of the second switch M2. By adjusting the gate GATE2 voltage of the second switch M2 to make it in a linear conduction state, the relatively large on-resistance of the second switch M2 is used to release the voltage on the output capacitor Co, limiting the magnitude of the discharge current, and preparing for open-circuit recovery. In this embodiment, when the second switch M2 is in a linear conduction state, the magnitude of the current through the circuit can be controlled, which helps to smoothly release the energy of the output capacitor Co and avoids the problem of excessive discharge current causing saturation and damage to the inductor L1 MOS.

[0084] In one embodiment, the level of the second drive signal changes based on a specified period. Optionally, the ratio of high to low levels within the specified period can be adjusted to change the signal duty cycle of the second drive signal. A larger duty cycle results in a larger discharge current and a faster drop in output voltage Vo; conversely, a smaller duty cycle results in a smaller discharge current. The signal duty cycle can be set as needed. In this embodiment, the periodically changing level can control the conduction time of the second switch M2, thereby limiting the discharge current in the discharge circuit and preventing inductor L1 saturation and MOS damage due to excessive discharge current.

[0085] In one embodiment, the comparison module 2 includes: a first comparator 21, a second comparator 22, a third comparator 23, a first AND gate circuit 26, and a second AND gate circuit 27; the input terminal of the first comparator 21 is connected to the two ends of the sampling resistor RCS and a first voltage source for outputting a first feedback threshold VFB1, and the output terminal of the first comparator 21 is connected to the input terminal of the first AND gate circuit 26; the input terminal of the second comparator 22 is connected to the two ends of the output capacitor Co and a second voltage source for outputting a first output threshold Vm, and the output terminal of the second comparator 22 is connected to the input terminal of the first AND gate circuit 26; the input terminal of the third comparator 23 is connected to the two ends of the output capacitor Co and a third voltage source for outputting a second output threshold V, and the output terminal of the third comparator 24 is connected to the input terminal of the second AND gate circuit 27; the output terminal of the first AND gate circuit 26 is connected to the driving module and the input terminal of the second AND gate circuit 27; and the output terminal of the second AND gate circuit 27 is connected to the driving module 3.

[0086] Among them, the first AND gate circuit 26 and the second AND gate circuit 27 are used to perform the logical "AND" operation; the first comparator 21, the second comparator 22 and the third comparator 23 are voltage comparators. The first comparator 21 is used to compare the feedback voltage VFB across the sampling resistor and the first feedback threshold VFB1; the second comparator 22 is used to compare the output voltage Vo across the output capacitor and the first output threshold Vm; the third comparator 23 is used to compare the output voltage Vo and the second threshold voltage Vm.

[0087] Optionally, if the comparison module 2 needs to perform the function of stopping the output of the first signal and outputting the second signal when the output voltage Vo is greater than the second output threshold V, based on the output of the first signal for a specified duration, then the comparison module 2 further includes a delay circuit. The output terminal of the first AND gate circuit 26 is connected to the input terminal of the delay circuit, and the output terminal of the delay circuit is connected to the input terminal of the second AND gate circuit 27.

[0088] Optionally, the first comparator 21 outputs a high-level signal when VFB across the sampling resistor is less than VFB1; otherwise, it outputs a low-level signal. The second comparator 22 outputs a high-level signal when Vo is greater than Vm; otherwise, it outputs a low-level signal. The third comparator 23 outputs a high-level signal when Vo is greater than V; otherwise, it outputs a low-level signal. The first AND gate outputs a first signal when all inputs are high-level signals. The second AND gate outputs a second signal when all inputs are high-level signals. It is understood that the first comparator 21 can also output a low-level signal when Vo is greater than Vm, and a NOT gate can be added to the output of the first comparator 21. Alternatively, the first AND gate 26 can be replaced with other existing logic gates according to application requirements, including but not limited to replacing or adding NOT gates, NAND gates, etc. The second comparator 22 can also output a low-level signal when VFB is less than VFB1, and adjust the internal connection structure and selected logic gates of the comparison module according to the output level signal. The first comparator 21 and the second comparator 22 can be selected from single-limit comparators, hysteresis comparators, window comparators, tri-state voltage comparators, etc., depending on the circuit implementation requirements. In this embodiment, the first comparator 21, the second comparator 22, the first AND gate circuit 26, and the second AND gate circuit 27 constitute a comparison module, which outputs a first signal or a second signal, achieving low cost.

[0089] In one embodiment, the output of the comparison module 2 is also connected to the input of the second AND gate circuit 27. When the comparison module 2 outputs a first signal, and the output voltage Vo is greater than the second output threshold V, and the feedback voltage VFB across the sampling resistor RCS is less than the first feedback threshold VFB1, the comparison module 2 stops outputting the first signal and outputs a second signal. Specifically, when the first AND gate circuit outputs the first signal, the first comparator determines that VFB is less than VFB1, and the second comparator determines that Vo is greater than V, the second AND gate circuit outputs the second signal.

[0090] In this embodiment, by combining the feedback voltage VFB with the output of the second signal, the accuracy of determining whether the load connected to the Buck synchronous rectifier circuit is in an open-circuit fault state can be improved.

[0091] In one embodiment, when the output voltage Vo is less than or equal to the second output threshold V, the comparison module 2 stops outputting the second signal and outputs the third signal; the drive module 3 responds to the third signal by alternately turning on the first switch M1 and the second switch M2.

[0092] Optionally, the drive module 3 outputs a signal with a small duty cycle to the gate GATE1 of the first switch M1 and the gate GATE2 of the second switch M2. Where the output voltage Vo is less than or equal to the second output threshold V, the output capacitor Co has already discharged.

[0093] In this embodiment, to avoid the load from recovering too slowly after being connected to the Buck synchronous rectifier circuit, the drive module 3 turns on the first switch M1 and the second switch M2, slightly increasing the output voltage Vo on the output capacitor Co, thereby improving the open circuit recovery speed.

[0094] It is understandable that the first switch M1 and the second switch M2 can be continuously and alternately turned on, so that the output voltage Vo rises and exceeds the second output threshold V. When the output voltage Vo exceeds the first output threshold Vm again, the comparison module 2 will output the first signal, and the drive module 3 will respond to the third signal to turn off the first switch M1 and the second switch M2 to avoid the output voltage Vo from being too large.

[0095] Furthermore, the judgment of the third signal output can be achieved by combining the feedback voltage VFB: when the feedback voltage VFB across the sampling resistor RCS is less than or equal to the first feedback threshold VFB1 and the output voltage Vo is less than or equal to the second output threshold V, the comparison module 2 stops outputting the second signal and outputs the third signal. Similarly, when the feedback voltage VFB is greater than or equal to the first feedback threshold VFB1, the open circuit is restored, and the load is reconnected to the Buck synchronous rectification circuit. When the output voltage Vo is greater than the first output threshold Vm again, the comparison module 2 outputs the first signal, turns off the first switch and the second switch M2, and enters the open circuit protection state.

[0096] Considering that if the Buck synchronous rectifier circuit is in an open-circuit fault state, and the voltage on the output capacitor Co has not yet started to discharge, or the discharge is not complete before the downstream load is energized, there will be a large overshoot current, leading to equipment damage and threatening the safety of operators. Related technologies do not consider the safety issue of power recovery in this situation. Therefore, in one embodiment, the comparison module 2 further includes a fourth comparator 24 and a timer. The input terminal of the fourth comparator 24 is connected to both ends of the sampling resistor, a fourth voltage source for outputting the second feedback threshold VFB2, and the output terminal of the timer. The output terminal of the fourth comparator 24 is connected to the drive module 3. When the feedback voltage VFB is greater than or equal to the second feedback threshold VFB2, the comparison module 2 continuously outputs a fourth signal for a preset time length; wherein the second feedback threshold VFB2 is greater than the first feedback threshold VFB1.

[0097] In one embodiment, the comparison module 2 may further include a fourth comparator 24, a timer, and a multiplier. The input terminal of the fourth comparator 24 is connected to both ends of the sampling resistor RCS and a fourth voltage source for outputting the second feedback threshold VFB2. The output terminal of the fourth comparator 24 and the output terminal of the timer are connected to the input terminal of the multiplier. The output terminal of the multiplier is connected to the driving module 3, so that the comparison module 2 continuously outputs a fourth signal of a preset time length when the feedback voltage VFB is greater than or equal to the second feedback threshold VFB2.

[0098] The timer is used to limit the output of the fourth signal to a preset time length, which can be modified as needed. After the load is connected to the circuit, by outputting the fourth signal for the preset time length, the Buck synchronous rectifier circuit can perform the discharge function again, causing the feedback voltage VFB to decrease and fall below the second feedback threshold VFB2, thus protecting the load's safety.

[0099] Specifically, when the feedback voltage VFB is greater than or equal to the first feedback threshold VFB1 and less than the second feedback threshold VFB2, the downstream load can be quickly connected to the synchronous rectification circuit and start working. Specifically, when the feedback voltage VFB is greater than or equal to the first feedback threshold VFB1 and less than the second feedback threshold VFB2, the comparator module 2 does not output the first, second, third, and fourth signals, and the synchronous rectification module 1 resumes normal operation.

[0100] Figure 5 A schematic diagram of a comparison module and a driver module is provided, such as... Figure 5As shown, the comparison module 2 includes not only the first comparator 21, second comparator 22, third comparator 23, first AND gate circuit 26, and second AND gate circuit 27, as well as the fourth comparator 24, timer, and multiplier described in the above embodiments, but also a delay circuit and a fifth comparator 25. The input terminal of the fourth comparator 24 is connected to both ends of the sampling resistor RCS and a fourth voltage source for outputting the second feedback threshold VFB2. The output terminals of the fourth comparator 24 and the timer are connected to the input terminal of the multiplier, and the output terminal of the multiplier is connected to the driver module 3. The output terminal of the first AND gate circuit 26 is connected to the input terminal of the delay circuit, and the output terminal of the delay circuit is connected to the input terminal of the second AND gate circuit 27. The input terminal of the fifth comparator 25 is connected to the output terminals of the feedback voltage VFB, the reference voltage VREF, and the soft-start signal SS. The output terminal of the fifth comparator 25 is connected to the driver module 3. The driver module 3 outputs a first drive signal M1_GATE and a second drive signal M2_GATE. The drive module 3 includes a drive unit 31 and a signal modulation unit 32. The input of the signal modulation unit 32 receives not only the signal output from the comparator module but also a CLOCK signal and a SLOPE COMP (Slope Compensation) signal. The signal modulation unit 32 can perform PWM modulation (Pulse Width Modulation) on the signal input to the drive module 3. Furthermore, the signal modulation unit 32 can also perform signal compensation processing based on existing signal compensation circuits. Optionally, the signal modulation unit 32 can use an existing PWM chip; the drive unit 31 can also use an existing drive chip. No restrictions are placed on the selection of devices for the signal modulation unit 32 and the drive unit 31. The fifth comparator 25 outputs a normal operating signal. The drive module 3 is used to alternately turn on the first switch M1 and the second switch M2 in response to the normal operating signal. The BUCK synchronous rectification circuit compares VFB with VREF and adjusts the duty cycle of the drive signal output by the drive module according to the difference between VFB and VREF. The value of the reference voltage VREF depends on the specific circuit design of the BUCK synchronous rectification circuit.

[0101] In this embodiment, when the normal working signal is restored, the first switch M1 and the second switch M2 are turned on alternately, and the Buck synchronous rectifier circuit continues to perform its synchronous rectification function.

[0102] In one embodiment, taking the first switch M1 and the second switch M2 as MOSFETs and the load as an LED device as an example, the open-circuit protection process of Buck synchronous rectification is explained in detail:

[0103] Figure 6 A basic circuit topology for Buck circuits is provided, such as Figure 6As shown. The positive terminal of the power supply DC is connected to the positive terminal of the input capacitor Cin, and the negative terminal of the power supply DC is connected to the negative terminal of the input capacitor Cin; the positive terminal of the input capacitor Cin is connected to the drain of the first switching transistor M1, and the negative terminal of the input capacitor Cin is connected to the source of the second switching transistor M2; the source of the first switching transistor M1 is connected to the drain of the second switching transistor M2; one end of the inductor L1 is connected to the source of the first switching transistor M1, and the other end is connected to the positive terminal of the output capacitor Co; the source of the second switching transistor M2 is connected to the negative terminal of the output capacitor Co; the positive terminal of the output capacitor Co is connected to the positive terminal of the LED device, and the negative terminal of the output capacitor Co is connected to one end of the sampling resistor RCS; the other end of the sampling resistor RCS is connected to the negative terminal of the LED device.

[0104] When comparator module 2 detects that the voltage Vo on the output capacitor Co is greater than the set first output threshold Vm and the voltage VFB at FB is less than the first feedback threshold VFB1, the LED device is in an open-circuit fault state, and the Buck synchronous rectifier circuit enters the open-circuit protection state. In the open-circuit protection state, there is no load in the downstream circuit, and the voltage on the output capacitor Co cannot be released. If the open-circuit fault state disappears at this time, and the LED device is energized, a large overcurrent will damage the LED device, causing economic losses and threatening the safety of operators.

[0105] To strictly limit the voltage on the output capacitor Co under open-circuit fault conditions without adding extra components, the first switch M1 or the second switch M2 can be turned on to form a discharge circuit.

[0106] Figure 7(a) provides a schematic diagram of the discharge circuit when the second switch M2 is turned on. As shown in Figure 7(a), in the open circuit protection state, the circuit is formed as "positive terminal of output capacitor Co → inductor L1 → switch M2 → negative terminal of output capacitor Co". The DC impedance DCR of the inductor and the on-resistance Rds_on of the switch discharge the voltage on the output capacitor Co, preparing for the open circuit recovery.

[0107] The low on-resistance Rds_on of the second switch M2 and the low DC resistance DCR of the inductor L1 prevent inductor L1 from saturating due to excessive discharge current, thus preventing damage to the MOSFET. The discharge current can be limited by controlling the on-time of the second switch M2, i.e., adjusting the duty cycle of the input MOSFET's gate signal, thereby protecting the devices from damage during discharge. When the voltage Vo on the output capacitor Co is less than the second output threshold V, the lower switch can be turned off to stop the discharge, ensuring a safe, reliable, and controllable discharge process.

[0108] Figure 7(b) is a simulation diagram of the voltage release on the output capacitor Co when the second switch M2 is fully turned on and the duty cycle is 0.2; Figure 7(c) is a simulation diagram of the voltage release on the output capacitor Co when the second switch M2 is fully turned on and the duty cycle is 0.5. Wherein, GATE_H is the voltage on the first switch M1, GATE_L is the voltage on the second switch M2, IL is the discharge current (i.e., the current flowing through inductor L1), and Vo is the output voltage Vo. Figure 7(d) is a comparison of the discharge current under duty cycles of 0.2 and 0.5; where t is time. The simulations in Figures 7(b) and 7(c) verify the feasibility of the discharge logic in Figure 7(a) and the controllability of the discharge current: turning on the second switch M2 releases the voltage on the output capacitor Co, and turning on the second switch M2 with a small duty cycle signal strictly limits the discharge current, protecting the device from damage.

[0109] Figure 7(e) provides a schematic diagram of the discharge logic when the second switch M2 is fully turned on. As shown in Figure 7(e), the scheme is the Buck synchronous rectification circuit in this embodiment. After the load enters the open circuit fault state, the upper and lower switches (the first switch M1 and the second switch M2) are turned off, thereby entering the open circuit protection state. The comparison module 2 determines whether the output voltage Vo is greater than the second output threshold V; if so, the lower switch (the second switch M2) is fully turned on, and the discharge current is limited by adjusting the duty cycle of the drive module 3; if not, the lower switch is turned off, and the discharge stops.

[0110] Figure 8(a) provides a schematic diagram of the discharge circuit when the first switch M1 is turned on. As shown in Figure 8(a), in the open-circuit protection state, the voltage on the output capacitor Co is discharged through the circuit of "positive terminal of output capacitor Co → inductor L1 → switch M1 → input capacitor Cin → negative terminal of output capacitor Co". This discharge operation is performed by reverse discharge from the output to the input, preparing for open-circuit recovery.

[0111] During the reverse discharge process from the output to the input, excessive discharge current can cause inductor L1 to saturate and damage the MOSFET. Furthermore, excessive current can lead to an excessively high instantaneous input voltage, causing overvoltage damage to components such as the input capacitor Cin, and also damaging other components sharing the same input voltage on the board, resulting in significant economic losses. Reducing the output voltage Vo also requires limiting the reverse current, which can be achieved by adjusting the duty cycle of the gate signal of the input MOSFET.

[0112] Figure 8(b) is a simulation diagram of voltage release on output capacitor Co when the first switch M1 is turned on and the duty cycle is 0.2; Figure 8(c) is a simulation diagram of voltage release on output capacitor Co when the first switch M1 is turned on and the duty cycle is 0.3. Figure 8(d) is a comparison diagram of discharge current under duty cycles of 0.2 and 0.3. The simulations in Figures 8(b) and 8(c) verify the feasibility of the discharge logic of the circuit corresponding to Figure 8(a) and the controllability of the discharge current: by turning on the first switch M1, the energy on output capacitor Co is reversed to the input terminal, and at the same time, the discharge current and the input terminal voltage amplitude are strictly controlled by controlling the signal duty cycle of the gate of the first switch M1, thus protecting the device from damage.

[0113] Figure 8(e) provides a schematic diagram of the discharge logic when the first switch M1 is turned on. As shown in Figure 8(e), after the load enters the open circuit fault state, the upper and lower switches (the first switch M1 and the second switch M2) are turned off, thereby entering the open circuit protection state. The comparison module 2 determines whether the output voltage Vo is greater than the second output threshold V; if so, the upper switch (the first switch M1) is turned on, and the discharge current is limited by adjusting the duty cycle of the drive module 3; if not, the upper switch is turned off, and the discharge stops.

[0114] Figure 9(a) provides a schematic diagram of a discharge circuit when the second switch M2 is linearly turned on. The difference between Figure 9(a) and Figure 7(a) is that in Figure 9(a), the second switch M2 is in a linearly turned-on state, and the larger on-resistance at this time can be used for discharge operation. The discharge current can be limited by controlling the linear on-time and its duty cycle to protect the device from damage; while in Figure 7(a), the second switch M2 is in a fully turned-on state. Specifically, in Figure 9(a), the discharge operation is performed through the circuit of "positive terminal of output capacitor Co → inductor L1 → switch M2 → negative terminal of output capacitor Co". The driving voltage of the second switch M2 is changed to make it in a linearly turned-on state, thereby using its larger on-resistance to release the voltage on the output capacitor Co, preparing for open-circuit recovery. The discharge circuit in Figure 9(a) can also limit the discharge current by controlling the duration of the MOS transistor drive voltage to control the length of time it is in the linear conduction state. At the same time, the discharge current can also be limited by controlling the duty cycle, so as to avoid the problem of inductor L1 saturation and MOS damage due to excessive discharge current.

[0115] Figure 9(b) is a simulation diagram of the voltage release on the output capacitor Co when the second switch M2 is linearly turned on and the duty cycle is 0.1. In this simulation, the driving voltage of the second switch M2 gradually increases, transitioning from a linearly turned-on state to a fully turned-on state while maintaining a duty cycle of 0.1. Figure 9(c) is a simulation diagram of the voltage release on the output capacitor Co when the second switch M2 is linearly turned on and the duty cycle is 0.2. In Figure 9(c), the driving voltage of the second switch M2 gradually increases, transitioning from a linearly turned-on state to a fully turned-on state, while its duty cycle changes from 0.1 to 0.2. Figure 9(d) is a simulation diagram of the voltage release on the output capacitor when the second switch M2 is in a long linearly turned-on state with a duty cycle of 0.2. Compared to Figure 9(c), the duty cycle in Figure 9(d) remains unchanged at 0.2, but the time the MOS is in linearly turned-on increases. Figure 9(e) is a comparison of discharge currents with different duty cycles and linear conduction times. Figure 9(e) compares the discharge currents with duty cycles of 0.1 and 0.2 and multiple linear conduction times.

[0116] Figure 9(f) provides a schematic diagram of the discharge logic when the second switch M2 is linearly turned on. As shown in Figure 9(f), after the load enters an open-circuit fault state, the upper and lower switches (the first switch M1 and the second switch M2) are turned off, thus entering the open-circuit protection state. Comparison module 2 determines whether the output voltage Vo is greater than the second output threshold V; if so, the lower switch (the second switch M2) enters the linearly turned-on state, and the discharge current is limited by adjusting the duty cycle of the drive module 3; if not, the lower switch is turned off, and the discharge stops.

[0117] In the discharge processes corresponding to the three discharge circuits shown in Figures 7(a), 8(a), and 9(a), when the comparison module detects that the voltage across the output capacitor Co is less than or equal to the second output threshold V, the discharge operation stops and waits for recovery. During the recovery process, to avoid a slow recovery speed, small duty cycle signals can be intermittently sent to the first switch M1 and the second switch M2. By alternately turning on the first switch M1 and the second switch M2, the LED device can quickly and reliably switch to normal operating status when connected, greatly improving the speed of the recovery process.

[0118] Understandably, when the LED device is in an open-circuit fault state, the output voltage Vo will gradually rise as the first switch M1 and the second switch M2 are alternately turned on based on the small duty cycle signal. When the output voltage Vo is detected to be greater than the second output threshold V, the discharge logic is restarted. When the output voltage Vo is less than or equal to the second output threshold V, the open-circuit recovery logic is restarted, and the step of outputting a small duty cycle signal is executed, and so on.

[0119] Furthermore, considering that when the LED device has a very short open-circuit time, the energy on the output capacitor may not have had time to be released, or may not have been released to the safety threshold, before the downstream load is connected to the Buck synchronous rectifier circuit and enters the open-circuit recovery state; at the moment of device connection, the feedback voltage VFB at the FB terminal is very high, posing a risk of overvoltage damage to the FB terminal. Moreover, directly connecting the LED device will result in a large LED overshoot current, causing damage to the LED device and threatening the safety of operators, resulting in unnecessary economic losses. To address this risk, protective measures can be implemented on the feedback voltage VFB at the FB terminal to ensure that the LED device can be stably, safely, and reliably connected to the circuit.

[0120] Figure 10 A schematic diagram of open-circuit recovery control logic is provided, such as... Figure 10 As shown, when the comparison module 2 detects that the feedback voltage VFB is greater than the first feedback threshold VFB1, the LED device can be connected. At this time, it will check again whether the feedback voltage VFB is less than the second feedback threshold VFB2. If the feedback voltage VFB is less than the second feedback threshold VFB2, the open circuit recovery logic is started to restore normal operation; if the feedback voltage VFB is greater than the second feedback threshold VFB2, the shutdown scheme is immediately turned off (the first switch M1 and the second switch M2 are turned off) and the discharge logic is entered, and a timer is started. After the timer expires, a restart is attempted. This process is repeated to achieve a safe, stable and reliable open circuit recovery process.

[0121] Figure 11 A logic control diagram of a Buck synchronous rectifier circuit is provided, such as... Figure 11As shown, after power-on, the output voltage Vo on the output capacitor Co and the feedback voltage VFB at the FB terminal are detected and compared with the set first output threshold Vm and the first feedback voltage VFB1. If the output voltage Vo is greater than Vm and VFB is less than VFB1, it is determined that the LED device is in an open-circuit fault state, and the first switch M1 and the second switch M2 are turned off, entering the open-circuit protection state. After entering the open-circuit protection state, the output voltage Vo is discharged through any of the discharge circuits shown in Figure 7(a), Figure 8(a), and Figure 9(a). During the discharge process, the comparison module 2 detects the output voltage Vo and the feedback voltage VFB throughout. If VFB is detected to be greater than or equal to the threshold VFB1, it is determined that the downstream device (LED device) has entered the discharge mode, and it is necessary to further determine whether VFB is less than the second feedback threshold VFB2. If VFB is greater than or equal to the second feedback threshold VFB2, it is forced to enter the discharge mode until VFB is less than VFB2 and then it recovers normally to avoid risks. If VFB is detected to be less than the threshold VFB1, the load is still in an open circuit state. At this point, it is further determined whether the output voltage Vo on the output capacitor Co is less than the second output threshold V. If the output voltage Vo is less than V, the discharge can be stopped, and the drive module 3 operates at small duty cycle intervals to prepare for open circuit recovery. While the drive module 3 operates at small duty cycle intervals, the voltage on the output capacitor Co will also rise. When the output voltage Vo is greater than the first output threshold Vm, the discharge logic is activated again, and this process is repeated to ensure the scheme can recover safely and reliably.

[0122] The Buck synchronous rectifier circuit in this embodiment can provide open circuit protection when the LED device is in an open circuit fault, and ensure the circuit recovers safely and quickly when the open circuit state disappears, thus realizing the functions of open circuit protection and open circuit recovery.

[0123] The circuit described above can also be applied to devices other than LED devices, such as computers, servers, routers, and battery systems.

[0124] Based on the same concept, this application also provides an LED device, which includes an LED module and a Buck synchronous rectification circuit, with the LED module connected to the Buck synchronous rectification circuit. The Buck synchronous rectification circuit includes: a synchronous rectification module 1, a comparator module 2, and a driver module; the synchronous rectification module 1 includes an input capacitor Cin, an output capacitor Co, an inductor L1, a first switch M1, a second switch M2, and a sampling resistor RCS; the input capacitor Cin, the first switch M1, the inductor L1, and the output capacitor Co are connected in series; one end of the second switch M2 is connected to the inductor L1 and the first switch M1, and the other end of the second switch M2 is connected to the output capacitor Co and the input capacitor Cin; the sampling resistor RCS is connected in series with the load, and the series-connected sampling resistor RCS and the load are connected in parallel with the output capacitor Co; the first input terminal of the comparator module 2 is connected to both ends of the output capacitor Co, and the second input terminal of the comparator module 2 is connected to... The output terminal of the comparison module 2 is connected to the input terminal of the drive module, and the output voltage Vo across the output capacitor Co is greater than the first output threshold Vm and the feedback voltage VFB across the sampling resistor RCS is less than the first feedback threshold VFB1. The comparison module 2 outputs a first signal when the output voltage Vo across the output capacitor Co is greater than the first output threshold Vm and the feedback voltage VFB across the sampling resistor RCS is less than the first feedback threshold VFB1. The first signal is output and the output voltage Vo is greater than the second output threshold V. The output terminal of the drive module is connected to the first switch M1 and the second switch M2. The drive module 3 is used to turn off the first switch M1 and the second switch M2 in response to the first signal, or the drive module 3 is used to turn on the first switch M1 or the second switch M2 in response to the second signal.

[0125] In one embodiment, the output terminal of the driving module 3 is connected to the gate GATE1 of the first switching transistor and the gate GATE2 of the second switching transistor M2, respectively. The driving module 3 is used to output a first driving signal to the gate GATE1 of the first switching transistor and a second driving signal to the gate GATE2 of the second switching transistor M2. Optionally, the voltage of the second driving signal output by the driving module 3 to the gate GATE2 of the second switching transistor M2 is in a first voltage range; wherein, when the voltage of the gate GATE2 of the second switching transistor M2 is in the first voltage range, the second switching transistor M2 is in a fully on state. Optionally, the voltage of the second driving signal output by the driving module 3 to the gate GATE2 of the second switching transistor M2 is in a second voltage range; wherein, when the voltage of the gate GATE2 of the second switching transistor M2 is in the second voltage range, the first switching transistor M1 is in a linearly on state. Optionally, the level of the second driving signal changes based on a specified period.

[0126] In one embodiment, the comparison module 2 includes: a first comparator 21, a second comparator 22, a third comparator 23, a first AND gate circuit 26, and a second AND gate circuit 27; the input terminal of the first comparator 21 is connected to the two ends of the sampling resistor RCS and a first voltage source for outputting a first feedback threshold VFB1, and the output terminal of the first comparator 21 is connected to the input terminal of the first AND gate circuit 26; the input terminal of the second comparator 22 is connected to the two ends of the output capacitor and a second voltage source for outputting a first output threshold Vm, and the output terminal of the second comparator 22 is connected to the input terminal of the first AND gate circuit 26; the input terminal of the third comparator 23 is connected to the two ends of the output capacitor and a third voltage source for outputting a second output threshold V, and the output terminal of the third comparator 23 is connected to the input terminal of the second AND gate circuit 27; the output terminal of the first AND gate circuit 26 is connected to the driving module 3 and the input terminal of the second AND gate circuit 27; the output terminal of the second AND gate circuit 27 is connected to the driving module 3. Optionally, the output of the first comparator 21 is also connected to the input of the second AND gate circuit 27. When the comparator module 2 outputs the first signal, and the output voltage Vo is greater than the second output threshold V, and the feedback voltage VFB across the sampling resistor RCS is less than the first feedback threshold VFB1, the comparator module 2 stops outputting the first signal and outputs the second signal. Optionally, when the output voltage Vo is less than or equal to the second output threshold V, the comparator module 2 stops outputting the second signal and outputs the third signal; the drive module 3 responds to the third signal by alternately turning on the first switch and the second switch M2.

[0127] In one embodiment, the comparison module 2 further includes a fourth comparator 24 and a timer. The input terminal of the fourth comparator 24 is connected to both ends of the sampling resistor RCS, a fourth voltage source for outputting the second feedback threshold VFB2, and the output terminal of the timer. The output terminal of the fourth comparator 24 is connected to the drive module 3. When the feedback voltage VFB is greater than or equal to the second feedback threshold VFB2, the comparison module 2 continuously outputs a fourth signal for a preset time length. The drive module 3 is used to turn on the first switch or the second switch M2 in response to the fourth signal. Optionally, the comparison module 2 may further include a fourth comparator 24, a timer, and a multiplier. The input terminal of the fourth comparator 24 is connected to both ends of the sampling resistor RCS and a fourth voltage source for outputting the second feedback threshold VFB2. The output terminals of the fourth comparator 24 and the timer are connected to the input terminal of the multiplier. The output terminal of the multiplier is connected to the drive module 3, so that the comparison module 2 continuously outputs a fourth signal for a preset time length when the feedback voltage VFB is greater than or equal to the second feedback threshold VFB2.

[0128] In the description of this specification, references to terms such as "some embodiments," "other embodiments," etc., indicate that a specific feature, structure, material, or characteristic described in connection with that embodiment or example is included in at least one embodiment or example of this application. In this specification, the illustrative descriptions of the above terms do not necessarily refer to the same embodiments or examples.

[0129] The technical features of the above embodiments can be combined in any way. For the sake of brevity, not all possible combinations of the technical features in the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0130] The embodiments described above are merely illustrative of several implementation methods of this application, and while the descriptions are specific and detailed, they should not be construed as limiting the scope of this application. It should be noted that those skilled in the art can make various modifications and improvements without departing from the concept of this application, and these modifications and improvements all fall within the protection scope of this application. Therefore, the protection scope of this application should be determined by the appended claims.

Claims

1. A Buck synchronous rectifier circuit, characterized in that, The Buck synchronous rectification circuit includes: a synchronous rectification module, a comparator module, and a driver module; The synchronous rectification module includes an input capacitor, an output capacitor, an inductor, a first switching transistor, a second switching transistor, and a sampling resistor. The input capacitor, the first switching transistor, the inductor, and the output capacitor are connected in series. One end of the second switching transistor is connected to the inductor and the first switching transistor, and the other end of the second switching transistor is connected to the output capacitor and the input capacitor. The sampling resistor is connected in series with the load, and the series-connected sampling resistor and the load are connected in parallel with the output capacitor. The first input terminal of the comparison module is connected to both ends of the output capacitor, the second input terminal of the comparison module is connected to both ends of the sampling resistor, and the output terminal of the comparison module is connected to the input terminal of the driving module. The comparison module outputs a first signal when the output voltage across the output capacitor is greater than a first output threshold and the feedback voltage across the sampling resistor is less than a first feedback threshold, and stops outputting the first signal and outputs a second signal when the first signal is output and the output voltage is greater than a second output threshold, wherein the first output threshold is greater than the second output threshold. The output terminal of the driving module is connected to the first switch and the second switch; the driving module is used to turn off the first switch and the second switch in response to the first signal, or the driving module is used to turn on the first switch or the second switch in response to the second signal.

2. The Buck synchronous rectifier circuit according to claim 1, characterized in that, The output terminal of the driving module is connected to the gate of the first switching transistor and the gate of the second switching transistor, respectively. The driving module is used to output a first driving signal to the gate of the first switching transistor and to output a second driving signal to the gate of the second switching transistor.

3. The Buck synchronous rectifier circuit according to claim 2, characterized in that, The voltage of the second drive signal is within the first voltage range; wherein, when the voltage of the gate of the second switch is within the first voltage range, the second switch is in a fully on state.

4. The Buck synchronous rectifier circuit according to claim 2, characterized in that, The voltage of the second drive signal is within the second voltage range; wherein, when the gate voltage of the second switch is within the second voltage range, the second switch is in a linear conduction state.

5. The Buck synchronous rectifier circuit according to claim 2, characterized in that, The level of the second drive signal changes based on a specified period.

6. The Buck synchronous rectifier circuit according to claim 1, characterized in that, The comparison module includes: a first comparator, a second comparator, a third comparator, a first AND gate circuit, and a second AND gate circuit; The input terminal of the first comparator is connected to both ends of the sampling resistor and a first voltage source for outputting the first feedback threshold, and the output terminal of the first comparator is connected to the input terminal of the first AND gate circuit. The input terminal of the second comparator is connected to both ends of the output capacitor and a second voltage source for outputting the first output threshold, and the output terminal of the second comparator is connected to the input terminal of the first AND gate circuit. The input terminal of the third comparator is connected to both ends of the output capacitor and a third voltage source for outputting the second output threshold. The output terminal of the third comparator is connected to the input terminal of the second AND gate circuit. The output of the first AND gate is connected to the input of the driving module and the second AND gate; The output of the second AND gate is connected to the driving module.

7. The Buck synchronous rectifier circuit according to claim 6, characterized in that, The output of the first comparator is also connected to the input of the second AND gate circuit; When the comparison module outputs the first signal, and the output voltage is greater than the second output threshold, and the feedback voltage across the sampling resistor is less than the first feedback threshold, the comparison module stops outputting the first signal and outputs the second signal.

8. The Buck synchronous rectifier circuit according to claim 1 or 6, characterized in that, When the output voltage is less than or equal to the second output threshold, the comparison module stops outputting the second signal and outputs the third signal. The drive module responds to the third signal by alternately turning on the first switch and the second switch.

9. The Buck synchronous rectifier circuit according to claim 6, characterized in that, The comparison module further includes a fourth comparator and a timer. The input terminal of the fourth comparator is connected to both ends of the sampling resistor, a fourth voltage source for outputting the second feedback threshold, and the output terminal of the timer. The output terminal of the fourth comparator is connected to the driving module. When the feedback voltage is greater than or equal to the second feedback threshold, the comparison module continuously outputs a fourth signal for a preset time length. The driving module is used to turn on the first switch or the second switch in response to the fourth signal.

10. An LED device, characterized in that, The device includes an LED module and a Buck synchronous rectifier circuit as described in any one of claims 1 to 9, wherein the LED module is connected to the Buck synchronous rectifier circuit.

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