A multi-bridge-arm fault-tolerant circuit for an inverter circuit

Abstract

The utility model relates to inverter circuit technical field, concretely relates to a kind of multi-bridge arm fault-tolerant circuit of inverter circuit, including power supply, first inverter bridge arm, spare bridge arm and first switch component;The first inverter bridge arm includes switch tube S1 and switch tube S2;The spare bridge arm includes switch tube S13 and switch tube S14;The positive pole of the power supply is connected with the negative pole of power supply after being sequentially passed through switch tube S1 and switch tube S2;The positive pole of the power supply is connected with the negative pole of power supply after being sequentially passed through switch tube S13 and switch tube S14;The junction of switch tube S1 and switch tube S2 is connected between switch tube S13 and switch tube S14 after being passed through first switch component.The utility model is provided with spare bridge arm and first switch component, when short circuit or open circuit condition appears, the switch tube S13 and switch tube S14 of system start spare bridge arm, first switch component is closed simultaneously, so that circuit can normally operate, so that fault-tolerant greatly improves.

Description

Technical Field

[0001] This utility model relates to the field of inverter circuit technology, and specifically to a multi-bridge-arm fault-tolerant circuit for inverter circuits. Background Technology

[0002] In the field of modern industrial automation, frequency converters occupy an indispensable position in motor drive systems due to their excellent speed regulation performance, and are widely used in many key industries such as industrial production, new energy power generation, and transportation.

[0003] In some existing designs, when a switch in one of the three-phase power supply phases of the inverter fails, the faulty bridge arm is disconnected, and the motor neutral point is connected to the DC power supply midpoint, reconfiguring the inverter into a two-phase, four-switch fault-tolerant topology. While this approach achieves fault handling to some extent, it still has significant drawbacks. Because the inverter circuit lacks one bridge arm, there is one less output phase, resulting in an inability to continuously and stably output three-phase power, thus affecting the normal operation of the motor.

[0004] Some solutions involve introducing a transformer into the inverter circuit. During normal operation, the transformer optimizes the three-phase output voltage waveform. In the event of a fault, the faulty bridge arm is disconnected, and the structure of the bridge arm allows for fault tolerance handling of single-arm, double-arm, and even triple-arm faults. The transformer then combines the two-phase voltages into a three-phase output, maintaining normal circuit operation under single-phase fault tolerance conditions. However, this solution also has drawbacks. The use of a transformer in the inverter circuit may cause a voltage boost, leading to increased voltage and potentially causing the motor current to exceed its limit, resulting in instability in motor operation and, in severe cases, even threatening the safe operation of the motor.

[0005] If the aforementioned basic protection functions fail, the transistors in the three-phase bridge arm will be damaged, and due to the lack of effective fault tolerance, the load motor will stop, causing the entire system to malfunction and become unable to work normally. Utility Model Content

[0006] The purpose of this invention is to address the aforementioned shortcomings in the prior art by providing a multi-bridge-arm fault-tolerant circuit for inverter circuits.

[0007] The purpose of this utility model is achieved through the following technical solution: a multi-arm fault-tolerant circuit for an inverter circuit, including a power supply, a first inverter arm, a spare arm, and a first switching assembly;

[0008] The first inverter bridge arm includes switch S1 and switch S2; the spare bridge arm includes switch S13 and switch S14; the positive terminal of the power supply is connected to the negative terminal of the power supply after passing through switch S1 and switch S2 in sequence; the positive terminal of the power supply is connected to the negative terminal of the power supply after passing through switch S13 and switch S14 in sequence; the connection between switch S1 and switch S2 is connected between switch S13 and switch S14 after passing through a first switching assembly.

[0009] The present invention is further configured such that both the switching transistor S13 and the switching transistor S14 are IGBT transistors; the collector of the switching transistor S13 is connected to the positive terminal of the power supply; the emitter of the switching transistor S14 is connected to the negative terminal of the power supply; and the emitter of the switching transistor S13 is connected to the collector of the switching transistor S14.

[0010] The present invention is further configured such that the first switching assembly includes a switching transistor S7 and a switching transistor S10; both switching transistors S7 and S10 are MOSFETs; both switching transistors S1 and S2 are IGBTs; the collector of switching transistor S1 is connected to the positive terminal of the power supply; the emitter of switching transistor S2 is connected to the negative terminal of the power supply; the emitter of switching transistor S1 is connected to the collector of switching transistor S2; the drain of switching transistor S7 is connected to the emitter of switching transistor S1; the source of switching transistor S7 is connected to the source of switching transistor S10; and the drain of switching transistor S10 is connected to the emitter of switching transistor S13.

[0011] The present invention is further configured such that a fuse F1 is provided between the collector of the switching transistor S1 and the positive terminal of the power supply;

[0012] A sampling resistor R1 is provided between the emitter of the switching transistor S2 and the negative terminal of the power supply; a first comparator is connected to both ends of the sampling resistor R1.

[0013] The present invention is further configured such that the multi-bridge fault-tolerant circuit includes a second inverter bridge arm and a second switching assembly; the second inverter bridge arm includes a switch S3 and a switch S4; the positive terminal of the power supply is connected to the negative terminal of the power supply after passing through the switch S3 and the switch S4 in sequence; the connection between the switch S3 and the switch S4 is connected between the switch S13 and the switch S14 after passing through the second switching assembly.

[0014] The present invention is further configured such that the second switching assembly includes a switching transistor S8 and a switching transistor S11; both switching transistors S8 and S11 are MOSFETs; both switching transistors S3 and S4 are IGBTs; the collector of switching transistor S3 is connected to the positive terminal of the power supply; the emitter of switching transistor S4 is connected to the negative terminal of the power supply; the emitter of switching transistor S3 is connected to the collector of switching transistor S4; the drain of switching transistor S8 is connected to the emitter of switching transistor S3; the source of switching transistor S8 is connected to the source of switching transistor S11; and the drain of switching transistor S11 is connected to the emitter of switching transistor S13.

[0015] The present invention is further configured such that a fuse F2 is provided between the collector of the switching transistor S3 and the positive terminal of the power supply;

[0016] A sampling resistor R2 is provided between the emitter of the switching transistor S4 and the negative terminal of the power supply; a second comparator is connected to both ends of the sampling resistor R2.

[0017] The present invention is further configured such that the multi-bridge fault-tolerant circuit includes a third inverter bridge arm and a third switching assembly; the third inverter bridge arm includes a switch S5 and a switch S6; the positive terminal of the power supply is connected to the negative terminal of the power supply after passing through the switch S5 and the switch S6 in sequence; the connection between the switch S5 and the switch S6 is connected between the switch S13 and the switch S14 after passing through the third switching assembly.

[0018] The present invention is further configured such that the third switching assembly includes a switching transistor S9 and a switching transistor S12; both switching transistors S9 and S12 are MOSFETs; both switching transistors S5 and S6 are IGBTs; the collector of switching transistor S5 is connected to the positive terminal of the power supply; the emitter of switching transistor S6 is connected to the negative terminal of the power supply; the emitter of switching transistor S5 is connected to the collector of switching transistor S6; the drain of switching transistor S9 is connected to the emitter of switching transistor S5; the source of switching transistor S9 is connected to the source of switching transistor S12; and the drain of switching transistor S12 is connected to the emitter of switching transistor S13.

[0019] The present invention is further configured such that a fuse F3 is provided between the collector of the switching transistor S5 and the positive terminal of the power supply;

[0020] A sampling resistor R3 is provided between the emitter of the switching transistor S6 and the negative terminal of the power supply; a third comparator is connected to both ends of the sampling resistor R3.

[0021] The beneficial effects of this utility model are as follows: By setting up a spare bridge arm and a first switching assembly, when a short circuit or open circuit occurs, the system activates the switching transistors S13 and S14 of the spare bridge arm and closes the first switching assembly at the same time, so that the circuit can operate normally, greatly improving fault tolerance. It can be used on equipment with extremely high requirements for stable operation. Attached Figure Description

[0022] The utility model will be further described with reference to the accompanying drawings, but the embodiments in the drawings do not constitute any limitation on the present utility model. For those skilled in the art, other drawings can be obtained based on the following drawings without creative effort.

[0023] Figure 1 This is the circuit schematic diagram of this utility model;

[0024] The components are: 1. First comparator; 2. Second comparator; 3. Third comparator; 4. Power supply. Detailed Implementation

[0025] The present invention will be further described in conjunction with the following embodiments.

[0026] Depend on Figure 1 As can be seen, the multi-arm fault-tolerant circuit of the inverter circuit described in this embodiment includes a power supply 4, a first inverter arm, a spare arm, and a first switching assembly.

[0027] The first inverter bridge arm includes switch S1 and switch S2; the spare bridge arm includes switch S13 and switch S14; the positive terminal of the power supply 4 is connected to the negative terminal of the power supply 4 after passing through switch S1 and switch S2 in sequence; the positive terminal of the power supply 4 is connected to the negative terminal of the power supply 4 after passing through switch S13 and switch S14 in sequence; the connection between switch S1 and switch S2 is connected between switch S13 and switch S14 after passing through a first switching assembly.

[0028] Specifically, the multi-bridge arm fault-tolerant circuit of the inverter circuit described in this embodiment, by setting a spare bridge arm and a first switching component, when a short circuit or open circuit occurs, the system starts the switching transistors S13 and S14 of the spare bridge arm and closes the first switching component at the same time, so that the circuit can operate normally, greatly improving fault tolerance, and can be used in equipment with extremely high requirements for stable operation.

[0029] This embodiment describes a multi-arm fault-tolerant inverter circuit, in which both switching transistors S13 and S14 are IGBTs. The collector of switching transistor S13 is connected to the positive terminal of power supply 4; the emitter of switching transistor S14 is connected to the negative terminal of power supply 4; and the emitter of switching transistor S13 is connected to the collector of switching transistor S14. This embodiment uses IGBTs as spare arms, which has the advantages of high efficiency, fast switching, easy driving, wide safe operating area, and suitability for high-voltage and high-current applications.

[0030] This embodiment describes a multi-arm fault-tolerant circuit for an inverter circuit. The first switching assembly includes a switching transistor S7 and a switching transistor S10. Both switching transistors S7 and S10 are MOSFETs. Both switching transistors S1 and S2 are IGBTs. The collector of switching transistor S1 is connected to the positive terminal of power supply 4. The emitter of switching transistor S2 is connected to the negative terminal of power supply 4. The emitter of switching transistor S1 is connected to the collector of switching transistor S2. The drain of switching transistor S7 is connected to the emitter of switching transistor S1. The source of switching transistor S7 is connected to the source of switching transistor S10. The drain of switching transistor S10 is connected to the emitter of switching transistor S13.

[0031] Specifically, in this embodiment, by setting the switching transistors S7 and S10 in reverse series, they can act as switches for switching the backup bridge arm. The reverse series connection of the switching transistors S7 and S10 can prevent the parasitic diode from causing the MOSFET to turn on when it is turned off.

[0032] In this embodiment, a multi-bridge fault-tolerant circuit for an inverter circuit is provided, wherein a fuse F1 is provided between the collector of the switching transistor S1 and the positive terminal of the power supply 4; the circuit can be protected by the above-mentioned arrangement.

[0033] A sampling resistor R1 is provided between the emitter of the switching transistor S2 and the negative terminal of the power supply 4; a first comparator 1 is connected to both ends of the sampling resistor R1. This configuration allows for real-time detection of the current in the sampling resistor R1.

[0034] This embodiment describes a multi-arm fault-tolerant circuit for an inverter circuit. The multi-arm fault-tolerant circuit further includes a second inverter arm and a second switching assembly. The second inverter arm includes switching transistors S3 and S4. The positive terminal of the power supply 4 is connected to the negative terminal of the power supply 4 after passing through switching transistors S3 and S4 in sequence. The connection between switching transistors S3 and S4 is connected between switching transistors S13 and S14 via the second switching assembly. This embodiment also describes a multi-arm fault-tolerant circuit for an inverter circuit. The multi-arm fault-tolerant circuit further includes a third inverter arm and a third switching assembly. The third inverter arm includes switching transistors S5 and S6. The positive terminal of the power supply 4 is connected to the negative terminal of the power supply 4 after passing through switching transistors S5 and S6 in sequence. The connection between switching transistors S5 and S6 is connected between switching transistors S13 and S14 via the third switching assembly.

[0035] Specifically, this embodiment sets up a first inverter bridge arm, a second inverter bridge arm, a third inverter bridge arm, a first switch assembly, a second switch assembly, and a third switch assembly. The first inverter bridge arm, the second inverter bridge arm, and the third inverter bridge arm have the same structure, and the first switch assembly, the second switch assembly, and the third switch assembly have the same structure, so that three-phase AC power can be output at the emitter of switch S1, the emitter of switch S3, and the emitter of switch S5, respectively.

[0036] This embodiment describes a multi-bridge fault-tolerant circuit for an inverter circuit. The second switching assembly includes switching transistors S8 and S11; both switching transistors S8 and S11 are MOSFETs; both switching transistors S3 and S4 are IGBTs; the collector of switching transistor S3 is connected to the positive terminal of power supply 4; the emitter of switching transistor S4 is connected to the negative terminal of power supply 4; the emitter of switching transistor S3 is connected to the collector of switching transistor S4; the drain of switching transistor S8 is connected to the emitter of switching transistor S3; the source of switching transistor S8 is connected to the source of switching transistor S11; and the drain of switching transistor S11 is connected to the emitter of switching transistor S13.

[0037] Specifically, in this embodiment, by setting the switching transistors S8 and S11 in reverse series, they can act as switches for switching the backup bridge arm. The reverse series connection of the switching transistors S8 and S11 can prevent the parasitic diode from causing the MOSFET to turn on when it is turned off.

[0038] In this embodiment, a multi-bridge fault-tolerant circuit for an inverter circuit is provided, wherein a fuse F2 is provided between the collector of the switching transistor S3 and the positive terminal of the power supply 4; the circuit can be protected by the above arrangement.

[0039] A sampling resistor R2 is provided between the emitter of the switching transistor S4 and the negative terminal of the power supply 4; a second comparator 2 is connected across the two ends of the sampling resistor R2. This configuration allows for real-time detection of the current in the sampling resistor R2.

[0040] This embodiment describes a multi-bridge arm fault-tolerant circuit for an inverter circuit. The third switching assembly includes switching transistors S9 and S12; both switching transistors S9 and S12 are MOSFETs; both switching transistors S5 and S6 are IGBTs; the collector of switching transistor S5 is connected to the positive terminal of power supply 4; the emitter of switching transistor S6 is connected to the negative terminal of power supply 4; the emitter of switching transistor S5 is connected to the collector of switching transistor S6; the drain of switching transistor S9 is connected to the emitter of switching transistor S5; the source of switching transistor S9 is connected to the source of switching transistor S12; and the drain of switching transistor S12 is connected to the emitter of switching transistor S13.

[0041] Specifically, in this embodiment, by setting the switching transistors S9 and S12 in reverse series, they can act as switches for switching the backup bridge arm. The reverse series connection of the switching transistors S9 and S12 can prevent the parasitic diode from causing the MOSFET to turn on when it is turned off.

[0042] In this embodiment, a multi-bridge fault-tolerant circuit for an inverter circuit is provided, wherein a fuse F3 is provided between the collector of the switching transistor S5 and the positive terminal of the power supply 4; the circuit can be protected by the above arrangement.

[0043] A sampling resistor R3 is provided between the emitter of the switching transistor S6 and the negative terminal of the power supply 4; a third comparator 3 is connected across the two ends of the sampling resistor R3. This configuration allows for real-time detection of the current in the sampling resistor R3.

[0044] When a short circuit occurs, fuses F1, F2, or F3 blow. Comparators 1, 2, and 3 simultaneously detect the short-circuit current. The system switches to the point where switches S13 and S14 are closed, activating the backup bridge arm. This ensures that the inverter circuit can continue to operate normally when maintenance engineers arrive on-site to analyze the damage. In subsequent fault analysis, the short-circuit point of the bridge arm can be quickly located using the truth table for short circuits. The truth table for short circuits is as follows:

[0045] S1 S2 S3 S4 S5 S6 Is current detected? Is it short-circuited? 1 0 0 0 0 0 There is current in phase U. S2 short circuit 0 1 0 0 0 0 There is current in phase U. S1 short circuit 0 0 1 0 0 0 There is current in phase V. S4 short circuit 0 0 0 1 0 0 There is current in phase V. S3 short circuit 0 0 0 0 1 0 There is current in phase W. S6 short circuit 0 0 0 0 0 1 There is current in phase W. S5 short circuit

[0046] 1 indicates that the device is enabled, and 2 indicates that it is disabled.

[0047] When an open circuit occurs, comparators 1, 2, and 3 detect no current. The system switches to close switches S13 and S14, opening the spare bridge arm to ensure the inverter circuit can continue to operate normally. If current is detected, it indicates that the phase is not open; if no current is detected, it indicates that a phase is open. Afterwards, maintenance engineers conduct a complete open-circuit test and analysis, cross-referencing the results of the truth table during the open circuit to quickly locate the bridge arm open circuit point. The truth table for the open circuit is as follows:

[0048] S1 S2 S3 S4 S5 S6 Is current detected? Should the road be opened? 1 0 0 1 0 1 Phase X has no current No / X phase open circuit 0 1 1 0 0 1 Phase X has no current No / X phase open circuit 0 1 0 1 1 0 Phase X has no current No / X phase open circuit

[0049] 1 indicates that the device is enabled, and 2 indicates that it is disabled.

[0050] This embodiment adds a circuit consisting of a spare bridge arm and a switching assembly to ensure that the inverter circuit can continue to work until the maintenance engineer arrives on site even if the inverter bridge arm is open-circuited or short-circuited. Damage to local components does not affect the overall normal operation of the system; that is, if one or more IGBTs are damaged, a spare bridge arm will take over and work normally.

[0051] In addition, more spare bridge arms can be added, which greatly improves fault tolerance and can be used on equipment with extremely high requirements for stable operation.

[0052] Secondly, by using the truth tables for short circuits and open circuits, maintenance engineers can quickly locate the short circuit point and open circuit point of the bridge arm during fault analysis, without the need for other sensors to detect the fault point of the circuit.

[0053] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of this utility model, and are not intended to limit the scope of protection of this utility model. Although this utility model has been described in detail with reference to preferred embodiments, those skilled in the art should understand that modifications or equivalent substitutions can be made to the technical solutions of this utility model without departing from the essence and scope of the technical solutions of this utility model.

Claims

1. A multi-arm fault-tolerant circuit for an inverter circuit, characterized in that: Includes power supply (4), first inverter bridge arm, spare bridge arm and first switch assembly; The first inverter bridge arm includes a switch S1 and a switch S2; the spare bridge arm includes a switch S13 and a switch S14; the positive terminal of the power supply (4) is connected to the negative terminal of the power supply (4) after passing through the switch S1 and the switch S2 in sequence; the positive terminal of the power supply (4) is connected to the negative terminal of the power supply (4) after passing through the switch S13 and the switch S14 in sequence; the connection between the switch S1 and the switch S2 is connected between the switch S13 and the switch S14 after passing through the first switching assembly; Both the switching transistor S13 and the switching transistor S14 are IGBT transistors; the collector of the switching transistor S13 is connected to the positive terminal of the power supply (4); the emitter of the switching transistor S14 is connected to the negative terminal of the power supply (4); the emitter of the switching transistor S13 is connected to the collector of the switching transistor S14. The multi-bridge fault-tolerant circuit also includes a second inverter bridge arm and a second switching assembly; the second inverter bridge arm includes a switch S3 and a switch S4; the positive terminal of the power supply (4) is connected to the negative terminal of the power supply (4) after passing through the switch S3 and the switch S4 in sequence; the connection between the switch S3 and the switch S4 is connected between the switch S13 and the switch S14 after passing through the second switching assembly.

2. The multi-arm fault-tolerant circuit for an inverter circuit according to claim 1, characterized in that: The first switching assembly includes a switching transistor S7 and a switching transistor S10; both switching transistors S7 and S10 are MOSFETs; both switching transistors S1 and S2 are IGBTs; the collector of switching transistor S1 is connected to the positive terminal of the power supply (4); the emitter of switching transistor S2 is connected to the negative terminal of the power supply (4); the emitter of switching transistor S1 is connected to the collector of switching transistor S2; the drain of switching transistor S7 is connected to the emitter of switching transistor S1; the source of switching transistor S7 is connected to the source of switching transistor S10; and the drain of switching transistor S10 is connected to the emitter of switching transistor S13.

3. The multi-bridge fault-tolerant circuit for an inverter circuit according to claim 2, characterized in that: A fuse F1 is provided between the collector of the switching transistor S1 and the positive terminal of the power supply (4); A sampling resistor R1 is provided between the emitter of the switching transistor S2 and the negative terminal of the power supply (4); a first comparator (1) is connected to both ends of the sampling resistor R1.

4. The multi-bridge-arm fault-tolerant circuit for an inverter circuit according to claim 1, characterized in that: The second switching assembly includes a switching transistor S8 and a switching transistor S11; both switching transistors S8 and S11 are MOSFETs; both switching transistors S3 and S4 are IGBTs; the collector of switching transistor S3 is connected to the positive terminal of the power supply (4); the emitter of switching transistor S4 is connected to the negative terminal of the power supply (4); the emitter of switching transistor S3 is connected to the collector of switching transistor S4; the drain of switching transistor S8 is connected to the emitter of switching transistor S3; the source of switching transistor S8 is connected to the source of switching transistor S11; and the drain of switching transistor S11 is connected to the emitter of switching transistor S13.

5. The multi-bridge-arm fault-tolerant circuit for an inverter circuit according to claim 4, characterized in that: A fuse F2 is provided between the collector of the switching transistor S3 and the positive terminal of the power supply (4); A sampling resistor R2 is provided between the emitter of the switching transistor S4 and the negative terminal of the power supply (4); a second comparator (2) is connected to both ends of the sampling resistor R2.

6. The multi-bridge fault-tolerant circuit for an inverter circuit according to claim 1, characterized in that: The multi-bridge fault-tolerant circuit also includes a third inverter bridge arm and a third switching assembly; the third inverter bridge arm includes a switch S5 and a switch S6; the positive terminal of the power supply (4) is connected to the negative terminal of the power supply (4) after passing through the switch S5 and the switch S6 in sequence; the connection between the switch S5 and the switch S6 is connected between the switch S13 and the switch S14 after passing through the third switching assembly.

7. The multi-bridge fault-tolerant circuit for an inverter circuit according to claim 6, characterized in that: The third switching assembly includes switching transistor S9 and switching transistor S12; both switching transistor S9 and switching transistor S12 are MOS transistors; both switching transistor S5 and switching transistor S6 are IGBT transistors; the collector of switching transistor S5 is connected to the positive terminal of the power supply (4); the emitter of switching transistor S6 is connected to the negative terminal of the power supply (4); the emitter of switching transistor S5 is connected to the collector of switching transistor S6; the drain of switching transistor S9 is connected to the emitter of switching transistor S5; the source of switching transistor S9 is connected to the source of switching transistor S12; and the drain of switching transistor S12 is connected to the emitter of switching transistor S13.

8. The multi-bridge fault-tolerant circuit for an inverter circuit according to claim 7, characterized in that: A fuse F3 is provided between the collector of the switching transistor S5 and the positive terminal of the power supply (4); A sampling resistor R3 is provided between the emitter of the switching transistor S6 and the negative terminal of the power supply (4); a third comparator (3) is connected to both ends of the sampling resistor R3.

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