Optical fiber longitudinal differential protection clock synchronization circuit

Abstract

The utility model discloses a kind of optical fiber longitudinal differential protection clock synchronization circuit, belong to electric power system relay protection technical field, including analog-digital conversion chip, crystal oscillator, optical fiber longitudinal differential protection microcontroller, GPS receiving module, crystal oscillator uses voltage-controlled constant temperature crystal oscillator;The 1PPS second pulse output end of GPS receiving module is connected to the timer clock capture end of optical fiber longitudinal differential protection microcontroller;Optical fiber longitudinal differential protection microcontroller is connected with analog-digital conversion chip, for controlling the output voltage of analog-digital conversion chip;The voltage output end of analog-digital conversion chip is connected with the control end of voltage-controlled constant temperature crystal oscillator.The utility model is through the timer capture second pulse of optical fiber longitudinal differential protection microcontroller, the counting error of second pulse and internal timer is compared constantly, the frequency of voltage-controlled constant temperature crystal oscillator is constantly calibrated, provides accurate clock reference for the two optical fiber longitudinal differential protection devices installed in different places, overcome the dynamic sampling error caused by crystal oscillator error.

Description

Technical Field

[0001] This utility model mainly relates to the field of power system relay protection technology, specifically to a fiber optic longitudinal differential protection clock synchronization circuit. Background Technology

[0002] Fiber optic differential protection is a differential protection technology based on fiber optic communication in power systems, primarily used for rapid fault isolation in high-voltage transmission lines. The structure of a fiber optic differential protection system is as follows: Figure 1 As shown, its core principle is to transmit the current vectors at both ends of the protected equipment in real time through a fiber optic channel, calculate the current difference using Kirchhoff's current theorem, quickly identify internal faults, and trip to clear the fault, ensuring system safety. Fiber optic differential protection devices are used in pairs, consisting of a reference measurement and a synchronization measurement. The two protection devices are installed at the beginning and end of the line, respectively, several kilometers to tens of kilometers apart. Ensuring the correct and reliable operation of the fiber optic differential protection depends on ensuring the synchronization of the sampling data from the two different fiber optic differential protection devices located several kilometers to tens of kilometers apart.

[0003] Two different fiber optic differential protection devices, located several kilometers to tens of kilometers apart, lack a unified clock reference and sample according to their own clock frequency and time. Due to different sampling start times and errors in the sampling clock reference frequency, the sampled data on both sides will be out of sync. The difference in sampling times can be synchronized after the two devices are powered on using the internal synchronization algorithm of the fiber optic differential protection system. The sampling clock reference error is caused by the crystal oscillator error selected by the fiber optic differential protection device. The accumulated error caused by the crystal oscillator errors of the two different protection devices must be continuously and dynamically adjusted during operation, making it difficult to achieve complete synchronization of the fiber optic differential protection clock. Summary of the Invention

[0004] This utility model provides a solution that is significantly different from existing technologies, addressing the problem that existing solutions are too simplistic. It mainly provides a fiber optic differential protection clock synchronization circuit, which provides a precise clock reference for two fiber optic differential protection devices located in two different places, thereby solving the problem of sampling clock reference error.

[0005] The technical solution adopted by this utility model to solve the above-mentioned technical problems is as follows:

[0006] A fiber optic longitudinal differential protection clock synchronization circuit includes an analog-to-digital converter chip, a crystal oscillator, a fiber optic longitudinal differential protection microcontroller, and a GPS receiver module. The crystal oscillator is a voltage-controlled temperature-controlled crystal oscillator. The 1PPS pulse output terminal of the GPS receiver module is connected to the timer clock capture terminal of the fiber optic longitudinal differential protection microcontroller. The fiber optic longitudinal differential protection microcontroller is connected to the analog-to-digital converter chip and is used to control the output voltage of the analog-to-digital converter chip. The voltage output terminal of the analog-to-digital converter chip is connected to the control terminal of the voltage-controlled temperature-controlled crystal oscillator.

[0007] Furthermore, the fiber longitudinal differential protection microcontroller is connected to the analog-to-digital converter chip via an SPI port.

[0008] Furthermore, the analog-to-digital converter chip used is the LTC1658.

[0009] Furthermore, the voltage-controlled temperature-controlled crystal oscillator is a 10MHz crystal oscillator of model NO0914LS3I107HE10A, powered by 5V, with a voltage control range of 0.5ppm.

[0010] Furthermore, the fiber optic longitudinal differential protection microcontroller is an AT32F435ZGT7.

[0011] Furthermore, the GPS receiver module is an ATGM332D-5N.

[0012] Furthermore, the output of the voltage-controlled thermostatic crystal oscillator is stabilized within ±3PPB, and the corresponding frequency output error is within ±0.03Hz.

[0013] Furthermore, the GPS receiving module outputs two time signals: a second pulse signal and a UTC time code, and the synchronization error between the rising edge of the second pulse signal and the UTC time code is less than or equal to 1 μs.

[0014] Compared with the prior art, the beneficial effects of this utility model are as follows:

[0015] (1) This utility model provides a high-precision fiber optic differential protection clock synchronization circuit based on a GPS receiving module and a voltage-controlled temperature-controlled crystal oscillator. The circuit captures GPS 1PPS pulses through the timer of the fiber optic differential protection microcontroller, continuously compares the 1PPS pulses with the counting error of the internal timer, and continuously calibrates the frequency of the voltage-controlled temperature-controlled crystal oscillator. This provides a precise clock reference for two fiber optic differential protection devices installed in different locations, achieving zero relative error between the two fiber optic differential protection crystal oscillators. This overcomes the dynamic sampling error caused by crystal oscillator error during the operation of previous fiber optic differential protection systems, greatly increasing the stability of the fiber optic differential protection.

[0016] (2) This utility model uses the ATGM332D-5N GPS receiver module (supporting six satellite systems) from Zhongke Microelectronics and the NO0914LS3I107HE10A voltage-controlled temperature-controlled crystal oscillator from Hengjing Technology. The hardware has strong compatibility and good anti-interference performance. The GPS receiver module can receive signals from 4 to 8 satellites at the same time. Even in the complex electromagnetic environment of the power system, it can still maintain a synchronization error of 1PPS ≤1μs. The voltage control range (0.5ppm) of the voltage-controlled temperature-controlled crystal oscillator is suitable for the long-term stability requirements of power protection.

[0017] (3) This utility model uses an LTC1658 analog-to-digital converter chip and an AT32F435ZGT7 microcontroller (288MHz main frequency) to achieve high-precision voltage regulation (14-bit resolution) through the SPI interface. It has fast calibration speed (real-time capture of 1PPS pulse) and low power consumption, which meets the dual requirements of power protection devices for real-time performance and low power consumption.

[0018] The present invention will be explained in detail below with reference to the accompanying drawings and specific embodiments. Attached Figure Description

[0019] Figure 1 This is a schematic diagram of the optical fiber longitudinal differential protection system in this utility model;

[0020] Figure 2 This is a diagram showing the interface connections between different modules in this utility model;

[0021] Figure 3 This is the circuit schematic diagram of this utility model. Detailed Implementation

[0022] To facilitate understanding of this utility model, a more comprehensive description of the utility model will be given below with reference to the accompanying drawings, which show several embodiments of the utility model. However, the utility model can be implemented in different forms and is not limited to the embodiments described in the text. On the contrary, these embodiments are provided to make the disclosure of the utility model more thorough and comprehensive.

[0023] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly associated with those skilled in the art to which this invention pertains. The terminology used herein is for the purpose of describing particular embodiments and is not intended to limit the invention. The term "and / or" as used herein includes any and all combinations of one or more of the associated listed items.

[0024] Example: A clock synchronization circuit for fiber optic differential protection includes: an analog-to-digital converter chip, a crystal oscillator, a fiber optic differential protection microcontroller, and a GPS receiver module; the crystal oscillator is a voltage-controlled temperature-controlled crystal oscillator, which serves as the active input crystal oscillator of the fiber optic differential protection microcontroller; the 1PPS pulse output terminal of the GPS receiver module is connected to the timer clock capture terminal of the fiber optic differential protection microcontroller; the fiber optic differential protection microcontroller controls the output voltage of the analog-to-digital converter chip through the SPI port; and the control terminal of the voltage-controlled temperature-controlled crystal oscillator is connected to the voltage output pin of the analog-to-digital converter chip.

[0025] When the GPS receiver module has a signal, the timer of the fiber optic differential protection microcontroller captures the GPS 1PPS pulse, obtaining the internal count N of the timer. The timer count of the fiber optic differential protection microcontroller is referenced to a voltage-controlled thermoelectric crystal oscillator (VCO). By calculating the error between N and the second pulse, the frequency error of the VCO can be obtained. After obtaining the error, the fiber optic differential protection microcontroller calculates the corresponding voltage-controlled voltage and adjusts the output voltage of the digital-to-analog converter chip via the SPI port, thereby adjusting the output frequency of the VCO and providing a high-precision synchronous clock for the fiber optic differential protection. After discipline calibration, the VCO can continue to provide a high-precision synchronous active crystal oscillator input for the fiber optic differential protection, regardless of whether a GPS signal is present or absent.

[0026] For the specific implementation of this fiber optic longitudinal differential protection clock synchronization circuit, see [link to details]. Figure 2 ,include:

[0027] U1 is an analog-to-digital converter chip, using the LTC1658. The LTC1658 is a 14-bit resolution digital-to-analog converter chip launched by Analog Devices (formerly Linear Technology).

[0028] U2 is a voltage-controlled temperature-controlled crystal oscillator, specifically a 10MHz crystal oscillator from Hengjing Technology, model NO0914LS3I107HE10A. This crystal oscillator uses a 5V power supply and has a voltage control range of 0.5ppm.

[0029] The U3 is a fiber optic differential protection microcontroller, employing the AT32F435ZGT7 from Artertronics. The Artertronics AT32F435 series of ultra-high-performance microcontrollers features a 32-bit ARM® Cortex®-M4 core, achieving an industry-leading 288MHz clock speed thanks to advanced process technology and integration. Its built-in single-precision floating-point unit (FPU), digital signal processor (DSP), and memory protection unit (MPU), along with rich peripherals and a flexible clock control mechanism, can meet the needs of various application fields.

[0030] U4 is a GPS receiver module, using the ATGM332D-5N from Zhongke Microelectronics. The ATGM332D-5N series is a general term for a series of high-performance BDS / GNSS full-constellation positioning and navigation modules with a 12×16 size. These modules are all based on Zhongke Microelectronics' fourth-generation low-power GNSS SOC single-chip—AT6558, supporting multiple satellite navigation systems, including China's BDS (BeiDou Navigation Satellite System), the US GPS, Russia's GLONASS, the EU's GALILEO, Japan's QZSS, and satellite augmentation systems SBAS (WAAS, EGNOS, GAGAN, MSAS). The AT6558 is a truly six-in-one multi-mode satellite navigation and positioning chip, containing 32 tracking channels, capable of simultaneously receiving GNSS signals from six satellite navigation systems, and achieving joint positioning, navigation, and timing.

[0031] The analog-to-digital converter chip U1 is connected to the fiber optic differential protection microcontroller U3 via SPI_SCK, SPI_SDA, and SPI_CS interfaces. The fiber optic differential protection microcontroller U3 is connected to the GPS receiver module U4 via CPS_TX, CPS_RX, and CPS_1PPS interfaces. The fiber optic communication interfaces (such as CPS_TX and RXD1) and hardware reset circuit (NRST) are explicitly integrated, which is compatible with the standard interface specifications of power protection devices. It can be directly embedded into existing differential protection devices without significant changes to the hardware architecture.

[0032] In application, the GPS receiver module can simultaneously receive information from 4 to 8 satellites within its field of view at any given time. By decoding, processing, and analyzing the received information, it can extract and output two time signals: one is a 1pps (1 pulse per second) signal, the synchronization error between the rising edge of this second pulse signal and the UTC time code not exceeding 1μs; the other is the UTC time (year, month, day, hour, minute, second) code corresponding to 1PPS output via the serial port. The fiber optic differential protection microcontroller obtains the UTC time through the serial port to synchronize the fiber optic differential protection, ensuring that the real-time time of the two protection devices remains consistent. The fiber optic differential protection microcontroller captures the 1PPS rising edge signal through a timer clock, serving two purposes: first, to achieve second-level updates of the real-time clock; and second, to calculate the error between the timer count and the second pulse, thereby calibrating the voltage-controlled temperature-controlled crystal oscillator.

[0033] By continuously comparing the 1PPS pulse with the counting error of the internal timer through the microcontroller of the fiber optic differential protection system, the voltage-controlled thermostatic crystal oscillator (VCO) is constantly calibrated. This stabilizes the VCO's output within ±3PPB, corresponding to an output error of ±0.03Hz. The maximum clock error between two fiber optic differential protection units is 0.006μs. Even after GPS signal loss, the VCO can maintain a high-precision clock output, providing a high-precision synchronization clock for the fiber optic differential protection system.

[0034] Both optical fiber longitudinal differential protection devices on both sides of the line use such clock synchronization circuits, and the sampling pulses given by the sampling clocks on both sides have a relative error of no more than 2μs.

[0035] In summary, this invention uses a voltage-controlled temperature-controlled crystal oscillator (VCSEL) as the active crystal input to the microcontroller for fiber optic differential protection, and calibrates the VCSEL using GPS 1PPS pulses. This provides a precise clock reference for two fiber optic differential protection devices installed in different locations, achieving zero relative error between the two crystal oscillators. This overcomes the dynamic sampling error caused by crystal oscillator errors during the operation of previous fiber optic differential protection systems, significantly increasing the stability of the fiber optic differential protection.

[0036] The present invention has been described above by way of example in conjunction with the accompanying drawings. Obviously, the specific implementation of the present invention is not limited to the above-described manner. Any non-substantial improvement made by adopting the inventive concept and technical solution of the present invention, or the direct application of the inventive concept and technical solution of the present invention to other occasions without modification, shall be within the protection scope of the present invention.

Claims

1. A fiber optic longitudinal differential protection clock synchronization circuit, characterized in that: The system includes an analog-to-digital converter (ADC), a crystal oscillator, a fiber optic differential protection microcontroller, and a GPS receiver module. The crystal oscillator is a voltage-controlled temperature-controlled crystal oscillator. The 1PPS pulse output terminal of the GPS receiver module is connected to the timer clock capture terminal of the fiber optic differential protection microcontroller. The fiber optic differential protection microcontroller is connected to the ADC and is used to control the output voltage of the ADC. The voltage output terminal of the ADC is connected to the control terminal of the voltage-controlled temperature-controlled crystal oscillator.

2. The fiber optic longitudinal differential protection clock synchronization circuit according to claim 1, characterized in that: The fiber optic longitudinal differential protection microcontroller is connected to the analog-to-digital converter chip via an SPI port.

3. The fiber optic longitudinal differential protection clock synchronization circuit according to claim 1, characterized in that: The analog-to-digital converter chip used is the LTC1658.

4. The fiber optic longitudinal differential protection clock synchronization circuit according to claim 1, characterized in that: The voltage-controlled temperature-controlled crystal oscillator is a 10MHz crystal oscillator of model NO0914LS3I107HE10A, powered by 5V, with a voltage control range of 0.5ppm.

5. The fiber optic longitudinal differential protection clock synchronization circuit according to claim 1, characterized in that: The fiber optic longitudinal differential protection microcontroller is an AT32F435ZGT7.

6. The fiber optic longitudinal differential protection clock synchronization circuit according to claim 1, characterized in that: The GPS receiver module used is ATGM332D-5N.

7. The fiber optic longitudinal differential protection clock synchronization circuit according to claim 1, characterized in that: The output of the voltage-controlled thermostatic crystal oscillator is stable within ±3PPB, and the corresponding frequency output error is within ±0.03Hz.

8. The fiber optic longitudinal differential protection clock synchronization circuit according to claim 1, characterized in that: The GPS receiver module outputs two time signals: a second pulse signal and a UTC time code, and the synchronization error between the rising edge of the second pulse signal and the UTC time code is less than or equal to 1 μs.

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