A short wave broadband modem module

Abstract

The utility model discloses a kind of short wave wideband modem module, including bottom plate and core board, the bottom plate integration has FPGA main control chip, audio codec, interface circuit, first crystal oscillator and first FLASH, the audio codec, first crystal oscillator and first FLASH are all with the FPGA main control chip electricity is connected, the interface circuit with the audio codec electricity is connected;The core board integration has DSP, second crystal oscillator, two SRAM and second FLASH, the second crystal oscillator, two SRAM and second FLASH are all with the DSP electricity is connected;The FPGA main control chip with the DSP electricity is connected;The utility model adopts overall architecture, through bottom plate plus core board, modular design, it is convenient to maintain, upgrade and reuse, separate high-speed digital signal and analog / radio frequency part, improve system stability;DSP and FPGA work cooperatively, give consideration to algorithm complexity and real-time performance, multiple crystal oscillator design, guarantee system synchronization and precision, FLASH is used for program and configuration save, guarantee system persistent operation.

Description

Technical Field

[0001] This utility model relates to the field of shortwave modulation and demodulation technology, and more specifically, to a shortwave broadband modem module. Background Technology

[0002] Shortwave communication, due to its unique long-distance characteristics, plays a crucial role in military communications, oil exploration, and ocean shipping. When shortwave communication was first developed, it was used to transmit keypad messages and voice, with a bandwidth of only 3kHz. Currently, shortwave data communication also utilizes a 3kHz bandwidth to transmit data services, with a maximum rate of 2.4kbps. A practical shortwave channel is a dispersive channel that varies in the time, frequency, and spatial domains. Time-domain broadening, frequency-domain dispersion, and fading are the main obstacles limiting reliable high-speed data transmission on shortwave channels. Given that 2.4kbps is difficult to achieve in practical shortwave channels, communication rates generally do not exceed 600bps. If efficient modulation methods are used to increase the rate on top of the 3kHz base, practical communication will become even more challenging.

[0003] SICOM, an American company, achieved a transmission rate of 57.6 kbps within a 1.5 MHz bandwidth using wideband direct sequence spread spectrum technology. However, practical shortwave channels exhibit a window effect, and various interferences are severe within a 1.5 MHz bandwidth, limiting the user capacity and communication performance of this technology. The US military's CHESS system, developed using high-speed differential frequency hopping technology, achieved 5000 hops / second and a transmission rate of 19.2 kbps within a 2.56 MHz bandwidth. The CHESS system utilizes the frequency position relationship between consecutive hops to carry information and employs wideband power amplifiers and wideband antennas. However, the frequency window for practical shortwave communication is relatively small. With existing shortwave channels becoming increasingly congested, current high-speed shortwave data transmission technologies cannot guarantee normal high-speed data communication under conditions of limited bandwidth and receiver signal-to-noise ratio.

[0004] Based on the above, a shortwave broadband modem module is proposed, which appropriately extends the original 3kHz bandwidth to 24kHz to improve the communication rate and ensure the communication effect. Utility Model Content

[0005] The purpose of this invention is to provide a shortwave broadband modem module that overcomes the aforementioned defects in the prior art.

[0006] The technical solution to achieve the purpose of this utility model is: a shortwave broadband modem module, the module adopting a 24kHz bandwidth single-carrier frequency domain equalization system; including a base plate and a core board, the base plate integrating an FPGA main control chip, an audio codec, an interface circuit, a first crystal oscillator and a first FLASH, the audio codec, the first crystal oscillator and the first FLASH are all electrically connected to the FPGA main control chip, and the interface circuit is electrically connected to the audio codec; the core board integrating a DSP, a second crystal oscillator, two SRAMs and a second FLASH, the second crystal oscillator, the two SRAMs and the second FLASH are all electrically connected to the DSP; the FPGA main control chip and the DSP are electrically connected.

[0007] Preferably or optionally, the FPGA main control chip is a GW2A-LV18LQ144C8 chip, the audio codec is a JAD73311 chip, and the FPGA main control chip and the audio codec are electrically connected through a McBSP interface.

[0008] Preferably or optionally, the first crystal oscillator uses a clock frequency of 18.432MHz, and the first FLASH uses an SM25QH64M chip.

[0009] Preferably or optionally, the interface circuit is connected to the differential signal lines HFT+ and HFT- at the transmitting end and the differential signal lines HFR+ and HFR- at the receiving end.

[0010] Preferably or optionally, the DSP uses an FT-C6416 chip, and the DSP is electrically connected to the FPGA main control chip through a McBSP interface.

[0011] Preferably or optionally, the second crystal oscillator uses a clock frequency of 50MHz.

[0012] Preferably or optionally, the two SRAMs are SM7C1061AV33 chips, the second FLASH is an SM29LV320 chip, and both SRAMs and the second FLASH are electrically connected to the DSP via an EMIF interface.

[0013] Preferably or optionally, the core board also integrates a UART, and the baseboard also integrates an RS232 interface; the UART and the RS232 interface are electrically connected, and the UART and the DSP are electrically connected through an EMIF interface.

[0014] Preferably or optionally, the UART uses an SM16C752 chip, and the RS232 interface uses an SM3232 chip.

[0015] Preferably or optionally, the base plate also integrates a power supply for powering the shortwave broadband modem module.

[0016] By adopting the above technical solution, this utility model has the following beneficial effects:

[0017] (1) The shortwave broadband modem module of this utility model adopts single-carrier frequency domain equalization technology. The single-carrier frequency domain equalization system is a new shortwave broadband physical layer waveform that is different from the traditional 3kHz single-tone serial system. It uses a 24kHz bandwidth and can achieve a higher symbol rate. At the transmitting end, the single-carrier frequency domain equalization system adds a cyclic prefix to the symbol block composed of multiple data for multipath protection. At the receiving end, frequency domain equalization technology is used to equalize the entire symbol block at once, avoiding the symbol-by-symbol equalization process of traditional time domain equalization technology and reducing the implementation complexity. Moreover, the spectrum of the single-carrier signal occupies the entire bandwidth, the signal has a low peak-to-average power ratio, and the radio power transmission efficiency is high, so as to improve the communication rate and ensure the communication effect.

[0018] (2) This utility model adopts an overall architecture, with a baseboard and a core board, and a modular design, which facilitates maintenance, upgrades and reuse. It separates the high-speed digital signal and the analog / RF part to improve system stability. The core board with different functions can be replaced to adapt to different application scenarios. The baseboard can connect more peripherals or expansion interfaces. The separation of the core board and the baseboard is conducive to functional isolation and problem localization. The DSP and FPGA work together to balance the complexity of the algorithm and real-time performance. The multi-crystal oscillator design ensures system synchronization and accuracy. FLASH is used to save programs and configurations to ensure the system runs continuously.

[0019] (3) The FPGA main control chip (GW2A-LV18LQ144C8) of this utility model has high-speed parallel processing capability, is suitable for real-time signal preprocessing, and its programmability supports flexible function adjustment and upgrade, reducing the DSP burden and improving the overall system efficiency; the audio codec (JAD73311) supports high-quality voice acquisition and playback, meets the voice transmission requirements in shortwave communication, supports multiple audio sampling rates, adapts to different communication scenarios, and connects to the FPGA through the McBSP interface to realize high-speed data exchange.

[0020] (4) The first crystal oscillator (18.432MHz) of this utility model provides the system master clock reference for the internal logic timing control of the FPGA. 18.432MHz is the standard audio clock frequency (supports 48kHz, 96kHz, etc.) to ensure audio quality. The high-precision crystal oscillator improves the system stability and synchronization performance.

[0021] (5) The first FLASH (SM25QH64M) of this utility model stores non-volatile data such as FPGA configuration files, boot code, and system parameters. It has a large capacity SPINOR Flash, which is suitable for fast loading of FPGA configuration. It is non-volatile and retains configuration information after power failure, ensuring the reliability of system startup.

[0022] (6) The interface circuit of this utility model connects HFT+ / HFT- and HFR+ / HFR-, the differential signal enhances the anti-interference capability, reduces electromagnetic radiation, facilitates docking with RF front-end modules (such as power amplifiers and low noise amplifiers), supports high-speed signal transmission, and is suitable for shortwave broadband communication.

[0023] (7) The DSP (FT-C6416) of this utility model executes complex algorithms such as Turbo encoding / decoding, interleaving / deinterleaving, equalization, modulation and demodulation, controls the entire signal processing flow, coordinates data interaction with FPGA, optimizes high-speed digital signal processing, and has strong computing power.

[0024] (8) The second crystal oscillator (50MHz) of this invention provides the main clock source for the DSP, ensuring that it operates at a high frequency. The high-stability crystal oscillator helps to improve signal processing accuracy and system stability. Two SRAMs (SM7C1061AV33) provide high-speed cache space for storing intermediate calculation results, filter coefficients, FFT data, etc. Static RAM has fast access speed and no refresh delay, making it suitable for high-speed signal processing. The dual SRAM design improves data bandwidth and avoids bottlenecks.

[0025] (9) The second FLASH (SM29LV320) of this utility model stores non-volatile data such as DSP programs, firmware, and system configuration parameters. It can directly run code, save memory overhead, and does not lose data after power failure, ensuring reliable system restart.

[0026] (10) The EMIF of this utility model is a standard interface for connecting the DSP to external storage, realizing efficient read and write control of SRAM and FLASH, and supporting large-capacity external storage expansion. The UART (SM16C752) provides a serial communication interface for debugging, log output, and remote control, supporting dual-channel asynchronous serial communication to improve debugging efficiency. The RS232 interface (SM3232) converts TTL level to RS232 level to realize serial communication with PC or other devices. Attached Figure Description

[0027] To make the content of this utility model easier to understand, the present utility model will be further described in detail below with reference to specific embodiments and accompanying drawings, wherein...

[0028] Figure 1 This is a schematic diagram of the structure of this utility model.

[0029] Figure 2 This is a block diagram of the transmission system structure of this utility model.

[0030] 1. Baseboard; 1-1. FPGA main control chip; 1-2. Audio codec; 1-3. Interface circuit; 1-4. First crystal oscillator; 1-5. First FLASH; 1-6. RS232 interface; 1-7. Power supply; 2. Core board; 2-1. DSP; 2-2. Second crystal oscillator; 2-3. SRAM; 2-4. Second FLASH; 2-5. UART. Detailed Implementation

[0031] To better understand the above technical solutions, the following will provide a detailed explanation of the technical solutions in conjunction with the accompanying drawings and specific implementation methods.

[0032] To make the objectives, technical solutions, and advantages of the embodiments of this utility model clearer, the technical solutions of the embodiments of this utility model will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this utility model, and not all embodiments. The components of the embodiments of this utility model described and shown in the accompanying drawings can generally be arranged and designed in various different configurations.

[0033] Therefore, the following detailed description of the embodiments of the present invention provided in the accompanying drawings is not intended to limit the scope of the claimed invention, but merely to illustrate selected embodiments of the invention. All other embodiments obtained by those skilled in the art based on the embodiments of the present invention without inventive effort are within the scope of protection of the present invention.

[0034] It should be noted that similar labels and letters in the following figures indicate similar items. Therefore, once an item is defined in one figure, it does not need to be further defined and explained in subsequent figures.

[0035] In the description of the embodiments of this utility model, it should be understood that the terms "center", "upper", "lower", "left", "right", "vertical", "horizontal", "inner", "outer", etc., indicate the orientation or positional relationship based on the orientation or positional relationship shown in the drawings, or the orientation or positional relationship commonly used when the utility model product is in use, or the orientation or positional relationship commonly understood by those skilled in the art. They are only for the convenience of describing this utility model and simplifying the description, and are not intended to indicate or imply that the device or component referred to must have a specific orientation, or be constructed and operated in a specific orientation. Therefore, they should not be construed as limitations on this utility model.

[0036] In the description of the embodiments of this utility model, it should also be noted that, unless otherwise explicitly specified and limited, the terms "set," "install," "connect," and "link" should be interpreted broadly. For example, they can refer to a fixed connection, a detachable connection, or an integral connection; they can refer to a direct connection or an indirect connection through an intermediate medium; and they can refer to the internal communication between two components. Those skilled in the art can understand the specific meaning of the above terms in this utility model based on the specific circumstances. The utility model will be further described below with reference to the accompanying drawings. The following embodiments are only used to more clearly illustrate the technical solution of this utility model and should not be used to limit the scope of protection of this utility model.

[0037] (Example 1)

[0038] See Figure 1 A shortwave broadband modem module is disclosed, which adopts a 24kHz bandwidth single-carrier frequency domain equalization system. It includes a baseboard 1 and a core board 2. The baseboard integrates an FPGA main control chip 1-1, an audio codec 1-2, an interface circuit 1-3, a first crystal oscillator 1-4, and a first FLASH 1-5. The audio codec 1-2, the first crystal oscillator 1-4, and the first FLASH 1-5 are all electrically connected to the FPGA main control chip 1-1, and the interface circuit 1-3 is electrically connected to the audio codec 1-2. The core board 2 integrates a DSP 2-1, a second crystal oscillator 2-2, two SRAMs 2-3, and a second FLASH 2-4. The second crystal oscillator 2-2, the two SRAMs 2-3, and the second FLASH 2-4 are all electrically connected to the DSP 2-1. The FPGA main control chip 1-1 and the DSP 2-1 are electrically connected.

[0039] The FPGA main control chip 1-1 uses the GW2A-LV18LQ144C8 model, and the audio codec 1-2 uses the JAD73311 model. The FPGA main control chip 1-1 and the audio codec 1-2 are electrically connected via a McBSP interface. The first crystal oscillator 1-4 uses a clock frequency of 18.432MHz, and the first FLASH 1-5 uses the SM25QH64M chip. The FPGA main control chip (GW2A-LV18LQ144C8) has high-speed parallel processing capabilities, is suitable for real-time signal preprocessing, and its programmability supports flexible function adjustments and upgrades, reducing the DSP burden and improving the overall system efficiency. The audio codec (JAD73311) supports high-quality voice acquisition and playback, meets the voice transmission requirements in shortwave communication, supports multiple audio sampling rates, adapts to different communication scenarios, and connects to the FPGA via the McBSP interface to achieve high-speed data exchange. The first crystal oscillator (18.432MHz) provides the system's main clock reference for FPGA internal logic timing control. 18.432MHz is the standard audio clock frequency (supporting 48kHz, 96kHz, etc.), ensuring audio quality. The high-precision crystal oscillator improves system stability and synchronization performance. The first FLASH (SM25QH64M) is a non-volatile memory that stores FPGA configuration files, boot code, system parameters, and other non-volatile data. Its large-capacity Spinor Flash is suitable for quickly loading FPGA configurations. The non-volatile storage retains configuration information even after power failure, ensuring system startup reliability.

[0040] Interface circuits 1-3 connect the differential signal lines HFT+ and HFT- at the transmitting end and the differential signal lines HFR+ and HFR- at the receiving end. Connecting HFT+ / HFT- and HFR+ / HFR- enhances the differential signal's anti-interference capability, reduces electromagnetic radiation, facilitates interfacing with RF front-end modules (such as power amplifiers and low-noise amplifiers), supports high-speed signal transmission, and is suitable for shortwave broadband communication.

[0041] DSP 2-1 uses the FT-C6416 chip and is electrically connected to the FPGA main control chip 1-1 via the McBSP interface. The DSP (FT-C6416) is a digital signal processor that executes complex algorithms such as Turbo encoding / decoding, interleaving / deinterleaving, equalization, modulation / demodulation, etc., controlling the entire signal processing flow, coordinating data interaction with the FPGA, and is optimized for high-speed digital signal processing with strong computing power. The McBSP is a multi-channel buffered serial port that supports multiple serial communication protocols.

[0042] The second crystal oscillator 2-2 uses a clock frequency of 50MHz. The second crystal oscillator (50MHz) provides the main clock source for the DSP, ensuring that it operates at a high frequency. The high stability of the crystal oscillator helps to improve signal processing accuracy and system stability.

[0043] The two SRAMs 2-3 use the SM7C1061AV33 chip. SRAM is Static Random Access Memory. The two SRAMs (SM7C1061AV33) provide high-speed cache space for storing intermediate calculation results, filter coefficients, FFT data, etc. Static RAM has fast access speed and no refresh delay, making it suitable for high-speed signal processing. The dual SRAM design improves data bandwidth and avoids bottlenecks. The second FLASH 2-4 uses the SM29LV320 chip. Both the two SRAMs 2-3 and the second FLASH 2-4 are electrically connected to the DSP 2-1 through the EMIF interface. The second FLASH (SM29LV320) stores non-volatile data such as DSP programs, firmware, and system configuration parameters. It can directly run code, saving memory overhead. Data is not lost after power failure, ensuring reliable system restart.

[0044] Core board 2 also integrates UART 2-5, and baseboard 1 integrates RS232 interfaces 1-6. UART 2-5 and RS232 interfaces 1-6 are electrically connected, and UART 2-5 and DSP 2-1 are electrically connected via an EMIF interface. UART 2-5 uses the SM16C752 chip, and RS232 interfaces 1-6 use the SM3232 chip. UART is a universal asynchronous transceiver used for serial communication. It can convert parallel data into serial data for transmission, or convert received serial data into parallel data for CPU processing. The UART (SM16C752) provides a serial communication interface for debugging, log output, and remote control, supporting dual-channel asynchronous serial communication to improve debugging efficiency. The RS232 interface (SM3232) converts TTL levels to RS232 levels, enabling serial communication with a PC or other devices.

[0045] The base plate 1 also integrates power supplies 1-7 for powering the shortwave broadband modem module.

[0046] In this embodiment, the shortwave broadband modem module employs single-carrier frequency domain equalization (SCE) technology. SCE is a novel shortwave broadband physical layer waveform, distinct from the traditional 3kHz single-tone serial equalization. It utilizes a 24kHz bandwidth, enabling higher symbol rates. At the transmitting end, a cyclic prefix is ​​added to the symbol block composed of multiple data points for multipath protection. At the receiving end, frequency domain equalization is used to equalize the entire symbol block in a single operation, avoiding the symbol-by-symbol equalization process of traditional time-domain equalization and reducing implementation complexity. Furthermore, the single-carrier signal's spectrum occupies the entire bandwidth, resulting in a lower peak-to-average power ratio and high efficiency in radio power transmission.

[0047] In this embodiment, see Figure 2 At the transmitting end, the DSP transmits bits through Turbo encoding and interleaving, then PSK / QAM modulation. The modulated data signal follows the FPGA synchronization header, is converted into an analog signal by the audio codec, and then transmitted through the interface circuit.

[0048] At the receiving end, the audio signal is converted into a digital signal by an audio codec. The signal first undergoes interference cancellation by an FPGA to filter out narrowband interference within the 24kHz bandwidth. The signal after interference cancellation is then synchronized. Next, the rate and interleaving information are extracted by a DSP before data reception. The data reception process includes equalization, PSK / QAM demodulation, deinterleaving, and Turbo iterative decoding to obtain the final received bits.

[0049] The specific embodiments described above further illustrate the purpose, technical solution, and beneficial effects of this utility model. It should be understood that the above descriptions are merely specific embodiments of this utility model and are not intended to limit this utility model. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of this utility model should be included within the protection scope of this utility model.

Claims

1. A shortwave broadband modem module, characterized in that: The module adopts a 24kHz bandwidth single-carrier frequency domain equalization system; it includes a baseboard (1) and a core board (2). The baseboard integrates an FPGA main control chip (1-1), an audio codec (1-2), an interface circuit (1-3), a first crystal oscillator (1-4), and a first FLASH (1-5). The audio codec (1-2), the first crystal oscillator (1-4), and the first FLASH (1-5) are all electrically connected to the FPGA main control chip (1-1), and the interface circuit (1-3) is electrically connected to the audio codec (1-2). The core board (2) integrates a DSP (2-1), a second crystal oscillator (2-2), two SRAMs (2-3), and a second FLASH (2-4). The second crystal oscillator (2-2), the two SRAMs (2-3), and the second FLASH (2-4) are all electrically connected to the DSP (2-1). The FPGA main control chip (1-1) and the DSP (2-1) are electrically connected.

2. The shortwave broadband modem module according to claim 1, characterized in that: The FPGA main control chip (1-1) is a GW2A-LV18LQ144C8 chip, and the audio codec (1-2) is a JAD73311 chip. The FPGA main control chip (1-1) and the audio codec (1-2) are electrically connected through the McBSP interface.

3. A shortwave broadband modem module according to claim 2, characterized in that: The first crystal oscillator (1-4) uses a clock frequency of 18.432MHz, and the first FLASH (1-5) uses an SM25QH64M chip.

4. A shortwave broadband modem module according to claim 3, characterized in that: The interface circuit (1-3) is connected to the differential signal lines HFT+ and HFT- of the transmitting end and the differential signal lines HFR+ and HFR- of the receiving end.

5. A shortwave broadband modem module according to claim 3, characterized in that: The DSP (2-1) uses the FT-C6416 chip, and the DSP (2-1) is electrically connected to the FPGA main control chip (1-1) through the McBSP interface.

6. A shortwave broadband modem module according to claim 5, characterized in that: The second crystal oscillator (2-2) uses a clock frequency of 50MHz.

7. A shortwave broadband modem module according to claim 5, characterized in that: The two SRAMs (2-3) are SM7C1061AV33 chips, and the second FLASH (2-4) is an SM29LV320 chip. Both SRAMs (2-3) and the second FLASH (2-4) are electrically connected to the DSP (2-1) through an EMIF interface.

8. A shortwave broadband modem module according to claim 7, characterized in that: The core board (2) also integrates a UART (2-5), and the baseboard (1) also integrates an RS232 interface (1-6); the UART (2-5) and the RS232 interface (1-6) are electrically connected, and the UART (2-5) and the DSP (2-1) are electrically connected through an EMIF interface.

9. A shortwave broadband modem module according to claim 8, characterized in that: The UART (2-5) uses the SM16C752 chip, and the RS232 interface (1-6) uses the SM3232 chip.

10. A shortwave broadband modem module according to claim 1, characterized in that: The base plate (1) also integrates a power supply (1-7) for powering the shortwave broadband modem module.

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