Stress buffer type ceramic substrate

Abstract

The utility model discloses a stress buffer type ceramic substrate, including ceramic base layer, upper circuit layer, lower circuit layer, first radiating layer and metal dam, the edge of this ceramic base layer is equipped with stress leak hole, and this metal dam sets up on the upper surface of ceramic base layer. Through adopting the metal dam of arc surface of outside, inside and top, arc surface can effectively buffer stress, prevent the situation that stress is too big between metal dam and ceramic base layer, and cooperate with the lower surface of ceramic base layer and set up radiating groove, and the inner wall surface of radiating groove is coated with second radiating layer, and the design of radiating groove increases the radiating area of ceramic substrate, and the radiating efficiency of ceramic substrate is greatly accelerated, effectively prevent the temperature of ceramic base layer and metal dam from being too high, so as to reduce the difference of volume change produced by thermal expansion of both, reduce the stress between both, so that ceramic substrate is not easy to damage, effectively prolong the life of ceramic substrate and improve its reliability.

Description

Technical Field

[0001] This utility model relates to the field of ceramic substrates, and in particular to a stress-buffered ceramic substrate. Background Technology

[0002] Ceramic substrates are special process boards where copper foil is directly bonded to the surface of an alumina or aluminum nitride ceramic substrate at high temperatures. The resulting ultra-thin composite substrates possess excellent electrical insulation properties, high thermal conductivity, excellent solderability, and high adhesion strength. Like PCB boards, they can be etched with various patterns and have a large current-carrying capacity. Therefore, ceramic substrates have become a fundamental material for high-power power electronic circuit structure technology and interconnection technology. Ultraviolet (UV) light-emitting diodes (LEDs) offer advantages such as energy saving, environmental friendliness, long lifespan, small size, and controllable wavelength. Deep UV LEDs, with an emission wavelength less than 300nm, can be applied in sterilization, water purification, and biochemical detection. UV LEDs are typically packaged using ceramic substrates. To facilitate the packaging of the UV chip, the ceramic substrate has metal dams forming a packaging cavity to house and encapsulate the UV chip.

[0003] Currently, to prevent aging, traditional ceramic substrates for packaging have abandoned the traditional molding process and adopted metal dam packaging. This design can effectively avoid aging problems. However, the thermal expansion coefficient of metal differs greatly from that of ceramic, leading to excessive stress during the packaging process, which reduces the lifespan and reliability of the ceramic substrate. Therefore, it is necessary to improve the existing metal dam packaging substrates. Utility Model Content

[0004] In view of this, the present invention addresses the deficiencies of the existing technology, and its main objective is to provide a stress-buffered ceramic substrate that can effectively solve the problem that, during the use of existing metal dam packaging substrates, the temperature of both the ceramic substrate and the metal dam will rise due to the heat generated during the operation of the UV wafer. Because the thermal expansion coefficients of metal and ceramic are quite different, excessive stress will occur on both, which will easily damage the ceramic substrate and reduce its lifespan and reliability.

[0005] To achieve the above objectives, the present invention adopts the following technical solution:

[0006] A stress-relief type ceramic substrate includes a ceramic base layer, an upper circuit layer, a lower circuit layer, a first heat dissipation layer, and a metal dam.

[0007] The surface of the ceramic substrate has through holes, and through holes are formed with conductive pillars. Stress relief holes are provided at the edges of the ceramic substrate. Heat dissipation grooves are provided on the lower surface of the ceramic substrate, and a second heat dissipation layer is coated on the inner wall of the heat dissipation grooves.

[0008] The upper circuit layer is formed on the upper surface of the ceramic substrate and is conductively connected to the upper end of the conductive post; the lower circuit layer is formed on the lower surface of the ceramic substrate and is conductively connected to the lower end of the conductive post; the first heat dissipation layer is formed on the upper surface of the ceramic substrate and is close to the upper circuit layer.

[0009] The metal dam is set on the upper surface of the ceramic substrate, and the metal dam and the upper surface of the ceramic substrate form a packaging cavity. The aforementioned through hole is opened at the bottom of the packaging cavity. The aforementioned upper circuit layer and the first heat dissipation layer are both formed on the bottom surface of the packaging cavity. The outer side, inner side and top surface of the metal dam are all arc-shaped surfaces.

[0010] As a preferred embodiment, multiple buffer grooves are formed on the lower surface of the ceramic substrate. These multiple buffer grooves are located on both sides of the heat dissipation groove. The design of the buffer grooves can reduce the internal stress of the ceramic substrate and provide buffering.

[0011] As a preferred embodiment, the bottom surfaces of the plurality of buffer grooves are all arc-shaped, which can buffer stress and further reduce stress concentration.

[0012] As a preferred embodiment, the top surface of the heat dissipation groove is provided with a heat conduction hole, and a heat conduction column is formed in the heat conduction hole. The two ends of the heat conduction column are in contact with the first heat dissipation layer and the second heat dissipation layer, respectively.

[0013] As a preferred embodiment, the first heat dissipation layer, the second heat dissipation layer, and the heat-conducting pillar are all made of graphene.

[0014] As a preferred embodiment, a heat dissipation component is provided on the top surface of the heat dissipation groove, and the heat dissipation component is in contact with the second heat dissipation layer.

[0015] As a preferred embodiment, none of the multiple ends of the heat sink extend outside the heat sink groove.

[0016] As a preferred embodiment, stress relief grooves are provided on the inner side of the metal dam.

[0017] As a preferred embodiment, there are two lower circuit layers, with the first heat dissipation layer located between the two lower circuit layers, and the space between the first heat dissipation layer and the two lower circuit layers is filled with ink to form a solder resist layer.

[0018] Compared with the prior art, this utility model has obvious advantages and beneficial effects. Specifically, as can be seen from the above technical solution:

[0019] By employing a metal dam with curved surfaces on the outer, inner, and top sides, the curved surfaces can effectively buffer stress and prevent excessive stress between the metal dam and the ceramic substrate. In addition, heat dissipation grooves are formed on the lower surface of the ceramic substrate, and a second heat dissipation layer is coated on the inner wall of the heat dissipation grooves. The design of the heat dissipation grooves increases the heat dissipation area of ​​the ceramic substrate, greatly accelerates the heat dissipation efficiency of the ceramic substrate, and effectively prevents the temperature of the ceramic substrate and the metal dam from becoming too high. This reduces the difference in volume change caused by thermal expansion between the two, reduces the stress between them, makes the ceramic substrate less prone to damage, effectively extends the life of the ceramic substrate, and improves its reliability.

[0020] To more clearly illustrate the structural features and effects of this utility model, the following detailed description is provided in conjunction with the accompanying drawings and specific embodiments: Attached Figure Description

[0021] Figure 1 This is a cross-sectional view of a preferred embodiment of the present invention.

[0022] Explanation of reference numerals in the attached diagram:

[0023] 10. Ceramic base layer 101. Through hole

[0024] 102. Stress relief hole; 103. Heat dissipation groove

[0025] 104. Buffer groove; 105. Heat conduction hole

[0026] 11. Conductor post; 12. Second heat dissipation layer

[0027] 13. Heat-conducting pillars 14. Heat sink

[0028] 20. Upper circuit layer; 30. Lower circuit layer

[0029] 40. First heat dissipation layer; 50. Metal dam.

[0030] 51. Encapsulation cavity; 52. Stress relief groove

[0031] 60. Solder resist layer. Detailed Implementation

[0032] Please refer to Figure 1 The present invention is shown to have a preferred embodiment of the structure, including a ceramic base layer 10, an upper circuit layer 20, a lower circuit layer 30, a first heat dissipation layer 40, and a metal dam 50.

[0033] The surface of the ceramic base layer 10 has through holes 101 formed therethrough, and through holes 101 have conductive posts 11 formed in them. Stress relief holes 102 are formed at the edges of the ceramic base layer 10. A heat dissipation groove 103 is formed on the lower surface of the ceramic base layer 10, and a second heat dissipation layer 12 is coated on the inner wall of the heat dissipation groove 103. In this embodiment, multiple buffer grooves 104 are formed on the lower surface of the ceramic base layer 10. These buffer grooves 104 are located on both sides of the heat dissipation groove 103. The design of the buffer grooves 104 can reduce the internal stress of the ceramic base layer 10. The bottom surfaces of the multiple buffer grooves 104 are all arc-shaped, which can buffer stress and further reduce stress concentration. In addition, the heat dissipation... The top surface of the heat sink 103 is provided with a heat conduction hole 105, and a heat conduction pillar 13 is formed in the heat conduction hole 105. The two ends of the heat conduction pillar 13 are in contact with the first heat dissipation layer 40 and the second heat dissipation layer 12, respectively. The first heat dissipation layer 40, the second heat dissipation layer 12 and the heat conduction pillar 13 are all made of graphene. In addition, a heat dissipation component 14 is provided on the top surface of the heat sink 103. The heat dissipation component 14 is in contact with the second heat dissipation layer 12. The multiple ends of the heat dissipation component 14 do not protrude from the heat sink 103. The heat dissipation component 14 can be a heat dissipation patch or a finned heat sink. Specifically, the depth of the heat sink 103 is greater than the size of the heat dissipation component 14 to prevent the staff from being scratched by the heat dissipation component 14 when installing the ceramic substrate.

[0034] The upper circuit layer 20 is formed on the upper surface of the ceramic base layer 10 and is conductively connected to the upper end of the conductive post 11; the lower circuit layer 30 is formed on the lower surface of the ceramic base layer 10 and is conductively connected to the lower end of the conductive post 11; the first heat dissipation layer 40 is formed on the upper surface of the ceramic base layer 10 and close to the upper circuit layer 20; in this embodiment, there are two lower circuit layers 30, the first heat dissipation layer 40 is located between the two lower circuit layers 30, and the space between the first heat dissipation layer 40 and the two lower circuit layers 30 is filled with ink to form a solder resist layer 60.

[0035] The metal dam 50 is disposed on the upper surface of the ceramic base layer 10, and the metal dam 50 and the upper surface of the ceramic base layer 10 form an encapsulation cavity 51. The aforementioned through hole 101 is opened at the bottom of the encapsulation cavity 51, and the aforementioned upper circuit layer 20 and first heat dissipation layer 40 are both formed on the bottom surface of the encapsulation cavity 51. The outer side, inner side, and top surface of the metal dam 50 are all arc-shaped surfaces. In this embodiment, a stress relief groove 52 is provided on the inner side of the metal dam 50, which can not only relieve some stress, but also, during encapsulation, high-elasticity adhesive is used for encapsulation. The high-elasticity adhesive will fill the stress relief groove 52. After the high-elasticity adhesive cures and forms the encapsulation component, the design of the stress relief groove 52 can also make the fit between the encapsulation component and the encapsulation cavity 51 more firm and reliable. Moreover, the part of the encapsulation component extending into the stress relief groove 52 is elastic, which can absorb the volume change of thermal expansion of the metal dam 50, effectively preventing excessive stress.

[0036] The key design feature of this utility model is:

[0037] By employing a metal dam with curved surfaces on the outer, inner, and top sides, the curved surfaces can effectively buffer stress and prevent excessive stress between the metal dam and the ceramic substrate. In addition, heat dissipation grooves are formed on the lower surface of the ceramic substrate, and a second heat dissipation layer is coated on the inner wall of the heat dissipation grooves. The design of the heat dissipation grooves increases the heat dissipation area of ​​the ceramic substrate, greatly accelerates the heat dissipation efficiency of the ceramic substrate, and effectively prevents the temperature of the ceramic substrate and the metal dam from becoming too high. This reduces the difference in volume change caused by thermal expansion between the two, reduces the stress between them, makes the ceramic substrate less prone to damage, effectively extends the life of the ceramic substrate, and improves its reliability.

[0038] The above description is merely a preferred embodiment of the present utility model and does not constitute any limitation on the technical scope of the present utility model. Therefore, any minor modifications, equivalent changes and alterations made to the above embodiments based on the technical essence of the present utility model shall still fall within the scope of the technical solution of the present utility model.

Claims

1. A stress-relief type ceramic substrate, characterized in that: It includes a ceramic base layer, an upper circuit layer, a lower circuit layer, a first heat dissipation layer, and a metal dam; The surface of the ceramic substrate has through holes, and through holes are formed with conductive pillars. Stress relief holes are provided at the edges of the ceramic substrate. Heat dissipation grooves are provided on the lower surface of the ceramic substrate, and a second heat dissipation layer is coated on the inner wall of the heat dissipation grooves. The upper circuit layer is formed on the upper surface of the ceramic substrate and is conductively connected to the upper end of the conductive post; the lower circuit layer is formed on the lower surface of the ceramic substrate and is conductively connected to the lower end of the conductive post; the first heat dissipation layer is formed on the upper surface of the ceramic substrate and is close to the upper circuit layer. The metal dam is set on the upper surface of the ceramic substrate, and the metal dam and the upper surface of the ceramic substrate form a packaging cavity. The aforementioned through hole is opened at the bottom of the packaging cavity. The aforementioned upper circuit layer and the first heat dissipation layer are both formed on the bottom surface of the packaging cavity. The outer side, inner side and top surface of the metal dam are all arc-shaped surfaces.

2. The stress-relief ceramic substrate according to claim 1, characterized in that: Multiple buffer grooves are formed on the lower surface of the ceramic base layer, and these multiple buffer grooves are located on both sides of the heat dissipation groove.

3. The stress-relief ceramic substrate according to claim 2, characterized in that: The bottom surfaces of all the multiple buffer slots are curved.

4. The stress-relief ceramic substrate according to claim 1, characterized in that: The top surface of the heat dissipation groove is provided with a heat conduction hole, and a heat conduction column is formed in the heat conduction hole. The two ends of the heat conduction column are in contact with the first heat dissipation layer and the second heat dissipation layer, respectively.

5. The stress-relief ceramic substrate according to claim 4, characterized in that: The first heat dissipation layer, the second heat dissipation layer, and the heat-conducting pillars are all made of graphene.

6. The stress-relief ceramic substrate according to claim 1, characterized in that: A heat dissipation component is provided on the top surface of the heat dissipation groove, and the heat dissipation component is in contact with the second heat dissipation layer.

7. The stress-relief ceramic substrate according to claim 6, characterized in that: None of the ends of the heat sink extend outside the heat sink groove.

8. The stress-relief ceramic substrate according to claim 1, characterized in that: Stress relief grooves are provided on the inner side of the metal dam.

9. The stress-relief ceramic substrate according to claim 1, characterized in that: There are two lower circuit layers. The first heat dissipation layer is located between the two lower circuit layers, and the space between the first heat dissipation layer and the two lower circuit layers is filled with ink to form a solder resist layer.

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