A source-down MOS device based on planar MOS technology

Abstract

This invention discloses a source-down MOS device based on planar MOS technology, relating to the field of semiconductor device technology. It includes a semiconductor substrate, an active region, and a gate region. The active region is formed on the surface of the semiconductor substrate, and the gate region is located above the active region. A drain and a source are disposed within the active region. The drain on one side is electrically connected to the front side of the chip via a forward metal electrode, which is located within the gate region. The source on the other side is connected to the semiconductor substrate via an electrode connection region, forming a good ohmic contact. A substrate metal electrode is disposed at the bottom of the semiconductor substrate. This invention features a reasonable layout, compact structure, and low process cost. Compared to the heterogeneous structure of Diodes, it reduces the need for two masking steps (main trench and field trench), avoiding stress and defects caused by trench filling. It also boasts high integration; compared to Infineon's package-level source-down design, source interconnection is directly achieved within the chip, supporting multi-device stacking designs and saving space occupied by pads and lead channels.

Description

Technical Field

[0001] This utility model relates to the field of semiconductor device technology, and in particular to a source-down MOS device based on planar MOS technology. Background Technology

[0002] MOSFETs are among the most important power semiconductor devices in modern electronic devices, playing a crucial role in power management, motor control, inverters, and other applications. As electronic devices evolve towards miniaturization, higher efficiency, and higher power density, higher demands are placed on MOSFET performance, particularly in terms of on-resistance, switching speed, and thermal management. The source-down structure, as an innovative power MOSFET packaging and structural technology, has received widespread attention in recent years.

[0003] Diodes Incorporated's patents (such as US20210151596A) propose a source-down configuration field-effect transistor. This is achieved by creating trenches in a semiconductor chip and embedding conductive gate material and a conductive field plate within those trenches. However, this approach requires deep trench etching and filling, placing higher demands on equipment and processes. Furthermore, the need to form a vertical field plate structure increases manufacturing complexity. The trench and field plate structures increase parasitic capacitance, which may affect the transistor's switching speed and frequency performance. It is also incompatible with existing planar MOS processes, necessitating the development of new process flows and equipment.

[0004] Infineon's source-down devices (such as OptiMOS) TM The series adopts flip-chip technology, directly connecting the source pads to the package substrate. Although this simplifies the chip structure, it is limited by package parasitic parameters (such as lead inductance ~1.2nH). Its quality factor [FoM = Rds(on)·Qg] drops by up to 40% in the 2.4GHz band compared to lower frequency conditions. It is also not easy to integrate with other devices, such as the BCD structure. Further optimization is still needed to improve the integration level.

[0005] Therefore, how to provide a source-down MOS device based on planar MOS technology, which adopts an embedded source interconnect structure to achieve source-down layout, while being compatible with traditional planar MOS technology and effectively reducing packaging costs, has become a technical problem that urgently needs to be solved by those skilled in the art. Utility Model Content

[0006] The purpose of this invention is to provide a source-down MOS device based on planar MOS technology, which solves the high-difficulty and high-cost problems of deep trench etching and filling required by existing technologies.

[0007] To solve the above-mentioned technical problems, the present invention adopts the following technical solution:

[0008] This invention discloses a source-down MOS device based on planar MOS technology, comprising a semiconductor substrate, an active region, and a gate region. The active region is formed on the surface of the semiconductor substrate, and the gate region is located above the active region. The active region includes the entire region composed of an inversion layer and a drift layer.

[0009] The active region is provided with a drain and a source. The drain on the upper side is electrically connected to the front side of the chip through a positive metal electrode, which is located in the gate region. The source on the other side is connected to the semiconductor substrate through an electrode connection region to form a good ohmic contact. The electrode connection region is located in the inversion layer provided on the top of the semiconductor substrate. The bottom of the semiconductor substrate is provided with a substrate metal electrode for lead-out.

[0010] Preferably, the semiconductor substrate is made of single-crystal semiconductor material and is a heavily doped substrate layer, the inversion layer is a highly doped isolation layer, and the drift layer is a lightly doped epitaxial layer.

[0011] Preferably, the drift layer has multiple well regions, the source electrode is located in the well region and corresponds one-to-one with the position of the electrode connection region below; the drain electrode is located at the top of the drift layer and is located between any two adjacent source electrodes.

[0012] Preferably, the gate region includes a gate oxide layer, a gate, and a gate insulating layer arranged sequentially. The gate oxide layer is located above the drift layer. The gate is located above the gate oxide layer, and a plurality of gate grooves are reserved therefor corresponding to the drain and the source. The gate insulating layer fills and covers the gate. After the gate insulating layer is connected, the gate groove corresponding to the source is completely closed. The positive metal electrode is disposed in the gate groove corresponding to the drain. A second insulating layer is disposed at the positive metal electrode.

[0013] Preferably, the thickness of the semiconductor substrate after thinning is set to 325 μm to 425 μm.

[0014] Compared with the prior art, the beneficial technical effects of this utility model are as follows:

[0015] This invention discloses a source-down MOS device based on planar MOS technology, comprising a semiconductor substrate, an active region and a gate region sequentially disposed on the upper part of the semiconductor substrate, the active region including an inversion layer and a drift layer; specifically, a drain and a source are disposed on the drift layer, the drain located on one side is electrically connected to the front side of the chip through a forward metal electrode, the forward metal electrode being located within the gate region; the source located on the other side is connected to the semiconductor substrate through an electrode connection region, and a substrate metal electrode for lead-out is disposed at the bottom of the semiconductor substrate.

[0016] 1) Embedded source interconnect: Unlike traditional LDMOS devices, the source is located at the bottom of the device. Through specific doping and structural design, the electrode connection region on the inversion layer forms a current channel, which enables the source to form a good ohmic contact with the substrate and reduces the on-resistance. The drain is located at the top of the device and forms a certain distance from the source to achieve the device's withstand voltage function.

[0017] 2) The gate region is located between the source region and the drain region and is isolated from the semiconductor substrate by the gate oxide layer. It is used to control the conduction and cutoff of the device.

[0018] 3) Compatible with traditional planar MOS processes: Utilizing existing MOS processes, such as drift layers, gate trenches, and doping steps, requires additional ion implantation and back-side metallization processes. This eliminates the need for complex heterostructures, reducing manufacturing costs.

[0019] 4) Double-sided heat dissipation optimization: The source electrode on the back side is in direct contact with the metal electrode on the substrate, which, combined with the drain electrode heat dissipation path on the front side, forms a double-sided heat dissipation structure, which significantly improves thermal management efficiency.

[0020] In summary, this utility model has a reasonable layout, compact structure, and low process cost. Compared with the heterogeneous structure of Diodes, it reduces the masking steps of the main trench and field plate trench, avoiding stress and defects caused by trench filling. It has high integration. Compared with Infineon's package-level source bottom placement, the chip directly realizes source interconnection, supports multi-device stacking design, and saves space occupied by pads and lead channels. Attached Figure Description

[0021] The present invention will be further described below with reference to the accompanying drawings.

[0022] Figure 1 This is a schematic diagram of the source-down MOS device structure based on planar MOS technology according to this utility model;

[0023] Figure 2 This is a diagram showing the structural changes in steps one through three of this utility model;

[0024] Figure 3 This is a diagram showing the structural changes in steps four through seven of this utility model;

[0025] Figure 4 This is a diagram showing the structural changes in steps eight to ten of this utility model;

[0026] Figure 5 This is a diagram showing the structural changes in steps eleven to fourteen of this utility model;

[0027] Figure 6 This is a flowchart of the preparation method of this utility model.

[0028] Explanation of reference numerals in the attached figures: 1. Semiconductor substrate; 2. Inversion layer; 3. Electrode connection region; 4. Drift layer; 5. Well region; 6. Drain; 7. Source; 8. Gate oxide layer; 9. Gate; 10. Gate insulating layer; 11. Forward metal electrode; 12. Second insulating layer; 13. Substrate metal electrode. Detailed Implementation

[0029] To make the technical problem to be solved, the technical solution, and the beneficial effects of this utility model clearer, the present utility model will be further described in detail below with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are only used to explain this utility model and are not intended to limit this utility model.

[0030] like Figure 1-5 As shown, a source-down MOS device based on planar MOS technology includes a semiconductor substrate 1, an active region and a gate region, wherein the active region is formed on the surface of the semiconductor substrate and the gate region is located above the active region;

[0031] The active region is provided with a drain 6 and a source 7. The drain 6 located on the upper side is electrically connected to the front side of the chip through a positive metal electrode 11, which is located in the gate region. The source 7 located on the other side is connected to the semiconductor substrate 1 through an electrode connection region 3 and forms a good ohmic contact. The electrode connection region 3 is located in the inversion layer 2 provided on the top of the semiconductor substrate 1.

[0032] The bottom of the semiconductor substrate 1 is provided with a substrate metal electrode 13 for lead-out.

[0033] Specifically, the active region includes the entire region composed of the inversion layer 2 and the drift layer 4, the electrode connection region 3 is epitaxially formed to form the drift layer 4, and the inversion layer 2 is an isolation layer formed by epitaxy, diffusion or ion implantation.

[0034] The semiconductor substrate 1 is made of single-crystal semiconductor material and is a heavily doped substrate layer. The inversion layer 2 is a highly doped isolation layer, and the drift layer 4 is a lightly doped epitaxial layer.

[0035] Specifically, the drift layer 4 is provided with multiple well regions 5, the source electrode 7 is located in the well region 5 and corresponds one-to-one with the position of the electrode connection region 3 below; the drain electrode 6 is located on the top of the drift layer 4 and is located between any two adjacent source electrodes 7.

[0036] Specifically, the gate region includes a gate oxide layer 8, a gate 9, and a gate insulating layer 10 arranged sequentially. The gate oxide layer 8 is located above the drift layer 4. The gate 9 is located above the gate oxide layer 8, and multiple gate grooves are reserved therefor corresponding to the drain 6 and the source 7. The gate insulating layer 10 fills and covers the gate 9. After the gate insulating layer 10 is connected, the gate groove corresponding to the source 7 is completely sealed. The positive metal electrode 11 is disposed in the gate groove corresponding to the drain 6. A second insulating layer 12 is disposed at the positive metal electrode 11. The second insulating layer 12 is located above the gate insulating layer 10. The main function of the second insulating layer 12 is to achieve electrical isolation and prevent short circuit between the drain and adjacent conductors (such as the source, gate, or substrate). It can also play an environmental protection role, blocking corrosion or leakage caused by moisture, pollutants, or ion migration. The thickness and number of layers of the positive metal electrode 11 and the second insulating layer 12 can be further set according to actual needs.

[0037] Specifically, the gate oxide layer 8 is made of thermal SiO2 with a thickness of 24 nm; the gate 9 is made of polysilicon or a metal gate, specifically Pt, Pd, NiSi, or CoSi, with a thickness of 450 nm; the gate insulating layer 10 is made of SiO2 or SiO2. x N y The thickness is designed to be 1200nm.

[0038] like Figure 6 As shown, a method for fabricating a source-down MOS device based on planar MOS technology specifically includes the following steps:

[0039] Step 1: Substrate fabrication. A P-type or N-type silicon wafer is selected to fabricate the semiconductor substrate 1. Typically, a P-type substrate is used to fabricate NMOS, and an N-type substrate is used to fabricate PMOS. Simultaneously, after selecting the silicon wafer, a heavily doped substrate layer is formed through doping processes (CZ method, epitaxy, ion implantation, or diffusion), with a doping concentration reaching 10⁻⁶. 19 ~10 20 cm -3 The substrate layer serves as a support for the inversion layer 2, and its main functions are to reduce resistance, support epitaxial growth, and optimize device performance.

[0040] Step 2: Epitaxial growth, diffusion or ion implantation to form inversion layer 2. Inversion layer 2 is located above semiconductor substrate 1 and is used to isolate semiconductor substrate from drift layer. Since the resistance of heavily doped substrate layer is low and cannot withstand high voltage, inversion layer 2 can provide high-resistance drift region to balance conduction and withstand voltage.

[0041] Step 3: Ion implantation to form electrode connection region 3. According to the product type, corresponding ions are implanted at the designated position of the inversion layer 2 to form multiple independent heavily doped electrode regions, which become the current channel for the source 6 to connect with the semiconductor substrate 1, and at the same time, a good ohmic contact is formed between the two.

[0042] Step 4: Epitaxially forming drift layer 4, located between the source and drain, to withstand high voltage and optimize conduction characteristics. This layer belongs to the pre-prepared low-doped (lightly doped) region, with a specific doping concentration of approximately 10. 14 ~10 15 cm -3 Among them, inversion layer 2 and drift layer 4 together form the active region;

[0043] Step 5: Ion implantation or diffusion forms well region 5, located on drift layer 4 and positioned one-to-one with the electrode connection region 3, providing a basis for source region formation. The doping concentration of well region 5 can reach 10. 16 ~10 17 cm -3 ;

[0044] Step 6: Ion implantation forms drain region 6, located at the top of the drift layer and between two adjacent well regions. After ion implantation, an independent highly doped region is formed, which is used to connect with the positive metal electrode above.

[0045] Step 7: Ion implantation forms source region 7, located in the middle of the well region. After ion implantation, an independent highly doped region is formed; specifically, the doping concentration of drain region 6 and source region 7 can reach 10. 19 ~10 20 cm -3 ;

[0046] Step 8: Formation of the gate oxide layer, which serves as an insulating medium between the gate and the active region to prevent leakage; specifically, Thermal SiO2 (silicon dioxide generated through a thermal oxidation process) is used, with a thickness designed to be 24nm.

[0047] Step 9: Gate fabrication. The gate is located above the gate oxide layer, and multiple gate grooves are reserved to correspond to the drain and source. Specifically, polysilicon or metal gates (such as TiN, TaN+W) are used.

[0048] Step 10: The first insulating layer protects the gate to prevent damage during subsequent processes.

[0049] Step 11: First layer metallization to form a positive metal electrode;

[0050] Step 12: The second insulating layer protects the positive metal electrode, achieving frontal protection. Firstly, it provides passivation protection to prevent oxidation, corrosion, or mechanical damage to the metal electrode. Secondly, it provides dielectric isolation to reduce parasitic capacitance between adjacent metal electrodes.

[0051] Step 13: Thinning the back side of the substrate, mainly to reduce the substrate thickness, thereby making the overall product thinner to meet packaging requirements;

[0052] Step 14: Metallize the back side to form a substrate metal electrode, providing a connection interface between the chip and the packaging substrate.

[0053] Specifically, in step four, the drift layer is formed using planar MOS technology, which simplifies the manufacturing process and reduces manufacturing costs.

[0054] Specifically, in step thirteen, the back side of the substrate is thinned to a thickness of 325μm to 425μm, which can reduce thermal resistance and improve heat dissipation; at the same time, it can meet packaging requirements and realize the fabrication of thin chips.

[0055] The source-side-down MOS device manufactured in this invention forms a double-sided heat dissipation channel by leading the source to the back of the chip and cooperating with the drain on the top. The source on the back of the chip can contact and connect with the substrate metal electrode, forming an efficient main heat dissipation path. The substrate metal electrode, made of copper or aluminum, serves as both part of the electrical connection and the main heat dissipation path. Meanwhile, the drain on the front can still serve as an auxiliary heat dissipation path. This double-sided heat dissipation design greatly improves thermal management efficiency and is crucial for meeting the development needs of modern electronic devices for miniaturization, high efficiency, and high power density.

[0056] Specifically, taking PMOS (or NMOS) as an example, the detailed fabrication process is as follows:

[0057] Step 1: Substrate fabrication. Select an N-type (or P-type) silicon wafer and form a heavily doped substrate layer through epitaxy, one of the doping processes, i.e., form an N++ (or P++) substrate.

[0058] Step 2: An epitaxial P+ (or N+) inversion layer 2 is formed, which completely covers the substrate layer.

[0059] Step 3: Inject phosphorus (or boron) ions to form N+ (or P+) electrode connection region 3;

[0060] Step 4: Epitaxially form an N- (or P-) drift layer 4, located between the source and drain, to withstand high voltage;

[0061] Step 5: Ion implantation or diffusion to form a well region. Ions are implanted at designated locations in drift layer 4 to form a P+ (or N+) well region.

[0062] Step 6: Ion implantation to form a drain region. Phosphorus (or boron) ions are implanted at the top of the drift layer 4 and between two adjacent well regions 5 to form an independent highly doped region, which is the N+ (or P+) drain region.

[0063] Step 7: Ion implantation to form the source region. Phosphorus (or boron) ions are implanted into the trap region 5 to form a highly doped region, which is the N+ (or P+) source region.

[0064] Step 8: Formation of the gate oxide layer, which is made of Thermal SiO2 material with a thickness of 24nm;

[0065] Step 9: Gate fabrication, made of polycrystalline silicon, with multiple gate trenches reserved, the width of which is 650nm;

[0066] Step 10: The first insulating layer protects the gate, specifically made of SiO2 or SiOxNy material with a thickness of 1200nm;

[0067] Step 11: The first layer of metallization forms a positive metal electrode 11, which is formed by depositing metal into the gate groove corresponding to the drain region;

[0068] Step 12: The second insulating layer protects the positive metal electrode;

[0069] Step 13: Substrate backside thinning treatment;

[0070] Step 14: Metallize the back side to form the substrate metal electrode.

[0071] Specifically, in step four, the drift layer is formed using a planar MOS process.

[0072] Specifically, in step thirteen, the back side of the substrate is thinned, and the thickness of the thinned liner is 325μm to 425μm.

[0073] The product prepared by this method has a cell size of 8.8 μm to 11.6 μm; the specific doping concentration in each region is set reasonably according to the actual performance requirements.

[0074] It should be noted that, in this document, relational terms such as "first" and "second" are used only to distinguish one entity or operation from another, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Furthermore, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or apparatus.

[0075] The embodiments described above are merely preferred embodiments of the present utility model and are not intended to limit the scope of the present utility model. Various modifications and improvements made to the technical solutions of the present utility model by those skilled in the art without departing from the spirit of the present utility model should fall within the protection scope defined by the claims of the present utility model.

Claims

1. A source-down MOS device based on planar MOS technology, characterized in that: It includes a semiconductor substrate (1), an active region and a gate region, wherein the active region is formed on the surface of the semiconductor substrate and the gate region is located above the active region; the active region includes the entire region composed of an inversion layer (2) and a drift layer (4); The active region is provided with a drain (6) and a source (7). The drain (6) located on the upper side is electrically connected to the front side of the chip through a positive metal electrode (11), which is located in the gate region. The source (7) located on the other side is connected to the semiconductor substrate (1) through an electrode connection region (3) and forms a good ohmic contact. The electrode connection region (3) is located in the inversion layer (2) provided on the top of the semiconductor substrate (1). The bottom of the semiconductor substrate (1) is provided with a substrate metal electrode (13) for lead-out.

2. The source-down MOS device based on planar MOS technology according to claim 1, characterized in that: The semiconductor substrate (1) is made of single-crystal semiconductor material and is a heavily doped substrate layer. The inversion layer (2) is a highly doped isolation layer, and the drift layer (4) is a lightly doped epitaxial layer.

3. The source-down MOS device based on planar MOS technology according to claim 1, characterized in that: The drift layer (4) is provided with multiple well regions (5), the source electrode (7) is located in the well region (5) and corresponds one-to-one with the position of the electrode connection region (3) below; the drain electrode (6) is located on the top of the drift layer (4) and is located between any two adjacent source electrodes (7).

4. The source-down MOS device based on planar MOS technology according to claim 1, characterized in that: The gate region includes a gate oxide layer (8), a gate (9), and a gate insulating layer (10) arranged in sequence. The gate oxide layer (8) is located above the drift layer (4). The gate (9) is located above the gate oxide layer (8), and a plurality of gate grooves are reserved corresponding to the drain (6) and the source (7). The gate insulating layer (10) fills and covers the gate (9). After the gate insulating layer (10) is connected, the gate groove corresponding to the source (7) is completely closed. The positive metal electrode (11) is disposed in the gate groove corresponding to the drain (6), and a second insulating layer (12) is disposed at the positive metal electrode (11).

5. The source-down MOS device based on planar MOS technology according to claim 1, characterized in that: The thickness of the semiconductor substrate (1) after thinning is set to 325μm~425μm.

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