rear side device structure

Abstract

A backside device structure is provided. The backside device structure according to the present disclosure includes a substrate having a front side and a back side, a fin structure located over the front side, a plurality of nanostructures disposed over the fin structure, a gate structure encasing each of the nanostructures, a doped region disposed over the substrate back side, a backside dielectric layer located over the doped region, and a first contact feature extending through the backside dielectric layer to interface the doped region.

Description

Technical Field

[0001] This disclosure relates to a rear-side device structure. Background Technology

[0002] The semiconductor integrated circuit (IC) industry has experienced exponential growth. Technological advancements in IC materials and design have spawned generations of ICs, each with circuits that are smaller and more complex than the previous generation. In IC development, functional density (i.e., the number of interconnects per wafer area) typically increases, while geometry (i.e., the smallest component (or line) that can be produced using manufacturing processes) decreases. This scaling down process usually provides benefits by increasing production efficiency and reducing associated costs. However, this scaling down also increases the complexity of handling and manufacturing ICs.

[0003] The reduction in device size puts stress on electrical routing and component placement in back-end-of-line (BEOL) architectures. In some applications, larger active or passive components may be placed in certain layers of the front-end interconnect. This approach presents several challenges. For example, these active or passive components may occupy valuable space in the front-end interconnect, potentially leading to difficulties in meeting footprint or design requirements. Furthermore, electrical signals traveling to and from these passive or active components may need to traverse more than one metallization layer, potentially resulting in undesirable increases in resistance and capacitance. Utility Model Content

[0004] According to some embodiments of the present disclosure, the rear-side device structure includes a substrate having a front side and a rear side, a fin structure located above the front side, a plurality of nanostructures located above the fin structure, a gate structure covering each of the nanostructures, a doped region located above the rear side of the substrate, a rear-side dielectric layer located above the doped region, and a first contact feature extending through the rear-side dielectric layer and interfacing with the doped region.

[0005] According to some embodiments of the present disclosure, the rear-side device structure includes a substrate having a front side and a rear side, a plurality of nanostructures disposed above the front side, a gate structure covering each of the nanostructures, a front-side interconnect structure disposed on the gate structure and the nanostructures, a doped region disposed above the rear side of the substrate, and a rear-side device disposed above the doped region.

[0006] According to some embodiments of this disclosure, a rear-side device structure includes a substrate having a front side and a rear side, a plurality of nanostructures disposed above the front side of the substrate, a gate structure covering each of the nanostructures, a doped region disposed above the rear side of the substrate, and a rear-side device disposed above the doped region. The rear-side device includes a rear-side dielectric layer and contact features extending through the rear-side dielectric layer and mediating the doped region. Attached Figure Description

[0007] The contents of this disclosure can be best understood in conjunction with the accompanying drawings and the following detailed description. Note that, in accordance with standard industry practice, the various features are not drawn to scale and are for illustrative purposes only. In practice, the dimensions of the various features may be arbitrarily increased or decreased for clarity of discussion.

[0008] Figure 1 A flowchart illustrating a method 100 for forming a semiconductor device according to one or more of the present disclosure;

[0009] Figures 2 to 20 Explain the basis for one or more states according to this disclosure. Figure 1 A partial cross-sectional view of the work-in-progress (WIP) structure in the manufacturing process of the method;

[0010] Figure 21 A flowchart illustrating a method 400 for forming a semiconductor device according to one or more of the present disclosure;

[0011] Figures 22 to 44 Explain the basis for one or more states according to this disclosure. Figure 21 A partial cross-sectional view of the work-in-progress (WIP) structure in the manufacturing process of the method;

[0012] Figure 45 A schematic cross-sectional view of a device grain including a first type of substrate through-hole, according to one or more states of this disclosure;

[0013] Figure 46 A schematic cross-sectional view illustrating one or more embodiments of an apparatus including a second type of substrate through-hole according to the present disclosure.

[0014] [Symbol Explanation]

[0015] 100: Method

[0016] Blocks 102, 104, 106, 108, 110, 112, 114, 116, 118, 120, 122, 124

[0017] 200: WIP structure

[0018] 200B1, 200B2, 200B3, 200B4, 200B5: Rear-side device

[0019] 200F: Front

[0020] 202:Substrate

[0021] 202D1: Type I doped region

[0022] 202D2: Type II dopant region

[0023] 202N:n-well

[0024] 202P:p-trap

[0025] 203: Ion Fabric Embedding Mask

[0026] 204: Stacking

[0027] 206: Sacrifice Layer

[0028] 208: Channel Layer

[0029] 210: Hard mask layer

[0030] 212: Fin-shaped structure

[0031] 212B: Basal fin structure

[0032] 212C: Channel Area

[0033] 212SD: Source / Drain Region

[0034] 214: Isolation Features

[0035] 216: Dummy Dielectric Layer

[0036] 218: Dummy Electrode Layer

[0037] 220: Dummy gate stack

[0038] 222: Hard masking layer at the top of the gate

[0039] 223: Silicon oxide layer

[0040] 224: Silicon nitride layer

[0041] 226: Gate spacer layer

[0042] 228: Source / Drain Trench

[0043] 230: Virtual Layer

[0044] 232: Internal spacer groove

[0045] 234: Characteristics of internal spacers

[0046] 240: Source / Drain Characteristics

[0047] 242: Contact Etching Termination Layer

[0048] 244: Interlayer dielectric layer

[0049] 245: Covering layer

[0050] 246: Gate Trench

[0051] 250: Gate structure

[0052] 270: Front interconnect structure

[0053] 275: Bonding layer

[0054] 280: Carrier substrate

[0055] 290: Rear Interconnect Structure

[0056] 300: Method

[0057] 302: First rear-side isolation feature

[0058] 303: Second posterior isolation feature

[0059] 304: Silicide layer

[0060] 305: Block Isolation Feature

[0061] 306: Backside dielectric layer

[0062] 308: First contact feature

[0063] 310: Second contact feature

[0064] 312: Third contact feature

[0065] 316: Fourth contact feature

[0066] 318: Fifth contact feature

[0067] 320: First source / drain characteristics

[0068] 322: Second source / drain characteristics

[0069] 324: Sixth contact feature

[0070] 326: Seventh Contact Feature

[0071] 328: Interface Layer

[0072] 330: Gate dielectric layer

[0073] 332: Polycrystalline silicon electrode layer

[0074] 334: Gate spacer layer

[0075] 336: Characteristics of silicides

[0076] 338: Rear gate contact

[0077] 340: Rear isolation layer

[0078] 342: Isolation Features

[0079] 344: Gate dielectric layer

[0080] 345: Long gate structure

[0081] 346: Gate electrode

[0082] 348: Source / Drain Node

[0083] 400: Method

[0084] Blocks 402, 404, 406, 408, 410, 412, 414, 416, 418, 420, 422, 424, and 426:

[0085] 500: Device grain

[0086] 510:Substrate

[0087] 510B: Rear-side device

[0088] 510F: Front-side device

[0089] 550: Micrometer-scale substrate via

[0090] 560: Nanoscale substrate through-hole

[0091] 1000: Deep Trap Ion Implantation Process

[0092] 2000: Selective Deep Trap Ion Implantation Technology

[0093] 2080: Channel component

[0094] D1: First Depth

[0095] D2: Second Depth

[0096] T1: First thickness

[0097] T2: Second thickness

[0098] TW: Wafer Thickness

[0099] X, Y, Z: Direction Detailed Implementation

[0100] The following disclosure provides numerous different embodiments or instances for implementing various features of the provided subject matter. Specific examples of components and arrangements described below are used to simplify this disclosure. Of course, these are merely examples and are not intended to be limiting. For example, the following description of forming a first feature above or on a second feature may include embodiments in which the first and second features are formed in direct contact, and may also include embodiments in which an additional feature is formed between the first and second features such that the first and second features do not need to be in direct contact. Furthermore, element symbols or letters may be repeated in various instances of this disclosure. This repetition is for simplicity and clarity and does not in itself specify a relationship between the various embodiments or configurations discussed.

[0101] Furthermore, for ease of description, spatial relative terms such as “below,” “under,” “below,” “above,” and “above” may be used herein to describe the relationship between one element or feature and another element or feature as shown in the figures. In addition to the orientations depicted in the figures, the spatial relative terms are intended to cover different orientations of the device in use or operation. The device may be oriented in other ways (rotated 90 degrees or otherwise), and the spatial relative descriptive terms used herein may be interpreted accordingly.

[0102] Furthermore, when using terms such as "about," "approximately," etc., to describe a number or range of numbers, the term is intended to encompass a reasonable range of numbers that take into account variations inherent in manufacturing, as understood by one of ordinary skill in the art. For example, based on known manufacturing tolerances associated with manufacturing features having characteristics related to that number, a number or range of numbers encompasses a reasonable range including said number, such as within + / - 10% of said number. For example, a material layer with a thickness of "about 5 nm" can encompass a size range from 4.25 nm to 5.75 nm, where the manufacturing tolerances associated with the deposited material layer are known to one of ordinary skill in the art to be + / - 15%.

[0103] Semiconductor manufacturing typically includes front-end-of-line (FEOL) and back-end-of-line (BEOL) processes. The FEOL process involves the steps of forming individual components on a semiconductor substrate. The BEOL process involves the steps of forming interconnect structures to interconnect the individual components formed by the FEOL process. As integrated circuit (IC) technology advances to smaller technology nodes, multi-gate metal-oxide-semiconductor field-effect transistors (MOSFETs or multi-gate devices) have been widely adopted at the FEOL level to improve gate control by increasing gate channel coupling, reducing turn-off current, and reducing the short-channel effect (SCE). A multi-gate device generally refers to a device having a gate structure or a portion thereof located on more than one side of the channel region. Fin-like field-effect transistors (FinFETs) and gate-all-around (GAA) transistors are examples of multi-gate devices. FinFETs have raised channels that are covered by a gate on more than one side (e.g., the gate covers the top and sidewalls of a semiconductor material "fin" extending from the substrate). GAA transistors have a gate structure that may extend partially or entirely around the channel region, thereby providing access to the channel region on two or more sides. Because the gate structure surrounds the channel region, GAA transistors can also be called surrounding gate transistors (SGT) or multi-bridge-channel (MBC) transistors.

[0104] Besides multi-gate devices, many circuit applications include bipolar junction transistors (BJTs), diodes, resistors, capacitors, planar devices, or embedded dynamic random access memory (eDRAM) devices, which are incompatible with the fabrication processes of multi-gate devices or cannot be satisfactorily replaced by them. Because BJTs, diodes, resistors, capacitors, or planar devices are much larger, they are typically fabricated at the BEOL level in a metal layer far from the FEOL structure. This increased distance necessitates additional metal routing and additional parasitic resistances and capacitances in the interconnect structure. In some practices, eDRAM is implemented using multi-gate devices fabricated at the FEOL level. While eDRAM implemented using multi-gate devices is a viable solution, it may not have satisfactory memory retention and requires frequent refreshes.

[0105] This disclosure provides a method and structure for implementing passive and active components on the back side of a substrate, while fabricating FEOL devices on the front side of the substrate. In the process, a selective deep ion implantation process is used to form an ion implantation profile in the substrate before fabricating the multi-gate devices. After fabricating the multi-gate devices and front-side interconnect structures above the front side of the substrate, the substrate is flipped over, and back-side devices are formed above or around the ion implantation profiles. Back-side devices may include diodes, bipolar junction transistors (BJTs), resistors, capacitors, planar transistors, or embedded DRAM. Implementing components on the back side of the substrate provides a smaller footprint, thereby improving performance and reliability. Back-side components can also reduce parasitic resistance, reduce parasitic capacitance, improve energy efficiency and performance, or improve memory retention.

[0106] The various aspects of this disclosure will now be described in more detail with reference to the accompanying drawings. Figure 1 and Figure 21 This document provides flowcharts illustrating methods 100 and 400 for forming semiconductor structures from work-in-progress (WIP) structures according to embodiments of this disclosure. Methods 100 and 400 are merely examples and are not intended to limit this disclosure to the content explicitly described in methods 100 and 400. Additional steps may be provided before, during, and after method 100 or 400, and some described steps may be replaced, eliminated, or moved for additional embodiments of the method. For simplicity, not all steps are described in detail herein. The following is in conjunction with… Figures 2 to 20 Description method 100, Figures 2 to 20According to Figure 1 Partial cross-sectional views of the WIP structure 200 of an embodiment of method 100 at different manufacturing stages. The following is in conjunction with... Figures 22 to 44 Description method 400, Figures 22 to 44 According to Figure 21 Partial cross-sectional views of the WIP structure 200 at different manufacturing stages of an embodiment of method 300. Since the WIP structure 200 will be manufactured as a semiconductor structure or semiconductor device, it may be referred to herein as a semiconductor structure 200 or a semiconductor device 200, depending on the context. For the avoidance of doubt, Figures 2 to 20 and Figures 22 to 44 The X, Y, and Z directions are perpendicular to each other. Throughout this disclosure, unless otherwise expressly stated, the same element symbols denote the same features or steps.

[0107] Methods 100 and 400 include the step of forming a GAA transistor. Methods 100 and 400 first form a dopant placement profile in a substrate and form a stack over the substrate, wherein the stack includes multiple channel layers interleaved by multiple sacrificial layers. After forming the GAA transistor, methods 100 and 400 include the step of forming various back-side devices. Regarding the formation of the GAA transistor, methods 100 and 400 include the step of patterning the stack to form a fin structure. Method 100 retains the sacrificial layer in the channel regions of the fin structure until after source / drain features are formed in the source / drain regions of the fin structure. Unlike method 100, method 400 removes the sacrificial layer after forming the dummy gate stack and deposits dummy layers to interleave the channel layers. After forming source / drain features in the source / drain regions of the fin structure, the dummy layer is removed. Methods 100 and 400 will be described below. For brevity, detailed descriptions of similar operations may be omitted. Unless otherwise expressly stated in this disclosure, similar references relating to the descriptions of methods 100 and 400 should be considered interchangeable. First, focus on... Figure 1 Method 100.

[0108] See Figure 1 and Figures 2 to 4Method 100 includes block 102, in which a dopant placement profile is formed in substrate 202. The dopant placement profile formed at block 102 is configured based on the type and design of the back-end device formed using method 100. In the depicted embodiment, the dopant placement profile includes a first type dopant region 202D1 and a second type dopant region 202D2 selectively formed in a first type dopant placement profile. In some embodiments, the first type dopant region 202D1 may include p-type dopant, while the second type dopant region 202D2 may include n-type dopant. In some alternative embodiments, the first type dopant region 202D1 may include n-type dopant, while the second type dopant region 202D2 may include p-type dopant. When the back-end device is a planar device, resistor, or capacitor, the dopant placement profile formed at block 102 may include a single region having the same conductivity type. When the back-end device is a bipolar junction transistor or diode, the dopant placement profile formed at block 102 may include two different conductivity types of dopant. The operation at block 102 will be described in more detail below using examples of dopant implantation profiles that include regions of different conductivity types.

[0109] First see Figure 2 , Figure 2 Substrate 202 is described. Substrate 202 may be a semiconductor substrate, such as a silicon (Si) substrate. Substrate 202 may also include other semiconductors, such as germanium (Ge), silicon carbide (SiC), silicon-germanium (SiGe), germanium-tin (GeSn), or diamond. In one embodiment, substrate 202 is a silicon (Si) substrate. Figure 2 In some embodiments shown, a deep-well ion implantation process 1000 is performed to create a first-type doped region 202D1 in a substrate 202. The deep-well ion implantation process 1000 is used to form the first-type doped region 202D1 at a first depth D1. The first-type doped region 202D1 is designed to reach a second depth D2. In some embodiments, the first depth D1 may be between about 50 nm and about 100 nm, while the second depth D2 may be between about 100 nm and about 300 nm. The first depth D1 represents the region in which method 100 forms the FEOL multi-gate device. In some instances, the deep-well ion implantation process 1000 includes ion energies between 50 keV and about 1000 keV and ion energies between about 1 x 10⁻⁶ keV. 11 atoms / cm 2 With approximately 1x10 13 atoms / cm 2The ion dosage is between [specific values]. In embodiments where substrate 202 is a 300 mm silicon wafer, substrate 202 may have a wafer thickness Tw between approximately 750 μm and approximately 800 μm. For ease of illustration, most of the wafer thickness TW is represented by dashed lines. As will be further described below, most of substrate 202 may be ground or polished away to expose the type-1 dopant region 202D1 before forming the back-side device above the ion implantation profile. The deep-well ion implantation process 1000 may implant n-type dopant (e.g., phosphorus (P) or arsenic (As)) or p-type dopant (e.g., boron (B)).

[0110] See now Figure 3 In embodiments where the rear-side device requires implanted regions of different conductivity types, a selective deep-well ion implantation process 2000 is performed. Unlike deep-well ion implantation process 1000, selective deep-well ion implantation process 2000 includes the use of an ion implantation mask 203, which may include a photoresist, silicon oxide, or a combination thereof. Furthermore, the ion energy of selective deep-well ion implantation process 2000 can be greater than that of deep-well ion implantation process 1000. In some instances, the ion energy of selective deep-well ion implantation process 2000 can be between approximately 80 keV and approximately 1200 keV. The larger ion energy of selective deep-well ion implantation process 2000 allows for the formation of a second type doped region 202D2 that is deeper than the first type doped region 202D1. Similar to the deep-well ion implantation process 1000, the selective deep-well ion implantation process 2000 can implant n-type dopants (e.g., phosphorus (P) or arsenic (As)) or p-type dopants (e.g., boron (B)), as long as the first type dopant region 202D1 and the second type dopant region 202D2 have different conductivity types. The first type dopant region 202D1, the second type dopant region 202D2, or other combinations of doped regions can be referred to as the dopant implantation profile. After the selective deep-well ion implantation process 2000, the ion implantation mask 203 is removed.

[0111] See Figure 4The n-well 202N and p-well 202P can be selectively formed near the front side 200F of the substrate 202 as anti-doped regions to reduce leakage. In some embodiments, the formation of the n-well 202N and p-well 202P can be omitted because most of the substrate 202 is ground away. Unlike the first type dopant region 202D1 and the second type dopant region 202D2, the n-well 202N and p-well 202P are formed using a low-energy ion implantation process, which achieves ion energies of less than 10 keV. In an exemplary process, a first masking layer is formed to expose the n-well region to be formed, and an n-type dopant is implanted into the n-well region to be formed. The first masking layer is removed, and a second masking layer is formed to cover the n-well 202N, while the p-well 202P is formed by low-energy ion implantation. Alternatively, the p-well region can be formed first. It should be noted that the concentration, pattern, and depth of the first type doped region 202D1 and the second type doped region 202D2 are configured and selected for the formation of the back-side device. The first type doped region 202D1 and the second type doped region 202D2 are not formed as leakage prevention measures for the multi-gate device formed in blocks 104 to 120. Similarly, the n-well 202N and p-well 202P are formed to meet the design requirements of the multi-gate device, rather than as leakage prevention measures for the back-side device.

[0112] See Figure 1 and Figure 5 Method 100 includes block 104, wherein a stack 204 of alternating semiconductor layers is formed over 202. In some embodiments, stack 204 includes a channel layer 208 of a first semiconductor composition interleaved with a sacrificial layer 206 of a second semiconductor composition. That is, the sacrificial layer 206 and the channel layer 208 are interleaved. The first and second semiconductor compositions may be different. In some embodiments, the sacrificial layer 206 comprises silicon germanium (SiGe) or germanium tin (GeSn), while the channel layer 208 comprises silicon (Si). It should be noted that, as Figure 5 As shown, four (4) sacrificial layers 206 and three (3) channel layers 208 are arranged alternately. This is for illustrative purposes only and is not intended to limit the scope specifically described in the utility model claims. It is understood that any number of epitaxial layers can be formed in the stack 204. The number of layers depends on the number of channel components required for the semiconductor device 200. In some embodiments, the number of channel layers 208 is between 2 and 10.

[0113] Molecular beam epitaxy (MBE), vapor phase deposition (VPE), and / or other suitable epitaxial growth processes can be used to deposit the sacrificial layer 206 and the channel layer 208 in the stack 204. As described above, in at least some instances, the sacrificial layer 206 comprises an epitaxially grown silicon-germanium (SiGe) layer, and the channel layer 208 comprises an epitaxially grown silicon (Si) layer. In some embodiments, the sacrificial layer 206 and the channel layer 208 are substantially dopant-free (i.e., having approximately 0 atoms / cm²). 3 To approximately 1x10 17 atoms / cm 3 (intrinsic dopant concentration), where, for example, no intentional doping is performed during the epitaxial growth process of stack 204.

[0114] See Figure 1 and Figure 6 Method 100 includes block 106, wherein a fin structure 212 is formed from stack 204 and substrate 202. To pattern the stack 204, a hard mask layer 210 (e.g., ...) can be deposited over the stack 204. Figure 5 (As shown) to form an etch mask. The hard mask layer 210 can be a single layer or multiple layers. For example, the hard mask layer 210 may include a pad oxide layer and a pad nitride layer disposed above the pad oxide layer. The fin structure 212 can be patterned from the stack 204 and the substrate 202 using lithography and etching processes. The lithography process may include photoresist coating (e.g., spin coating), soft baking, mask alignment, exposure, post-exposure baking, photoresist development, rinsing, drying (e.g., spin drying and / or hard baking), other suitable lithography techniques and / or combinations thereof. In some embodiments, the etching process may include dry etching (e.g., RIE etching), wet etching and / or other etching methods. Figure 6 As shown, the etching process at block 104 forms a trench extending vertically through a portion of the stack 204 and the substrate 202. The trench defines the fin structure 212. In some embodiments, dual patterning or multiple patterning processes may be used to define the fin structure, for example, the spacing between these fin structures may be smaller than that achievable using a single direct lithography process. For example, in one embodiment, a material layer is formed on the substrate and patterned using a lithography process. Spacers are formed next to the patterned material layer using a self-aligning process. The material layer is then removed, and the remaining spacers or mandrel can then be used to pattern the fin structure 212 by etching a portion of the stack 204 and the substrate 202. Figure 6 As shown, the fin-shaped structure 212, including the sacrificial layer 206 and the channel layer 208, extends vertically along the Z direction and longitudinally along the X direction. Figure 6As shown, the fin structure 212 includes a base fin structure 212B patterned from the substrate 202. A patterned stack 204 including a sacrificial layer 206 and a channel layer 208 is disposed directly above the base fin structure 212B.

[0115] At block 106, an isolation feature 214 is formed near the fin-shaped structure 212. Figure 6 In some embodiments shown, isolation features 214 are disposed on the sidewalls of the substrate fin structure 212B. In some embodiments, isolation features 214 may be formed in trenches to isolate the fin structure 212 from adjacent fin structures. Isolation feature 214 may also be referred to as shallow trench isolation (STI) feature 214. For example, in some embodiments, a dielectric layer is first deposited over the substrate 202 to fill the trench with the dielectric layer. In some embodiments, the dielectric layer may include silicon oxide, silicon oxynitride, fluorosilicate glass (FSG), low-k dielectric layers and combinations thereof, and / or other suitable materials. In various instances, the dielectric layer may be deposited using CVD processes, subatmospheric CVD (SACVD) processes, flowable CVD processes, spin coating processes, and / or other suitable processes. The deposited dielectric material is then thinned and planarized, for example, by a chemical mechanical polishing (CMP) process. By using dry etching, wet etching, and / or combinations thereof, the planarized dielectric layer is further recessed or pulled back to form... Figure 6 The STI feature 214 is shown. After the indentation, the fin structure 212 rises above the STI feature 214, while the base fin structure 212B is embedded or buried in the isolation feature 214.

[0116] See Figure 1 and Figures 7 to 9 Method 100 includes block 108, wherein a dummy gate stack 220 is formed over channel region 212C of fin structure 212. In some embodiments, a gate replacement process (or gate final process) is employed, wherein the dummy gate stack 220 serves as a placeholder for various processes and is removed and replaced by a functional gate structure. Other processes and configurations are also possible. Figure 8 In some embodiments shown, a dummy gate stack 220 is formed above a fin structure 212, and the fin structure 212 can be divided into a channel region 212C located below the dummy gate stack 220 and a source / drain region 212SD not located below the dummy gate stack 220. The channel region 212C is adjacent to the source / drain region 212SD. Figure 8 As shown, the channel region 212C is disposed between the two source / drain regions 212SD along the X direction.

[0117] The formation of the dummy gate stack 220 may include depositing layers in the dummy gate stack 220 and patterning these layers. See also Figure 7 A dummy dielectric layer 216, a dummy electrode layer 218, and a gate top hard mask layer 222 can be deposited over the WIP structure 200. In some embodiments, the dummy dielectric layer 216 can be formed on the fin structure 212 using chemical vapor deposition (CVD), ALD, oxygen plasma oxidation, or other suitable processes. In some instances, the dummy dielectric layer 216 may include silicon oxide. Subsequently, a dummy electrode layer 218 can be deposited over the dummy dielectric layer 216 using CVD, ALD, or other suitable processes. In some instances, the dummy electrode layer 218 may include polysilicon. For patterning purposes, a gate top hard mask layer 222 can be deposited on the dummy electrode layer 218 using CVD, ALD, or other suitable processes. The gate top hard mask layer 222, the dummy electrode layer 218, and the dummy dielectric layer 216 can then be patterned to form a dummy gate stack 220, such as... Figure 8 As shown. For example, the patterning process may include lithography (e.g., photolithography or electron beam lithography) and etching. The lithography process may further include photoresist coating (e.g., spin coating), soft baking, mask alignment, exposure, post-exposure baking, photoresist development, rinsing, drying (e.g., spin drying and / or hard baking), other suitable lithography techniques and / or combinations thereof. The lithography process forms a patterned photoresist layer. Subsequently, in the etching process, the patterned photoresist layer is used as an etching mask to pattern the gate top hard mask layer 222, the dummy electrode layer 218, and the dummy dielectric layer 216. In some embodiments, the etching process may include dry etching (e.g., RIE etching), wet etching, and / or other etching methods. In some embodiments, the gate top hard mask layer 222 may include a silicon oxide layer 223 and a silicon nitride layer 224 located above the silicon oxide layer 223. Figure 8 As shown, the patterned dummy gate stack 220 is disposed only above the channel region 212C and not above the source / drain region 212SD.

[0118] See Figure 1 and Figure 9At block 108, a gate spacer layer 226 is deposited over the WIP structure 200 (including over the dummy gate stack 220). In some embodiments, the gate spacer layer 226 is conformally deposited over the WIP structure 200 (including over the top surface and sidewalls of the dummy gate stack 220). The term “conformal” may be used herein to conveniently describe a layer having a substantially uniform thickness over various regions. The gate spacer layer 226 may be a single layer or multiple layers. At least one layer of the gate spacer layer 226 may include silicon carbonitride, silicon carbide, silicon carbide, or silicon nitride. The gate spacer layer 226 may be deposited over the dummy gate stack 220 using processes such as CVD, subatmospheric CVD (SACVD), ALD, or other suitable processes.

[0119] See Figure 1 and Figure 10 Method 100 includes block 110, wherein the source / drain regions 212SD of the fin structure 212 are anisotropically recessed to form source / drain trenches 228. Anisotropic etching may include dry etching or a suitable etching process that etches the source / drain regions 212SD and a portion of the substrate 202 located beneath the source / drain regions 212SD. The resulting source / drain trenches 228 extend vertically through the depth of the stack 204 and partially into the substrate 202. An exemplary dry etching process for block 110 may be implemented using oxygen-containing gases, fluorine-containing gases (e.g., CF4, SF6, CH2F2, CHF3, C4F8 and / or C2F6), chlorine-containing gases (e.g., Cl2, CHCl3, CCl4 and / or BCl3), bromine-containing gases (e.g., HBr and / or CHBr3), iodine-containing gases, other suitable gases and / or plasmas and / or combinations thereof. Figure 10 As shown, the source / drain region 212SD of the fin structure 212 is recessed to expose the sidewalls of the sacrificial layer 206 and the channel layer 208. Since the source / drain trench 228 extends below the stack 204 into the substrate 202, the source / drain trench 228 includes a bottom surface and a lower sidewall defined in the substrate 202.

[0120] See Figure 1 and Figure 10 Method 100 includes block 112, in which internal spacer features 234 are formed. Although not explicitly stated, operations at block 112 may include selective and partial removal of the sacrificial layer 206 to form internal spacer recesses (in... Figure 10 The diagram shows the internal spacer feature 234 being filled with internal spacer material, deposited on top of the WIP structure 200, and etched back to form the internal spacer feature 234. Figure 10 (As shown in the image). See also Figure 10The sacrificial layer 206 exposed in the source / drain trench 228 is selectively and partially recessed to form internal spacer recesses (in Figure 10 The image shows the area filled with internal spacer feature 234, while the gate spacer layer 226, the exposed portion of the substrate 202, and the channel layer 208 are substantially unetched. In embodiments where the channel layer 208 is primarily composed of silicon (Si) and the sacrificial layer 206 is primarily composed of silicon-germanium (SiGe), selective wet etching or selective dry etching processes can be used to selectively recess the sacrificial layer 206. An exemplary selective dry etching process may include the use of one or more fluorine-based etchants, such as fluorine gas or hydrofluorocarbons. An exemplary selective wet etching process may include APM etching (e.g., an ammonium hydroxide-hydrogen peroxide-water mixture).

[0121] After the internal spacer recesses are formed, internal spacer material is deposited over the WIP structure 200 (including over the internal spacer recesses). The internal spacer material may include metal oxides, silicon oxides, silicon carbonitride, silicon nitride, silicon oxynitride, carbon-rich silicon carbonitride, or low-k dielectric materials. Metal oxides may include aluminum oxide, zirconium oxide, tantalum oxide, yttrium oxide, titanium oxide, lanthanum oxide, or other suitable metal oxides. Although not explicitly stated, the internal spacer material may be a single layer or multiple layers. In some embodiments, CVD, PECVD, SACVD, ALD, or other suitable methods may be used to deposit the internal spacer material. The internal spacer material is deposited in the internal spacer recesses and on the sidewalls of the exposed channel layer 208 in the source / drain trench 228. See also Figure 10 Then, the deposited internal spacer material is etched to remove it from the sidewalls of the channel layer 208, thereby forming internal spacer features 234 in the internal spacer recesses. At block 112, internal spacer material can also be removed from the top surface and / or sidewalls of the gate top hard mask layer 222 and the gate spacer layer 226. For example... Figure 10 As shown, each internal spacer feature 234 is in direct contact with the recessed sacrificial layer 206 and is disposed vertically (along the Z direction) between two adjacent channel layers 208.

[0122] Although not explicitly stated, method 100 may include a cleaning process to clean the surface of the WIP structure 200 prior to the formation of any epitaxial layer. The cleaning process may include dry cleaning, wet cleaning, or a combination thereof. In some instances, wet cleaning may include removing oxides using Standard Cleaner 1 (RCA SC-1, a mixture of deionized (DI) water, ammonium hydroxide, and hydrogen peroxide), Standard Cleaner 2 (RCA SC-2, a mixture of DI water, hydrochloric acid, and hydrogen peroxide), SPM (a mixture of sulfuric acid peroxide), and / or hydrofluoric acid. Dry cleaning processes may include helium (He) and hydrogen (H2) treatment. Hydrogen treatment can convert silicon on the surface into silane (SiH4), which can be pumped out for removal.

[0123] See Figure 1 and Figure 11 Method 100 includes block 114, wherein a source / drain feature 240 is formed over a source / drain region 212SD. The source / drain feature 240 may be n-type or p-type. When the source / drain feature 240 is n-type, it may include silicon (Si) and an n-type dopant such as phosphorus (P), arsenic (As), antimony (Sb), or combinations thereof. When the source / drain feature 240 is p-type, it may include silicon germanium (SiGe) and a p-type dopant such as boron (B) or boron difluoride (BF2). In some embodiments, the source / drain feature 240 may include multiple epitaxial layers with different dopant concentrations. In some embodiments, the source / drain feature 240 may be deposited using molecular beam epitaxy (MBE), vapor phase deposition (VPE), and / or other suitable epitaxial growth processes.

[0124] See Figure 1 and Figure 12 Method 100 includes block 116, in which a contact etchstop layer (CESL) 242 and an interlayer dielectric (ILD) layer 244 are deposited. See also Figure 11A CESL 242 is deposited over the WIP structure 200, including over the source / drain features 240. The CESL 242 may comprise silicon nitride or aluminum nitride. In some implementations, the CESL 242 may be deposited using CVD or ALD. An ILD layer 244 is then deposited over the CESL 242. In some embodiments, the ILD layer 244 comprises materials such as tetraethoxysilane (TEOS) oxide, undoped silicon glass, or doped silicon oxide (such as borosilicate glass (BPSG), fluorosilicate glass (FSG), phosphosilicate glass (PSG), borosilicate glass (BSG), and / or other suitable dielectric materials). The ILD layer 244 may be deposited using CVD, FCVD, spin coating, or suitable deposition techniques. After depositing the ILD layer 244, the WIP structure 200 may be planarized using a planarization process to expose the dummy gate stack 220.

[0125] To protect the ILD layer 244 from etching during the channel release process, a capping layer 245 is formed over the ILD layer 244. In the exemplary process, the ILD layer 244 is anisotropically and selectively recessed to form top recesses (e.g., Figure 13 As shown, the ILD layer 244 is filled with a capping layer 245. In some embodiments, anisotropic etching of the ILD layer 244 may include a plasma using a fluorine-containing gas (e.g., CF4, SF6, CH2F2, CHF3, C2F6, and / or C3F6). In some embodiments, the capping layer 245 may include a dielectric material that allows selective etching of the dummy electrode layer 218, the dummy dielectric layer 216, and the sacrificial layer 206. In some embodiments, the capping layer 245 may include silicon nitride. The capping layer 245 protects the ILD layer 244 from damage during the removal of the sacrificial layer 206. A planarization process is performed to remove excess capping layer 245 and expose the dummy gate stack 220. After planarization, the top surfaces of the capping layer 245, CESL 242, gate spacer layer 226, and dummy gate stack 220 are coplanar.

[0126] See Figure 1 and Figure 13 Method 100 includes block 118, wherein the channel layers 208 are released as channel members 2080. Operations at block 124 may include removing the dummy gate stack 220 and selectively removing the sacrificial layer 206 to release the channel layers 208 (e.g., Figure 12 (As shown). See also Figure 3The removal of the dummy gate stack 220 may include one or more etching processes that are selective to the material of the dummy gate stack 220. For example, the removal of the dummy gate stack 220 may be performed using selective wet etching, selective dry etching, or a combination thereof that are selective to the dummy gate stack 220. After the dummy gate stack 220 is removed, the sidewalls of the channel layer 208 and the sacrificial layer 206 in the channel region 212C are exposed. The sacrificial layer 206 between the channel layers 208 in the channel region 212C is selectively removed. The selective removal of the sacrificial layer 206 releases the channel layer 208 to form Figure 13 The channel member 2080 is shown. A selectively removed sacrificial layer 206 forms a gate trench 246, which includes space between adjacent channel members 2080. The selectively removed sacrificial layer 206 can be achieved by selective dry etching, selective wet etching, or other selective etching processes. An exemplary selective dry etching process may include the use of one or more fluorine-based etchants, such as fluorine gas or hydrofluorocarbons. An exemplary selective wet etching process may include APM etching (e.g., an ammonium hydroxide-hydrogen peroxide-water mixture).

[0127] See Figure 1 and Figure 13 Method 100 includes block 120, in which a gate structure 250 is formed to cover each released channel member 2080. After the channel member 2080 is released, the gate structure 250 is formed to cover each channel member 2080. Although not explicitly stated, the gate structure 250 includes an interface layer that interfaces the channel member 2080 in the channel region 212C with the substrate 202, a gate dielectric layer above the interface layer, and a gate electrode layer above the gate dielectric layer. The interface layer may include a dielectric material such as silicon oxide, hafnium silicate, or silicon oxynitride. The interface layer may be formed by chemical oxidation or thermal oxidation. The gate dielectric layer may include a high-k dielectric material such as hafnium oxide. Alternatively, the gate dielectric layer may comprise other high-k dielectric materials, such as titanium oxide (TiO2), hafnium zirconium oxide (HfZrO), tantalum oxide (Ta2O5), hafnium silicon oxide (HfSiO4), zirconium oxide (ZrO2), zirconium silicon oxide (ZrSiO2), lanthanum oxide (La2O3), aluminum oxide (Al2O3), zirconium oxide (ZrO), yttrium oxide (Y2O3), hafnium lanthanum oxide (HfLaO), lanthanum silicon oxide (LaSiO), aluminum silicon oxide (AlSiO), hafnium tantalum oxide (HfTaO), hafnium titanium oxide (HfTiO), or combinations thereof, or other suitable materials. The gate dielectric layer may be formed using ALD, physical vapor deposition (PVD), CVD, oxidation, and / or other suitable methods.

[0128] The gate electrode layer of gate structure 250 may comprise a single-layer or multi-layer structure, such as a metal layer (work function metal layer) having a selected work function to enhance device performance, a substrate, a wetting layer, an adhesive layer, a metal alloy, or a combination of metal silicides. For example, the gate electrode layer may comprise titanium nitride (TiN), titanium aluminum nitride (TiAl), titanium aluminum nitride (TiAlN), tantalum nitride (TaN), tantalum aluminum nitride (TaAl), tantalum aluminum nitride (TaAlN), tantalum aluminum carbide (TaAlC), tantalum carbonitride (TaCN), aluminum (Al), tungsten (W), nickel (Ni), titanium (Ti), ruthenium (Ru), cobalt (Co), platinum (Pt), tantalum carbide (TaC), tantalum silicon nitride (TaSiN), copper (Cu), other refractory metals, or other suitable metallic materials or combinations thereof. In various embodiments, the gate electrode layer may be formed by ALD, PVD, CVD, electron beam evaporation, or other suitable processes. In various embodiments, a CMP process may be performed to remove excess metal, thereby providing a generally flat top surface of the gate structure. The gate structure includes a portion between channel members 2080 in the channel region 212C.

[0129] See Figure 1 and Figure 14 Method 100 includes block 122 in which a front-side interconnect structure 270 is formed. The front-side interconnect structure 270 includes vias and contact features providing vertical connectivity and conductive lines providing horizontal connectivity. In some embodiments, the front-side interconnect structure 270 may include eight (8) to twenty (20) metal layers (or metallization layers) for signal routing. Each metal layer in the front-side interconnect structure 270 may include an etch stop layer (ESL) and an intermetallic dielectric (IMD) layer disposed on the ESL. The ESL may share the same composition and may include silicon nitride or silicon oxynitride. The IMD layer may have the same composition and may include silicon oxide, tetraethoxysilane (TEOS) oxide, undoped silicon glass (USG), or doped silicon oxide, such as borosilicate glass (BPSG), fluorosilicate glass (FSG), phosphosilicate glass (PSG), borosilicate glass (BSG), low-k dielectric materials, other suitable dielectric materials, or combinations thereof. Exemplary low-k dielectric materials include carbon-doped silicon dioxide, degel, aerogel, amorphous fluorinated carbon, phenylcyclobutene (BCB), or polyimide. Metal lines and vias in the metal layer may include titanium (Ti), ruthenium (Ru), nickel (Ni), cobalt (Co), copper (Cu), molybdenum (Mo), tungsten (W), aluminum (Al), and / or other suitable materials.

[0130] See Figure 1 and Figures 15 to 20Method 100 includes block 124, in which rear-side devices 200B1–200B5 are formed above the dopant implantation profile. Forming the rear-side devices requires flipping the WIP structure 200 vertically. To provide mechanical strength when the substrate 202 is ground away, a carrier substrate 280 is bonded to the top surface of the front-side interconnect structure 270. In some embodiments, the carrier substrate 280 may comprise silicon, quartz, or glass. In one embodiment, the carrier substrate 280 comprises silicon. The carrier substrate 280 may be bonded to the front-side interconnect structure 270 via a bonding film or a pair of bonding layers. For ease of illustration, Figures 15 to 20 The bonding structure between the carrier substrate 280 and the front interconnect structure 270 is omitted, and the thicknesses of the front interconnect structure 270 and the carrier substrate 280 are not drawn to scale. After the WIP structure 200 is flipped, as shown... Figure 15 As shown, the substrate 202 undergoes grinding and polishing processes until the block 102 formed by the ion implantation contour is exposed. In some embodiments, after the ion implantation contour is exposed by the grinding process, the substrate 202 has a first thickness T1 that may be between about 100 nm and about 300 nm.

[0131] This disclosure envisions the formation of different types of rear-side devices, some of which are such as Figures 16 to 20 As shown. Figure 16 The formation of the first rear-side device 200B1 is explained, and the first rear-side device 200B1 may be a diode. Figure 17 The formation of the second rear-side device 200B2 is explained. The second rear-side device 200B2 may be a bipolar junction transistor (BJT). Figure 18 The formation of the third rear-side device 200B3 is explained, and the third rear-side device 200B3 may be a resistor. Figure 19 The formation of the fourth rear-side device 200B4 is explained, which is a planar transistor. Figure 20 The formation of the fifth rear-side device 200B5 is explained. The fifth rear-side device 200B5 is an embedded dynamic random access memory (eDRAM) device.

[0132] First see Figure 16 , Figure 16A first backside device 200B1 is formed above the ion implantation profile. To form the first backside device 200B1, a first backside isolation feature 302 is formed along the vertical interface between the first type dopant region 202D1 and the second type dopant region 202D2. In an exemplary process, a trench is formed along the vertical interface between the first type dopant region 202D1 and the second type dopant region 202D2. A dielectric material is deposited over the backside (including over the trench), and then the dielectric material is planarized until the first type dopant region 202D1 and the second type dopant region 202D2 are exposed again. In some embodiments, the dielectric material may include tetraethoxysilane (TEOS) oxide, undoped silicon glass, or doped silicon oxide, such as borosilicate glass (BPSG), fluorosilicate glass (FSG), phosphosilicate glass (PSG), borosilicate glass (BSG), and / or other suitable dielectric materials. The first rearward isolation feature 302 can also be called the first rearward shallow trench isolation (STI) 302. For example... Figure 16 As shown, the depth of the first rear isolation feature 302 is selected such that the np or pn junction between the first type doped region 202D1 and the second type doped region 202D2 is substantially along the XY plane, which is a plane parallel to the rear surface of the substrate 202.

[0133] A back dielectric layer 306 is deposited over the back isolation feature 302, the first type dopant region 202D1, and the second type dopant region 202D2. In some instances, the composition of the back dielectric layer 306 may be similar to that of the ILD layer 244. After forming the back dielectric layer 306, two contact openings are formed through the back dielectric layer 306, one exposing the first type dopant region 202D1 and the other exposing the second type dopant region 202D2. After forming the contact openings, a silicide layer 304 is formed over the exposed region of the first type dopant region 202D1, while the other contact opening exposes the second type dopant region 202D2. In some embodiments, the silicide layer 304 may comprise nickel silicide (NiSi), cobalt silicide (CoSi), or titanium silicide (TiSi). In one embodiment, the silicide layer 304 comprises nickel silicide. The first contact feature 308 and the second contact feature 310 are then formed by depositing a metal filler layer over the two contact openings and removing excess material by planarization. In some instances, the metal filler layer may include tungsten (W), ruthenium (Ru), cobalt (Co), or copper (Cu). In one embodiment, the metal filler layer may be cobalt (Co). Figure 16In some embodiments shown, the first contact feature 308 is electrically coupled to the second type dopant region 202D2, and the second contact feature 310 is electrically coupled to the first type dopant region 202D1 through the silicide layer 304.

[0134] Then see Figure 17 , Figure 17 The second rear-side device 200B2 is described as being formed above the ion implantation profile. In the illustrated embodiment, the second rear-side device 200B2 is a bipolar junction transistor comprising two pn (or np) junctions, instead of just one in the first rear-side device 200B1. Figure 17 As shown, in addition to the first rear-side isolation feature 302, a second rear-side isolation feature 303 is also formed along the vertical interface between the first type doped region 202D1 and the second type doped region 202D2. The first rear-side isolation feature 302 and the second rear-side isolation feature 303 provide isolation between the three terminals of the second rear-side device 200B2. In addition to the first contact feature 308 and the second contact feature 310 described above for the first rear-side device 200B1, the second rear-side device 200B2 also includes a third contact feature 312, which is coupled to another portion of the second type doped region 202D2 through a silicide layer 304. In some instances, the second contact feature 310 can be used as the base of a bipolar junction transistor, while the first contact feature 308 and the third contact feature 312 can be used as the collector and emitter. The second rear-side isolation feature 303 and the third contact feature 312 can be formed using a process similar to that used for the first rear-side isolation feature 302 and the first contact feature 308. For the sake of brevity, detailed descriptions are omitted.

[0135] See now Figure 18 , Figure 18 This describes a third rear-side device 200B3 formed only above the first-type doped region 202D1. A longer block isolation feature 305 is formed in the first-type doped region 202D1 to increase the conduction path between the two resistive electrodes, rather than... Figure 16 and Figure 17 The first isolation feature 302 and the second rear isolation feature 303 are shown in the diagram. In the illustrated embodiment, the fourth contact feature 316 and the fifth contact feature 318 are formed via the rear dielectric layer 306. The fourth contact feature 316 and the fifth contact feature 318 are electrically coupled to two regions of the first type doped region 202D1 through the silicide layer 304. Figure 18As shown, the two regions are separated along the X direction by a block isolation feature 305, and the length of the block isolation feature 305 defines the length of the conduction path between the two regions, which are respectively coupled to the fourth contact feature 316 and the fifth contact feature 318. Therefore, if there is sufficient space, the length of the block isolation feature 305 determines the resistance of the third rear-side device 200B3, and it functions as a resistor.

[0136] See Figure 19 , Figure 19 This describes a fourth backside device 200B4 formed only above the first type dopant region 202D1. In some embodiments, the first type dopant region 202D1 includes a p-type dopant. In an exemplary process for forming the fourth backside device 200B4, an interface layer 328, a gate dielectric layer 330, and a polysilicon electrode layer 332 are deposited above the first type dopant region 202D1. In some instances, the interface layer 328 includes silicon oxide or silicon oxynitride; the gate dielectric layer 330 is formed of a high-k dielectric material (such as hafnium oxide); and the polysilicon gate 332 includes polysilicon and an n-type dopant (such as phosphorus (P)). In some alternative embodiments, the polysilicon gate 332 may be replaced by a metal gate formed of titanium nitride. The interface layer 328, the gate dielectric layer 330, and the polysilicon electrode layer 332 are then patterned to form a gate structure. A gate spacer layer 334 is conformally deposited above the gate structure and the first type dopant region 202D1. Then, the gate spacer layer 334 is anisotropically etched to form Figure 19The gate spacer shown is lining the sidewalls of the gate structure. The first source / drain region 320 and the second source / drain feature 322 can be formed by ion implantation or epitaxial deposition. In the illustrated embodiment, the first source / drain region 320 and the second source / drain feature 322 are epitaxially deposited and include silicon (Si) and an n-type dopant, such as phosphorus (P). After forming a back-side dielectric layer 306 over the first source / drain feature 320 and the second source / drain feature 322, a sixth contact feature 324 and a seventh contact feature 326 are formed through the back-side dielectric layer 306 to couple to the first source / drain region 320 and the second source / drain region 322 via silicide features. A back-side isolation layer 340 is formed over the sixth contact feature 324 and the seventh contact feature 326. The composition of the back-side isolation layer 340 may be similar to that of the back-side dielectric layer 306. Then, a rear gate contact 338 is formed through the rear isolation layer 340 to contact the polysilicon electrode layer 332 via the silicide feature 336. When the sixth contact feature 324 and the seventh contact feature 326 are pulled to the same potential, the fourth rear device 200B4 functions as a capacitor, wherein the interface layer 328 and the gate dielectric layer 330 serve as capacitor insulators. The rear gate contact 338 functions as an electrode, while the sixth contact feature 324 and the seventh contact feature 326 together serve as another electrode. When the sixth contact feature 324 and the seventh contact feature 326 are not coupled together, the fourth rear device 200B4 functions as a planar device. In some instances, the planar device implemented using the fourth rear device 200B4 can be used as a rear header device or a rear header switch to activate different blocks of the FEOL transistor.

[0137] See now Figure 20 , Figure 20 This describes the fifth rear-side device 200B5 formed only above the first type of dopant region 202D1. Figure 20 The fifth rear-side device 200B5 shown can be a low-leakage transistor in a 1-transistor-1-capacitor (1T1C) embedded dynamic random access memory (eDRAM) cell. In the exemplary process, isolation trenches and gate trenches are formed via a first-type doped region 202D1. The isolation trenches are formed entirely via a first-type doped implantation profile to ensure that the resulting isolation structure satisfactorily isolates the individual low-leakage transistors. After forming the isolation trenches and gate trenches, dielectric material is deposited into the isolation trenches to form... Figure 20The isolation feature 342 is shown. In some embodiments, the dielectric material of the isolation feature 342 may include silicon oxide or a low-k dielectric material. A gate dielectric layer 344 is deposited over the gate trench. In some embodiments, the gate dielectric layer 344 may include hafnium oxide. A gate electrode 346 is then deposited over the gate dielectric layer 344. In some embodiments, the gate electrode 346 may include tungsten (W), ruthenium (Ru), cobalt (Co), or titanium nitride (TiN). The gate electrode 346 and the gate dielectric layer 344 constitute a long gate structure 345, which is coupled to the length of the first type doped region 202D1. One of the two source / drain nodes 348 defined by the long gate structure 345 is coupled to a capacitor for use as a storage node. It should be noted that the isolation feature 342 and the long gate structure 345 may extend completely through a second thickness T2 of the first type doped region 202D1. In some instances, the second thickness T2 may be between about 50 nm and about 200 nm. Although not explicitly shown in the diagram, the capacitors of a 1T1CeDRAM cell may include deep trench capacitors.

[0138] Now turn attention to Figure 21 Method 400.

[0139] See Figure 21 and Figures 22 to 24 Method 400 includes block 402, in which a dopant placement profile is formed in substrate 202. The operation at block 402 is substantially similar to the operation at block 102, and will not be repeated here for the sake of simplicity.

[0140] See Figure 21 and Figure 25 Method 400 includes block 404, in which a stack 204 of alternating semiconductor layers is formed over the WIP structure 200. The operation at block 404 is substantially similar to the operation at block 104 described above. Therefore, for the sake of brevity, a detailed description of the operation at block 404 is omitted.

[0141] See Figure 21 and Figure 26 Method 400 includes block 406, in which a fin structure 212 is formed by stack 204 and substrate 202. The operation at block 406 is substantially similar to the operation at block 106 described above. Therefore, for the sake of brevity, a detailed description of the operation at block 406 is omitted.

[0142] See Figure 21 and Figures 27 to 29 Method 400 includes block 408, wherein a dummy gate stack 220 is formed above the channel region 212C of the fin structure 212. The operation at block 408 is substantially similar to the operation at block 108 described above. Therefore, for the sake of brevity, a detailed description of the operation at block 408 is omitted.

[0143] See Figure 21 and Figure 30 Method 400 includes block 410, wherein the source / drain region 212SD of the fin structure 212 is anisotropically recessed to form a source / drain trench 228. The operation at block 410 is substantially similar to the operation at block 110 described above. Therefore, for the sake of brevity, a detailed description of the operation at block 410 is omitted.

[0144] See Figure 21 and Figure 31 Method 400 includes block 412, wherein the channel layers 208 in the channel region are released as channel members 2080. After forming the source / drain trench 228, sacrificial layers 206 interleaved with the channel layers 208 in the channel region 212C are selectively removed. The selective removal of sacrificial layers 206 releases the channel layers 208 (e.g., Figure 30 (as shown) to form as Figure 31 The channel member 2080 is shown. The sacrificial layer 206 is selectively removed to form spaces between and around adjacent channel members 2080. The selective removal of the sacrificial layer 206 can be achieved by selective dry etching, selective wet etching, or other selective etching processes. An exemplary selective dry etching process may include the use of one or more fluorine-based etchants, such as fluorine gas or hydrofluorocarbons. An exemplary selective wet etching process may include APM etching (e.g., an ammonium hydroxide-hydrogen peroxide-water mixture).

[0145] See Figure 21 and Figure 32 Method 400 includes block 414, in which a dummy layer 230 is deposited around channel member 2080 and over source / drain trench 228. The dummy layer 230 may include silicon oxide and may be deposited using plasma-enhanced chemical vapor deposition (PECVD) or ALD. Figure 32 As shown, the dummy layer 230 fills the space between the channel members 2080 and covers the end sidewalls of the channel members 2080. Furthermore, the dummy layer 230 is in direct contact with the sidewalls of the gate spacer layer 226 and the top surface of the substrate 202. Depending on the design, the channel members 2080 may be in the form of nanowires, nanosheets, or other nanostructures.

[0146] See Figure 21 , Figure 33 and Figure 34 Method 400 includes block 416, wherein internal spacer features 234 are formed. See also Figure 33The dummy layer 230 is selectively and partially recessed to form internal spacer recesses 232, while the gate spacer layer 226, the dummy gate stack 220, the exposed portions of the substrate 202, and the channel layer 208 are substantially unetched. In embodiments where the channel layer 208 is substantially composed of silicon (Si) and the dummy layer 230 is formed of silicon oxide, the selective recessing of the dummy layer 230 can be performed using a selective wet etching process or a selective dry etching process. An exemplary selective dry etching process may include the use of carbon tetrafluoride (CF4), nitrogen trifluoride (NF3), hydrogen (H2), or mixtures thereof. An exemplary selective wet etching process may include the use of hydrofluoric acid, ammonium fluoride, or mixtures thereof.

[0147] To form internal spacer features, an internal spacer layer is deposited over the WIP structure 200 (including the source / drain trench 228 and the internal spacer recess 232). In some embodiments, the internal spacer layer may include silicon carbonitride (SiCN), silicon oxycarbonitride (SiOCN), silicon nitride (SiN), silicon oxycarbonitride (SiOC), or silicon oxynitride (SiON). In some embodiments, the internal spacer layer may be deposited using CVD or ALD. The deposited internal spacer layer is then etched back to form internal spacer features 234 in the internal spacer recess 232. In some embodiments, etching may include using a dry etching process, such as reactive ion etching (RIE) using plasma. Exemplary dry etching processes may include using boron trichloride (BCl3), chlorine (Cl2), hydrogen chloride (HCl), methane (CH4), nitrogen trifluoride (NF3), carbon tetrafluoride (CF4), sulfur hexafluoride (SF6), nitrogen (N2), or combinations thereof.

[0148] Although not explicitly stated, method 300 may include a cleaning process to clean the surfaces of the WIP structure 200, particularly the channels 2080 and the substrate 202, prior to the formation of any epitaxial layer. The cleaning process may include dry cleaning, wet cleaning, or a combination thereof. In some instances, wet cleaning may include removing oxides using Standard Cleaner 1 (RCA SC-1, a mixture of deionized (DI) water, ammonium hydroxide, and hydrogen peroxide), Standard Cleaner 2 (RCA SC-2, a mixture of DI water, hydrochloric acid, and hydrogen peroxide), SPM (a mixture of sulfuric acid peroxide), and / or hydrofluoric acid. Dry cleaning processes may include helium (He) and hydrogen (H2) treatment. Hydrogen treatment can convert silicon on the surface into silane (SiH4), which can be pumped out for removal.

[0149] See Figure 21 and Figure 35Method 400 includes block 418, wherein a source / drain feature 240 is formed above the source / drain region 212SD. Although not explicitly shown in the figure, the source / drain feature 240 may include a bottom epitaxial feature and a main epitaxial feature located above the bottom epitaxial feature. The source / drain feature 240 may be n-type or p-type. When the source / drain feature 240 is n-type, the bottom epitaxial feature may include undoped silicon (Si) or undoped silicon germanium (SiGe), while the main epitaxial feature may include silicon (Si) and an n-type dopant, such as phosphorus (P), arsenic (As), antimony (Sb), or combinations thereof. When the source / drain feature 240 is p-type, the bottom epitaxial feature may include undoped silicon (Si) or undoped silicon germanium (SiGe), while the main epitaxial feature may include silicon germanium (SiGe) and a p-type dopant, such as boron (B), boron difluoride (BF2), or combinations thereof. As used herein, undoped semiconductor material is considered undoped when it is not intentionally doped. In some alternative embodiments, the bottom epitaxial feature may include an anti-doperb to reduce leakage into the body substrate 202. For example, the bottom epitaxial feature in the n-type source / drain feature 240 may include a p-type dopant, such as boron (B). As another example, the bottom epitaxial feature in the p-type source / drain feature 240 may include an n-type dopant, such as phosphorus (P), arsenic (As), or antimony (Sb). The source / drain structure 240 may be formed using vapor-phase epitaxy (VPE), ultra-high vacuum CVD (UHV-CVD), or molecular beam epitaxy (MBE). Doping of the source / drain structure 240 may be achieved using in-situ doping.

[0150] See Figure 21 and Figure 36Method 400 includes block 420, in which a contact etchstop layer (CESL) 242 and an interlayer dielectric (ILD) layer 244 are deposited. At block 420, CESL 242 is deposited over WIP structure 200, including over source / drain features 240. CESL 242 may comprise silicon nitride or aluminum nitride. In some embodiments, CESL 242 may be deposited using CVD or ALD. ILD layer 244 is then deposited over CESL 242. In some embodiments, ILD layer 244 comprises materials such as tetraethoxysilane (TEOS) oxide, undoped silicon glass, or doped silicon oxide (e.g., borosilicate glass (BPSG), fluorosilicate glass (FSG), phosphosilicate glass (PSG), borosilicate glass (BSG), and / or other suitable dielectric materials). ILD layer 244 may be deposited using CVD, FCVD, spin coating, or suitable deposition techniques. After depositing the ILD layer 244, the WIP structure 200 can be planarized using a planarization process to expose the dummy gate stack 220. After the planarization process, the top surfaces of the dummy gate stack 220, CESL 242, ILD layer 244, and gate spacer layer 226 are exposed.

[0151] See Figure 21 and Figure 37 Method 400 includes block 422, wherein the dummy gate stack 220 and the dummy layer 230 are replaced with gate structure 250. To protect the ILD layer 244 from damage during the removal of the dummy layer 230, the ILD layer 244 is anisotropically and selectively recessed to form a top recess (in Figure 37 (As shown in the diagram, filled with capping layer 245). In some embodiments, anisotropic etching of ILD layer 244 may include plasma using fluorine-containing gases (e.g., CF4, SF6, CH2F2, CHF3, C2F6, and / or C3F6). Dielectric material is deposited over the top recess and planarized to form capping layer 245. In some embodiments, capping layer 245 may include silicon nitride. Due to the planarization process, the top surfaces of capping layer 245, CESL 242, gate spacer layer 226, and dummy gate stack 220 are coplanar.

[0152] After the capping layer 245 is formed, the dummy gate stack 220 is removed. Removing the dummy gate stack 220 may include one or more etching processes selectively targeting the material of the dummy gate stack 220. For example, selective wet etching, selective dry etching, or a combination thereof selectively targeting the dummy gate stack 220 may be used to remove the dummy gate stack 220. After removing the dummy gate stack 220, the channel member 2080 and the dummy layer 230 in the channel region 212C are exposed. After removing the dummy gate stack 220, a separate etching process may be performed to selectively remove the dummy layer 230 in the channel region 212C. For example, a selective wet etching process or a selective dry etching process may be performed to remove the dummy layer 230. An exemplary selective wet etching process may include using diluted hydrofluoric acid (DHF) or a mixture of hydrofluoric acid (HF) and ammonium fluoride (NH4F). An exemplary selective dry etching process may include the use of anhydrous hydrogen fluoride (HF) vapor, trifluoromethane (CHF3), nitrogen trifluoride (NF3), hydrogen (H2), ammonia (NH3), carbon tetrafluoride (CF4), sulfur hexafluoride (SF6), or combinations thereof. In one embodiment, a selective wet etching process is performed at block 422. After selective removal of the dummy layer 230, the channel component 2080 in the channel region 212C is re-exposed.

[0153] After releasing channel component 2080, as Figure 37As shown, a gate structure 250 is formed to enclose each channel member 2080. Although not explicitly stated, the gate structure 250 includes an interface layer interfacing with the channel member 2080 in the channel region 212C and the substrate 202, a gate dielectric layer above the interface layer, and a gate electrode layer above the gate dielectric layer. The interface layer may include a dielectric material such as silicon oxide, hafnium silicate, or silicon oxynitride. The interface layer may be formed by chemical oxidation, thermal oxidation, atomic layer deposition (ALD), chemical vapor deposition (CVD), and / or other suitable methods. The gate dielectric layer may include a high-k dielectric material such as hafnium oxide. Alternatively, the gate dielectric layer may comprise other high-k dielectric materials, such as titanium oxide (TiO2), hafnium zirconium oxide (HfZrO), tantalum oxide (Ta2O5), hafnium silicon oxide (HfSiO4), zirconium oxide (ZrO2), zirconium silicon oxide (ZrSiO2), lanthanum oxide (La2O3), aluminum oxide (Al2O3), zirconium oxide (ZrO), yttrium oxide (Y2O3), hafnium lanthanum oxide (HfLaO), lanthanum silicon oxide (LaSiO), aluminum silicon oxide (AlSiO), hafnium tantalum oxide (HfTaO), hafnium titanium oxide (HfTiO), or combinations thereof, or other suitable materials. The gate dielectric layer may be formed using ALD, physical vapor deposition (PVD), CVD, oxidation, and / or other suitable methods.

[0154] The gate electrode layer of gate structure 250 may include a multilayer structure, such as a metal layer (work function metal layer) having a selected work function to enhance device performance, a substrate, a wetting layer, an adhesive layer, a metal alloy, or a combination of metal silicides. For example, the gate electrode layer may include titanium nitride (TiN), titanium aluminum nitride (TiAl), titanium aluminum nitride (TiAlN), tantalum nitride (TaN), tantalum aluminum nitride (TaAl), tantalum aluminum nitride (TaAlN), tantalum aluminum carbide (TaAlC), tantalum carbonitride (TaCN), aluminum (Al), tungsten (W), nickel (Ni), titanium (Ti), ruthenium (Ru), cobalt (Co), platinum (Pt), tantalum carbide (TaC), tantalum silicon nitride (TaSiN), copper (Cu), other refractory metals, or other suitable metallic materials or combinations thereof. In various embodiments, the gate electrode layer may be formed by ALD, PVD, CVD, electron beam evaporation, or other suitable processes. In various embodiments, a CMP process may be performed to remove excess metal, thereby providing a generally flat top surface of the gate structure. Gate structure 250 includes portions located between channel members 2080 in channel region 212C. In some embodiments, gate structure 250 may include a p-type gate structure portion and an n-type gate structure portion. The p-type gate structure portion includes a p-type work function metal layer disposed closer to the channel member 2080. The n-type gate structure portion includes an n-type work function metal layer disposed closer to the channel member 2080.

[0155] See Figure 21 and Figure 38 Method 400 includes block 424, in which a front-side interconnect structure 270 is formed. The operations at block 424 are substantially similar to those at block 122 described above. Therefore, for the sake of brevity, a detailed description of the operations at block 424 is omitted.

[0156] See Figure 21 and Figures 39 to 44 Method 400 includes block 426, in which rear-side devices 200B1 to 200B5 are formed above the dopant implantation profile. The operation at block 426 is substantially similar to the operation at block 124 described above. Furthermore, Figures 40 to 44 The rear-side devices 200B1, 200B2, 200B3, 200B4 and 200B5 shown can be used with Figures 16 to 20 The rear-side devices 200B1, 200B2, 200B3, 200B4, and 200B5 shown are essentially similar. Therefore, for the sake of brevity, a detailed description of the operation at block 426 and the resulting rear-side device is omitted.

[0157] Figure 45 and Figure 46 This is a cross-sectional view of device die 500, which includes a rear-side device formed using method 100 or 400 described above. First, see... Figure 45. Figure 45 The device die 500 includes a substrate 510, which includes a front device 510F and a rear device 510B. The front device 510F includes a FEOL device. The rear device 510B may include rear devices 200B1, 200B2, 200B3, 200B4, and 200B5 formed using methods 100 or 400 described above. A front interconnect structure 270 is disposed above the front side of the substrate 510. A rear interconnect structure 290 is disposed above the rear side of the substrate 510. A carrier substrate 280 is bonded to the top surface of the front interconnect structure 270 via a pair of bonding layers 275. In some embodiments, the device die 500 includes a micron-sized through-substrate-via (TSV) 550 extending through the substrate 510 to route power signals from the front side of the substrate 510 to the rear side of the substrate 510. In some embodiments, the micron-scale TSV 550 includes a diameter or width between about 0.3 μm and about 0.8 μm and a vertical length between about 3 μm and about 7 μm. Figure 46 The device chip 500 and Figure 45 Similar to the device die 500, except that the micron-sized TSV 550 is replaced by a nano-sized TSV 560. Like the micron-sized TSV 550, the nano-sized TSV 560 is also used to route power signals from the front side of the substrate 510 to the rear side of the substrate 510. In some embodiments, the nano-sized TSV 560 includes a diameter or width between about 50 nm and about 150 nm and a vertical length between about 300 nm and about 500 nm.

[0158] In one exemplary embodiment, this disclosure relates to a device structure. The device structure includes a substrate having a front side and a rear side, a fin structure located above the front side, a plurality of nanostructures located above the fin structure, a gate structure covering each of the nanostructures, a first doped region located above the rear side of the substrate, a rear dielectric layer located above the first doped region, and a first contact feature extending through the rear dielectric layer to interface with the first doped region.

[0159] In some embodiments, the device structure further includes a silicide layer sandwiched between the first contact feature and the first doped region. In some embodiments, the device structure further includes a second contact feature extending through the back dielectric layer to interface with the first doped region, an electrode disposed in the back dielectric layer between the first contact feature and the second contact feature, an interface layer disposed between the electrode and the first doped region, and a high-k dielectric layer disposed between the interface layer and the electrode. In some embodiments, the electrode comprises titanium nitride or polycrystalline silicon. In some instances, the interface layer comprises silicon oxynitride. In some embodiments, the high-k dielectric layer comprises hafnium oxide. In some embodiments, the device structure further includes a spacer layer disposed along the sidewalls of the electrode, the interface layer, and the high-k dielectric layer.

[0160] In another exemplary embodiment, this disclosure relates to a device structure. The device structure includes a substrate having a front side and a rear side, a plurality of nanostructures disposed on the front side, a gate structure covering each of the nanostructures, a front interconnect structure disposed on the gate structure and the nanostructures, a first doped region disposed on the rear side of the substrate, and a rear device disposed on the first doped region.

[0161] In some embodiments, the device structure further includes a rear dielectric layer disposed above the first doped region, a first contact feature and a second contact feature extending through the rear dielectric layer to interface with the first doped region, an electrode disposed between the first contact feature and the second contact feature in the rear dielectric layer, an interface layer disposed between the electrode and the first doped region, and a high-k dielectric layer disposed between the interface layer and the electrode. In some embodiments, the electrode comprises titanium nitride or polycrystalline silicon. In some embodiments, the interface layer comprises silicon oxynitride. In some embodiments, the high-k dielectric layer comprises hafnium oxide. In some instances, each of the first contact feature and the second contact feature interfaces with the first doped region via a silicide feature. In some embodiments, the device structure further includes a spacer layer disposed along the sidewalls of the electrode, the interface layer, and the high-k dielectric layer.

[0162] In another exemplary embodiment, this disclosure relates to a method. The method includes the following steps: performing an ion implantation process on a substrate to form doped regions; forming a stack over the substrate, the stack including multiple channel layers interleaved with multiple sacrificial layers; patterning the stack and the substrate to form a fin structure having a base portion formed by the substrate and a stack portion formed by the stack; forming isolation features around the base portion; forming a dummy gate stack over the channel regions of the fin structure; depositing a gate spacer layer over the dummy gate stack; after depositing the gate spacer layer, recessing the source / drain regions of the fin structure to form source / drain trenches extending into the base portion; selectively removing these sacrificial layers from the channel regions. The process involves: releasing the channel layers that serve as multiple channel components; depositing dummy layers over these channel components; selectively and partially recessing the dummy layers to form internal spacer trenches between these channel components and forming bottom dummy features on the bottom surface of the source / drain trenches; forming internal spacer features in the internal spacer trenches; forming source / drain features over the source / drain regions; removing the dummy gate stack after forming the source / drain features; removing the dummy layers; forming a gate structure to cover each of these channel components; forming a front-side interconnect structure over the gate structure; and forming a rear-side device over the doped regions after forming the front-side interconnect structure.

[0163] In some embodiments, the step of forming a rear-side device includes the following steps: bonding a carrier substrate to a front-side interconnect structure; after bonding, flipping the substrate over; forming an electrode over a doped region; depositing a rear-side dielectric layer over the doped region and the electrode; and forming a first contact feature and a second contact feature via the rear-side dielectric layer to interface with the doped region. The electrode is disposed between the first contact feature and the second contact feature. In some embodiments, the step of forming the first contact feature and the second contact feature includes the following steps: forming a first contact opening and a second contact opening via the rear-side dielectric layer to expose the doped region; forming a first silicide feature in the first contact opening and a second silicide feature in the second contact opening; and depositing a metal filler layer over the first silicide feature and the second silicide feature. In some embodiments, the method further includes the following steps: depositing an interface layer over the doped region before forming the electrode over the doped region. After forming the electrode, disposing the interface layer between the doped region and the electrode. In some embodiments, the method further includes the following steps: depositing a high-k dielectric layer on the interface layer over the doped region before forming the electrode over the doped region. After forming the electrode, disposing the interface layer and the high-k dielectric layer between the doped region and the electrode. In some embodiments, the back-side device includes a diode, a bipolar junction transistor, a resistor, a capacitor, a metal-oxide-semiconductor transistor, or embedded dynamic random access memory (eDRAM).

[0164] In another exemplary embodiment, this disclosure relates to a rear-side device structure. The rear-side device structure includes a substrate having a front side and a rear side, a plurality of nanostructures disposed above the front side of the substrate, a gate structure covering each of the nanostructures, a doped region disposed above the rear side of the substrate, and a rear-side device disposed above the doped region. The rear-side device includes a rear-side dielectric layer and contact features extending through the rear-side dielectric layer and mediating the doped region.

[0165] The foregoing summary outlines the features of several embodiments, enabling those skilled in the art to better understand the various aspects of this disclosure. Those skilled in the art should understand that this disclosure can be readily used as the basis for designing or modifying other processes and structures to achieve the same objectives and / or advantages as the embodiments described herein. Those skilled in the art should also recognize that these equivalent constructions do not depart from the spirit and scope of this disclosure, and that various changes, substitutions, and modifications can be made to these equivalent constructions without departing from the spirit and scope of this disclosure.

Claims

1. A rear-side device structure, characterized in that, Include: A substrate having a front side and a rear side; A fin-shaped structure is located above the front side; Multiple nanostructures are disposed above the fin-shaped structure; A gate structure that encapsulates each of the plurality of nanostructures; A doped region is disposed above the rear side of the substrate; A rear dielectric layer is located above the doped region; as well as A first contact feature extends through the back dielectric layer and interfaces with the doped region.

2. The rear-side device structure as described in claim 1, characterized in that, Further includes: A silicide layer is sandwiched between the first contact feature and the doped region.

3. The rear-side device structure as described in claim 1 or 2, characterized in that, Further includes: A second contact feature extends through the rear dielectric layer to interface the doped region; An electrode is disposed in the rear dielectric layer between the first contact feature and the second contact feature; An interface layer is disposed between the electrode and the doped region; and A high-k dielectric layer is disposed between the interface layer and the electrode.

4. The rear-side device structure as described in claim 3, characterized in that, It further includes a spacer layer disposed along multiple sidewalls of the electrode, the interface layer and the high-k dielectric layer.

5. A rear-side device structure, characterized in that, Include: A substrate having a front side and a rear side; Multiple nanostructures are disposed on the upper front side; A gate structure that encapsulates each of the plurality of nanostructures; A front-side interconnect structure is disposed above the gate structure and the plurality of nanostructures; A doped region is disposed above the rear side of the substrate; as well as A rear-side device is positioned above the doped region.

6. The rear-side device structure as described in claim 5, characterized in that, Further includes: A rear dielectric layer is disposed above the doped region; A first contact feature and a second contact feature extend through the rear dielectric layer to interface the doped region; An electrode is disposed in the rear dielectric layer between the first contact feature and the second contact feature; An interface layer is disposed between the electrode and the doped region; and A high-k dielectric layer is disposed between the interface layer and the electrode.

7. The rear-side device structure as described in claim 6, characterized in that, Each of the first contact feature and the second contact feature is interposed with the doped region through a silicide feature.

8. The rear-side device structure as described in claim 6 or 7, characterized in that, It further includes a spacer layer disposed along multiple sidewalls of the electrode, the interface layer and the high-k dielectric layer.

9. A rear-side device structure, characterized in that, Include: A substrate having a front side and a rear side; Multiple nanostructures are disposed on the upper front side; A gate structure that encapsulates each of the plurality of nanostructures; A doped region is disposed above the rear side of the substrate; as well as A rear-side device is disposed above the doped region, wherein the rear-side device includes: A rear dielectric layer; and A contact feature extends through the back dielectric layer and interfaces with the doped region.

10. The rear-side device structure as described in claim 9, characterized in that, The rear-side device includes a diode, a bipolar junction transistor, a resistor, a capacitor, a metal-oxide-semiconductor transistor, or an embedded dynamic random access memory.

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