Semiconductor structure

Abstract

A semiconductor structure includes source and drain features disposed in a substrate, a gate structure disposed over the substrate and between the source and drain features, and a first trapezoidal shallow trench isolation feature disposed in the substrate at least partially beneath the gate structure in a channel region between the source and drain features, the first trapezoidal shallow trench isolation feature including multiple portions of different depths, including a first depth portion and a second depth portion.

Description

Technical Field

[0001] This disclosure relates to a semiconductor structure. Background Technology

[0002] Semiconductor components are used in a variety of electronic applications, such as personal computers, mobile phones, digital cameras, and other electronic devices. Semiconductor components are typically manufactured by sequentially depositing an insulating or dielectric layer, a conductive layer, and a semiconductor layer on a semiconductor substrate, and using lithography and etching processes to pattern the various material layers to form circuit components and parts thereon.

[0003] The semiconductor industry continues to improve the integration density of various electronic components (e.g., transistors, diodes, resistors, capacitors, etc.) by continuously reducing the minimum feature size, thereby allowing more components to be integrated into a given area. However, as the minimum feature size decreases, other problems arise in each process used, and these other problems need to be addressed. Utility Model Content

[0004] According to some embodiments disclosed herein, a semiconductor structure includes a source feature and a drain feature disposed in a substrate; a gate structure disposed on the substrate and located between the source feature and the drain feature; and a first trapezoidal shallow trench isolation feature disposed in the substrate, which is at least partially located below the gate structure in the channel region between the source feature and the drain feature, the first trapezoidal shallow trench isolation feature including multiple portions of different depths, including a first depth portion and a second depth portion.

[0005] According to some embodiments disclosed herein, a semiconductor structure includes a substrate, source and drain features, a channel region, a gate structure, and a trapezoidal shallow trench isolation feature. The source and drain features are disposed in the substrate. The channel region is disposed in the substrate and located between the source and drain features. The gate structure is disposed above the channel region. The trapezoidal shallow trench isolation feature is located in the channel region. The trapezoidal shallow trench isolation feature includes multiple portions of different depths, including a first depth portion and a second depth portion, wherein the first depth portion has a first depth, the second depth portion has a second depth, and the first depth is greater than the second depth, wherein the ratio of the first depth to the second depth is between 1.2:1 and 3:1.

[0006] According to some embodiments disclosed herein, a semiconductor structure includes a source feature including a first doped region and a drain feature including a second doped region disposed in a substrate; a channel region disposed in the substrate and located between the source feature and the drain feature; a gate structure disposed above the channel region, wherein the channel region has a drain side that spans between the second doped region and a region in the substrate located in a lateral direction below a midpoint of the gate structure; and a first trapezoidal shallow trench isolation feature disposed on the drain side of the channel region, the first trapezoidal shallow trench isolation feature including multiple portions of different depths, including a first depth portion and a second depth portion. Attached Figure Description

[0007] When the following detailed description and appendix Figure 1 When reading this document, the following detailed description is recommended for a better understanding of its format. It should be emphasized that, in accordance with industry standard practice, the various features are not drawn to scale. In fact, for clarity of explanation, the dimensions of the various features may be arbitrarily increased or decreased.

[0008] Figure 1 This is a schematic cross-sectional view of an exemplary semiconductor device including a laterally diffused metal-oxide-semiconductor device according to some embodiments;

[0009] Figure 2A This is a schematic cross-sectional view of an exemplary LDMOS device according to some embodiments, the device including a 1L trapezoidal STI having a depth of 2 below the LDMOS gate structure;

[0010] Figure 2B This is a schematic cross-sectional view of an exemplary LDMOS device according to some embodiments, which includes a 2L trapezoidal STI with a depth of 3 below the LDMOS gate structure;

[0011] Figure 3A This is a schematic cross-sectional view of an exemplary LDMOS device according to some embodiments;

[0012] Figure 3B This is a schematic cross-sectional view of another exemplary LDMOS device according to some embodiments;

[0013] Figure 3C This is a schematic cross-sectional view of another exemplary LDMOS device according to some embodiments;

[0014] Figure 4A This is a schematic cross-sectional view of an example substrate having 1L STI features formed according to some embodiments;

[0015] Figure 4B This is a schematic cross-sectional view of an example 1L STI feature based on some embodiments;

[0016] Figure 5A An example substrate with a 1L trapezoidal STI structure according to some embodiments is shown, the 1L trapezoidal STI structure having a higher depth region and a lower depth region;

[0017] Figure 5B Another example substrate with a 1L trapezoidal STI structure according to some embodiments is shown, the 1L trapezoidal STI structure having a higher depth region and a lower depth region;

[0018] Figure 5C Another example substrate with a 1L trapezoidal STI structure according to some embodiments is shown, the 1L trapezoidal STI structure having a higher depth region and a lower depth region;

[0019] Figure 5D Another example substrate with an xL trapezoidal STI structure according to some embodiments is shown, the xL trapezoidal STI structure having multiple regions of different depths;

[0020] Figure 5E A top view of a substrate having a 1L trapezoidal STI structure according to some embodiments is shown, the structure having a lower depth region on the left side and a higher depth region on the right side of the 1L trapezoidal STI structure;

[0021] Figure 5F A top view of a substrate with a 1L trapezoidal STI structure is shown. According to the 1L trapezoidal STI structure, there are lower depth regions on the left and right sides of the 1L trapezoidal STI structure, and a higher depth region in the center of the 1L trapezoidal STI structure.

[0022] Figure 5G A top view of a substrate having a 1L trapezoidal STI structure according to some embodiments is shown, the 1L trapezoidal STI structure having a lower depth STI region on the right side of the 1L trapezoidal STI structure and a higher depth STI region on the left side.

[0023] Figure 5H A top view of a substrate with an xL trapezoidal STI structure is shown. According to the xL trapezoidal STI structure, there is a lower depth region on the left side of the xL trapezoidal STI structure, a higher depth region on the right side, and an intermediate depth region in depth order in between.

[0024] Figure 6A This is a schematic cross-sectional view of an exemplary device according to some embodiments;

[0025] Figure 6B This is a schematic cross-sectional view of another exemplary device according to some embodiments;

[0026] Figure 7 This is a flowchart of an exemplary method for manufacturing a semiconductor device having a trapezoidal STI feature, according to some embodiments;

[0027] Figures 8A to 8I These are cross-sectional views of a semiconductor device according to some embodiments at various stages of its manufacturing process.

[0028] Figure 9 This is a flowchart of another exemplary method for manufacturing a semiconductor device having a trapezoidal STI feature, according to some embodiments;

[0029] Figures 10A to 10E This is a schematic cross-sectional view of an exemplary LDMOS device including trapezoidal STI features according to some embodiments.

[0030] [Symbol Explanation]

[0031] 100: Semiconductor devices

[0032] 102:Substrate

[0033] 104: Interconnection Structure

[0034] 106:LDMOS device

[0035] 108: Metal Wire

[0036] 110: Through hole

[0037] 112: Source terminal

[0038] 114: Leakage Extreme

[0039] 116: Device welding pad

[0040] 118: Gate terminal

[0041] 120: High-voltage n-well / HVNW

[0042] 122: High Voltage P-Surround / HVPW

[0043] 124: Deep n-well / DNW

[0044] 126:STI

[0045] 128: Gate Structure

[0046] 130: Doped region

[0047] 131:n+ doped region

[0048] 132: p+ doped region

[0049] 134: STI characteristics

[0050] 135: First Depth Section

[0051] 136: First Depth

[0052] 137: Second Depth Section

[0053] 138: Second Depth

[0054] 200:LDMOS device

[0055] 202:1L Trapezoidal STI Features

[0056] 203: Depth

[0057] 204: Gate structure

[0058] 205: Depth

[0059] 206:Substrate

[0060] 208:HVNW

[0061] 210:HVPW

[0062] 212:DNW

[0063] 214:HVPW

[0064] 216:HVNW

[0065] 218:STI

[0066] 222: p+ doped region

[0067] 224: p+ doped region

[0068] 226: n+ doped region

[0069] 250:LDMOS device

[0070] 251: Depth

[0071] 252:2L Trapezoidal STI Features

[0072] 253: Depth

[0073] 254: Gate structure

[0074] 255: Depth

[0075] 256:Substrate

[0076] 258:HVNW

[0077] 260:HVPW

[0078] 262:DNW

[0079] 264:HVPW

[0080] 266:HVNW

[0081] 268:STI

[0082] 272: p+ doped region

[0083] 274: p+ doped region

[0084] 276:n+ doped region

[0085] 300:LDMOS device

[0086] 301: Gate Oxide

[0087] 302: Gate structure

[0088] 303: First Depth

[0089] 304:Substrate

[0090] 305: Second Depth

[0091] 306: Source Characteristics

[0092] 307: Width

[0093] 308: Drain characteristics

[0094] 310:1L Trapezoidal STI

[0095] 312: Outline

[0096] 320:LDMOS device

[0097] 321: Gate oxide

[0098] 322: Gate structure

[0099] 323: First Depth

[0100] 324:Substrate

[0101] 325: Second Depth

[0102] 326: Source Characteristics

[0103] 327: Width

[0104] 328: Drain characteristics

[0105] 330:1L Trapezoidal STI

[0106] 332: Outline

[0107] 340:LDMOS device

[0108] 341: Gate oxide

[0109] 342: Gate structure

[0110] 343: First Depth

[0111] 344:Substrate

[0112] 345: Second Depth

[0113] 346: Source Characteristics

[0114] 347: Width

[0115] 348: Drain characteristics

[0116] 350:1L Trapezoidal STI

[0117] 352: Outline

[0118] 400:1L STI Features

[0119] 401:Substrate

[0120] 402: First Depth

[0121] 404: Second Depth

[0122] 406:First interior angle

[0123] 408:Second interior angle

[0124] 410:Third inside corner

[0125] 412:First outside corner

[0126] 414:Second outside corner

[0127] 416:Third outside corner

[0128] 420: Top surface

[0129] 422: First Wall

[0130] 424: The Second Wall

[0131] 426: The Third Wall

[0132] 428: First bottom surface

[0133] 430: Second bottom surface

[0134] 440:1L STI Features

[0135] 442: First Depth

[0136] 444: Second Depth

[0137] 446:First interior angle

[0138] 448:Second interior angle

[0139] 450:Third inside angle

[0140] 452:First outside corner

[0141] 454:Second outside corner

[0142] 456:Third outside corner

[0143] 460: Top surface

[0144] 462: The First Wall

[0145] 464: The Second Wall

[0146] 466: The Third Wall

[0147] 468: First bottom surface

[0148] 470: Second bottom surface

[0149] 501:Substrate

[0150] 502:1L Trapezoidal STI Structure

[0151] 504: Higher depth area

[0152] 506: Lower depth area

[0153] 521:Substrate

[0154] 522:1L Trapezoidal STI Structure

[0155] 524: Higher depth area

[0156] 526: Lower depth area

[0157] 541:Substrate

[0158] 542:1L Trapezoidal STI Structure

[0159] 544: Higher depth area

[0160] 546: Lower depth region

[0161] 561:Substrate

[0162] 562:xL trapezoidal STI structure

[0163] 564: First Depth Region

[0164] 566: Second Depth Region

[0165] 568: Third Depth Region

[0166] 570: Fourth Depth Region

[0167] 572: Fifth Depth Region

[0168] 600: Device

[0169] 602: Gate structure

[0170] 603: Gate Oxide

[0171] 604:Substrate

[0172] 606: Source Characteristics

[0173] 608: Drain Characteristics

[0174] 610: Left 1L STI structure

[0175] 620: Device

[0176] 622: Gate structure

[0177] 623: Gate oxide

[0178] 624:Substrate

[0179] 626: Source Characteristics

[0180] 628: Drain Characteristics

[0181] 630: Left 1L STI structure

[0182] 632: Right 1L STI structure

[0183] 700: Method

[0184] 710: Frame

[0185] 720: Box

[0186] 730: Box

[0187] 740: Box

[0188] 750: Box

[0189] 760: Box

[0190] 770: Box

[0191] 780: Box

[0192] 790: Box

[0193] 802: Semiconductor substrate

[0194] 803: Injection Zone

[0195] 804: Injection Zone

[0196] 805: Injection Zone

[0197] 807: Injection Area

[0198] 808: Patterned Mask Layer

[0199] 810: Opening

[0200] 812: Groove

[0201] 814: STI groove area

[0202] 816: Area 1

[0203] 818: Second Area

[0204] 820: Trapezoidal STI structure

[0205] 822:LDMOS device

[0206] 824: Gate structure

[0207] 825: Gate Oxide

[0208] 826: Gate spacer

[0209] 828: Source Characteristics

[0210] 830: Drain Characteristics

[0211] 832: Contact element

[0212] 834: Metal Wire

[0213] 900: Method

[0214] 910: Frame

[0215] 920: Box

[0216] 930: Box

[0217] 940: Box

[0218] 950: Box

[0219] 1000:HV Asymmetric NMOS Device

[0220] 1002: Trapezoidal STI Features

[0221] 1010:HV Symmetrical NMOS Device

[0222] 1012: First Trapezoidal STI Feature

[0223] 1014: Second Trapezoidal STI Feature

[0224] 1020:HV Asymmetric PMOS Device

[0225] 1022: Trapezoidal STI Features

[0226] 1030:HV Symmetrical PMOS Device

[0227] 1032: First Trapezoidal STI Feature 1032

[0228] 1034: Second Trapezoidal STI Feature

[0229] 1040:HV Isolated NMOS Device

[0230] 1042: Trapezoidal STI Features Detailed Implementation

[0231] The following disclosure provides numerous different embodiments or instances for implementing various features of this disclosure. Specific examples of components and configurations are described below to simplify the disclosure. Of course, these components and configurations are merely examples and are not intended to be limiting.

[0232] For simplicity, conventional techniques related to the manufacture of conventional semiconductor devices are not described in detail herein. Furthermore, various tasks and processes described herein can be integrated into more comprehensive steps or processes with additional functions not detailed herein. In particular, various processes for manufacturing semiconductor devices are well-known; therefore, for brevity, many conventional processes will be mentioned only briefly or omitted entirely without providing well-known process details. As will be readily apparent to those skilled in the art upon a full reading of this disclosure, the structures disclosed herein can be used with a variety of techniques and can be incorporated into a variety of semiconductor devices and products. Furthermore, it should be noted that semiconductor device structures include varying numbers of elements, and a single element shown in the figures may represent multiple elements.

[0233] Furthermore, spatially relative terms such as "above," "upper layer," "above," "higher," "top," "lower," "lower," "below," "bottom," etc., can be used to facilitate the description of the relationship between one or more components or features in the accompanying drawings and another component or feature(s). Spatially relative terms are used to include different orientations of the device in use or operation, as well as the orientations described in the accompanying drawings. When the device is turned to different orientations (rotated 90 degrees or other orientations), the spatially relative adjectives used will also be interpreted according to the orientation after the turn. When spatially relative terms such as those listed above are used to describe a second element relative to a first element, the first element may be directly on the other element, or there may be an intermediate element or layer between them. When an element or layer is referred to as being "on" another element or layer, it is directly on and in contact with the other element or layer.

[0234] Furthermore, reference values ​​and / or letters may be repeated in various examples in this disclosure. Such repetition is for the purpose of brevity and clarity, and is not intended to indicate a relationship between the different implementations and / or configurations discussed.

[0235] It should be noted that references to "an embodiment," "an embodiment," "an exemplary embodiment," "some embodiments," etc., in the specification indicate that the described embodiments may include specific features, structures, or characteristics, but each embodiment may not necessarily include that specific feature, structure, or characteristic. Furthermore, such phrases do not necessarily refer to the same embodiment. In addition, when a specific feature, structure, or characteristic is described in connection with an embodiment, whether explicitly described or not, implementing such a feature, structure, or characteristic in conjunction with other embodiments is within the knowledge of those skilled in the art.

[0236] It should be understood that the phrases or terms used herein are for description and not limitation, and those skilled in the art will be able to understand the terms or phrases in this specification in light of the teachings herein.

[0237] The following disclosure provides numerous different embodiments or instances for implementing various features of this disclosure. Specific examples of components and configurations are described below to simplify this disclosure. Of course, these components and configurations are merely examples and are not intended to be limiting. For example, in the following description, the formation of a first feature on or over a second feature may include embodiments where the first and second features are formed in direct contact, and may also include embodiments where additional features are formed between the first and second features so that the first and second features are not in direct contact. Throughout the description herein, unless otherwise specified, the same reference numerals in the different figures refer to the same or similar components formed using the same or similar materials and the same or similar forming methods.

[0238] As used herein, terms such as “first,” “second,” and “third” describe various elements, components, regions, layers, and / or sections, but these elements, components, regions, layers, and / or sections should not be limited by these terms. These terms may be used only to distinguish one element, component, region, layer, or section from another. For example, the terms “first,” “second,” and “third” as used herein do not imply any order or sequence unless the context clearly indicates otherwise.

[0239] As used herein, the terms “approximately,” “substantially,” “basically,” and “about” are used to describe and explain minute variations. When used in conjunction with an event or situation, the terms may refer to instances where the event or situation occurred precisely or instances where the event or situation approximately occurred. For example, when used in conjunction with a numerical value, the terms may refer to a range of variation less than or equal to ±10% of that value, such as less than or equal to ±5%, less than or equal to ±4%, less than or equal to ±3%, less than or equal to ±2%, less than or equal to ±1%, less than or equal to ±0.5%, less than or equal to ±0.1%, or less than or equal to ±0.05%. For example, if the difference between multiple values ​​is less than or equal to ±10% of the average of those values ​​(e.g., less than or equal to ±5%, less than or equal to ±4%, less than or equal to ±3%, less than or equal to ±2%, less than or equal to ±1%, less than or equal to ±0.5%, less than or equal to ±0.1%, or less than or equal to ±0.05%), then the two values ​​may be considered “substantially” the same or equal. For example, "essentially parallel" can refer to an angle variation of less than or equal to ±10° relative to 0°, such as less than or equal to ±5°, less than or equal to ±4°, less than or equal to ±3°, less than or equal to ±2°, less than or equal to ±1°, less than or equal to ±0.5°, less than or equal to ±0.1°, or less than or equal to ±0.05°. Similarly, "essentially perpendicular" can refer to an angle variation of less than or equal to ±10° relative to 90°, such as less than or equal to ±5°, less than or equal to ±4°, less than or equal to ±3°, less than or equal to ±2°, less than or equal to ±1°, less than or equal to ±0.5°, less than or equal to ±0.1°, or less than or equal to ±0.05°.

[0240] Figure 1 This is a schematic cross-sectional view of an exemplary semiconductor device 100 including a laterally diffused metal-oxide-semiconductor device (LDMOS device 106) according to some embodiments. The exemplary semiconductor device 100 includes a substrate 102 and an interconnect structure 104 covering the substrate 102. The substrate 102 includes a plurality of high-voltage n-well (HVNW) 120 structures, a plurality of high-voltage p-well (HVPW) 122 structures, and a deep n-well (DNW) 124 structure. The substrate 102 also includes shallow trench isolation (STI) features 126 for isolating the various devices. In this example, the LDMOS device 106 is formed in and on the substrate 102. The interconnect structure 104 includes a metal line 108 and a via 110, which connects the source terminal 112 and drain terminal 114 of the LDMOS device 106 to the device pad 116 of the semiconductor device 100, and connects the gate terminal 118 of the LDMOS device 106 to other devices.

[0241] The exemplary LDMOS device 106 is a planar double-diffused MOSFET (metal-oxide-semiconductor field-effect transistor) used in amplifiers, including microwave power amplifiers, RF power amplifiers, and audio power amplifiers. The exemplary LDMOS device 106 includes a source feature formed in HVNW 120, a drain feature formed in HVPW 122, and a gate structure 128 formed on a channel region in substrate 102 and between the source and drain features. The source feature includes a p+ (positively charged) doped region 130 in HVNW 120, and the drain feature includes a p+ doped region 132 in HVPW 122. The doped regions of the source and drain features have the same polarity type. In this example, the polarity type is positive. In other embodiments, the polarity can be negative. The LDMOS device 106 also includes an n+ (negatively charged) doped region 131 in the HVNW 120, which is separated from the p+ doped region 130 by an STI 126.

[0242] The LDMOS device 106 includes an STI feature 134 disposed in a substrate 102, which is at least partially located below the gate structure 128 in the channel region to prevent high voltage (HV) breakdown. The STI feature 134 is a trapezoidal STI feature having multiple portions of different depths; in this example, a first depth portion 135 has a first depth 136, and a second depth portion 137 has a second depth 138. The multiple depths allow the STI feature 134 to help prevent HV breakdown while simultaneously increasing the speed of the LDMOS device 106. The higher depth portions of the STI feature 134 (the first depth portion 135 with the first depth 136) help prevent HV breakdown, while the lower depth portions of the STI feature 134 (the second depth portion 137 with the second depth 138) help increase the speed of the LDMOS device 106. The channel region has a drain side spanning a region in the substrate 102 located below the middle position of the gate structure 128 in the lateral direction and a p+ doped region 132, and an STI feature 134 is disposed on the drain side of the channel region.

[0243] Figure 2A and Figure 2B This is a schematic cross-sectional view of an exemplary LDMOS device. This exemplary LDMOS device includes a trapezoidal STI below the LDMOS gate structure to help prevent HV breakdown while increasing the speed of the LDMOS device. Figure 2AThis is a schematic cross-sectional view of an exemplary LDMOS device 200, which includes a 1L trapezoidal STI feature 202 with two depths (depth 203 and depth 205) below the LDMOS gate structure 204. Figure 2B The diagram shows a schematic cross-sectional view of an exemplary LDMOS device 250, which includes a 2L trapezoidal STI feature 252 with three depths (depth 251, depth 253 and depth 255) below the LDMOS gate structure 254.

[0244] An exemplary LDMOS device 200 includes a substrate 206 having an HVNW 208, an HVPW 210, and a DNW 212. In various embodiments, the LDMOS device 200 also includes an HVPW 214, an HVNW 216, and an STI 218. The exemplary LDMOS device 200 includes a source feature formed in the HVNW 208, a drain feature formed in the HVPW 210, and a gate structure 204 formed over a channel region in the substrate 206 and between the source and drain features. The channel region has a drain side spanning a region in the substrate 206 located below the middle position of the gate structure 204 in the lateral direction between a region and a p+ doped region 224, and an 1L trapezoidal STI feature 202 is disposed on the drain side of the channel region.

[0245] The source feature includes a p+ doped region 222 in HVNW 208, and the drain feature includes a p+ doped region 224 in HVPW 210. The doped regions of the source feature and the doped regions of the drain feature have the same polarity type. In this example, the polarity type is positive. In other embodiments, the polarity can be negative. LDMOS device 200 also includes an n+ doped region 226 in HVNW 208, which is separated from the p+ doped region 222 by STI 218.

[0246] An exemplary LDMOS device 250 includes a substrate 256 having an HVNW 258, an HVPW 260, and a DNW 262. In various embodiments, the LDMOS device 250 also includes an HVPW 264, an HVNW 266, and an STI 268. The exemplary LDMOS device 250 includes a source feature formed in the HVNW 258, a drain feature formed in the HVPW 260, and a gate structure 254 formed over a channel region in the substrate 256 and between the source and drain features. The channel region has a drain side spanning a region in the substrate 256 located below the middle position of the gate structure 254 in the lateral direction between a region and a p+ doped region 274, and a 2L trapezoidal STI part 252 is disposed on the drain side of the channel region.

[0247] The source feature includes a p+ doped region 272 in HVNW 208, and the drain feature includes a p+ doped region 274 in HVPW 260. The doped regions of the source feature and the doped regions of the drain feature have the same polarity type. In this example, the polarity type is positive. In other embodiments, the polarity can be negative. LDMOS device 250 also includes an n+ doped region 276 in HVNW 258, which is separated from the p+ doped region 272 by STI 268.

[0248] Figure 2A The example shows a 1L trapezoidal STI structure. Figure 2B The example illustrates a 2L trapezoidal STI structure. In other embodiments, an xL trapezoidal STI structure with x+1 different depths can be formed.

[0249] Figure 3A , Figure 3B and Figure 3C This is a schematic cross-sectional view of an example LDMOS device containing a trapezoidal STI beneath the LDMOS gate structure. Figure 3A This is a schematic cross-sectional view of an exemplary LDMOS device 300. The LDMOS device 300 includes a gate structure 302 and a gate oxide 301 above a substrate 304, a source feature 306 in the substrate 304, and a drain feature 308 in the substrate 304. The LDMOS device 300 also includes a 1L trapezoidal STI 310 having two depths (a first depth 303 and a second depth 305) and a width 307 in the channel region of the substrate 304 below the gate structure 302 on the drain side of the channel region. Each of the first depth 303 and the second depth 305 extends into the substrate 304 lower than the bottom of the source feature 306 and the bottom of the drain feature 308. In various embodiments, the ratio of the first depth 303 to the second depth 305 is from about 1.2:1 to about 3:1.

[0250] Different LDMOS devices (not shown) can be formed on a substrate 304 including a single-depth STI feature (not shown) at least partially disposed beneath the gate structure of the different LDMOS devices, in the channel region of the different LDMOS devices between the source and drain features of the different LDMOS devices. A dimensional outline 312 of the single-depth STI feature is shown to illustrate the relative dimensions of a 1L trapezoidal STI 310, which can prevent HV breakdown while improving the speed of the LDMOS device 300. The single-depth STI feature can have a first depth 303 and a width 307. The speed improvement of the LDMOS device 300 relative to an LDMOS device with a single-depth STI (as shown in outline 312) can be achieved by using a 1L trapezoidal STI 310 because the STI 310 with a second depth 305 can provide a shorter channel path between the source feature 306 and the drain feature 308 than a single-depth STI with the same first depth 303 and width 307.

[0251] Figure 3B This is a schematic cross-sectional view of an exemplary LDMOS device 320. The LDMOS device 320 includes a gate structure 322 and a gate oxide 321 above a substrate 324, a source feature 326 in the substrate 324, and a drain feature 328 in the substrate 324. The LDMOS device 320 also includes a 1L trapezoidal STI 330 having two depths (a first depth 323 and a second depth 325) and a width 327 in the channel region of the substrate 324 below the gate structure 322 on the drain side of the channel region. Each of the first depth 323 and the second depth 325 extends into the substrate 324 lower than the bottom of the source feature 326 and the bottom of the drain feature 328. In various embodiments, the ratio of the first depth 323 to the second depth 325 is from about 1.2:1 to about 3:1.

[0252] Different LDMOS devices (not shown) can be formed on substrate 324, which includes a single-depth STI feature (not shown) at least partially disposed under the gate structure of the different LDMOS devices, between the source and drain features of the different LDMOS devices. A contour 332 of the single-depth STI feature is shown to illustrate the relative dimensions of the 1L trapezoidal STI 330, which prevents HV breakdown while increasing the speed of the LDMOS device 320. The single-depth STI feature can have a depth shorter than the first depth 323 and a width narrower than the width 327. By using the 1L trapezoidal STI 330, higher HV performance can be achieved in the LDMOS device 320 than in an LDMOS device with a single-depth STI (as shown in contour 332). The first depth 323 and width 327 are increased to provide greater HV performance, and a second depth 325 reduces speed losses that may occur due to the increased first depth 323 and width 327. The second depth 325 of the STI 330 can provide a shorter channel path between the source feature 326 and the drain feature 328 than a single-depth STI with the same first depth 323 and width 327.

[0253] Figure 3C This is a schematic cross-sectional view of an exemplary LDMOS device 340. The LDMOS device 340 includes a gate structure 342 and a gate oxide 341 above a substrate 344, a source feature 346 in the substrate 344, and a drain feature 348 in the substrate 344. The LDMOS device 340 also includes a 1L trapezoidal STI 350 having two depths (a first depth 343 and a second depth 345) and a width 347 in the channel region of the substrate 344 below the gate structure 342 on the drain side of the channel region. Each of the first depth 343 and the second depth 345 extends into the substrate 344 lower than the bottom of the source feature 346 and the bottom of the drain feature 348. In various embodiments, the ratio of the first depth 343 to the second depth 345 is from about 1.2:1 to about 3:1.

[0254] Different LDMOS devices (not shown) can be formed on a substrate 344, which includes a single-depth STI feature (not shown) at least partially disposed under the gate structure of the different LDMOS devices, between the source and drain features of the different LDMOS devices. A dimensional outline 352 of the single-depth STI feature is shown to illustrate the relative dimensions of a 1L trapezoidal STI 350, which can prevent HV breakdown while increasing the speed of the LDMOS device 340. The single-depth STI feature can have a depth greater than a first depth 343 and a width narrower than a width of 347. A balance of HV protection and speed enhancement in the LDMOS device 340 can be achieved by using a 1L trapezoidal STI 350 compared to an LDMOS device with a single-depth STI (as shown in outline 352). The increased width 347 provides greater HV performance, and the reduction in the first and second depths 345 can increase the device speed and offset the speed loss due to the increased width 347. The second depth 345 of the STI 350 can provide a shorter channel path between the source feature 346 and the drain feature 348 than a single-depth STI with the same first depth 343 and width 347.

[0255] Figure 4A This is a schematic cross-sectional view of an example substrate 401 in which the 1L STI feature 400 is formed. The 1L STI feature 400 has two depths, namely a first depth 402 and a second depth 404, wherein the first depth 402 is greater than the second depth 404. The 1L STI feature 400 has a top surface 420, a first wall 422, a second wall 424, a third wall 426, a first bottom surface 428, and a second bottom surface 430. The first wall 422 is located between the top surface 420 and the first bottom surface 428. The second wall is located between the first bottom surface 428 and the second bottom surface 430. The third wall 426 is located between the second bottom surface 430 and the top surface 420. The first bottom surface 428 is located between the first wall 422 and the second wall 424. The second bottom surface 430 is located between the second wall 424 and the third wall 426. In various embodiments, the first wall 422 is a curved first wall, the first bottom surface 428 is a curved first bottom surface, the second wall 424 is a curved second wall, the second bottom surface 430 is a curved bottom surface, and the third wall 426 is a curved bottom surface.

[0256] The 1L STI feature 400 has multiple STI interior angles (first interior angle 406, second interior angle 408, and third interior angle 410). The first interior angle 406 is located between the first wall 422 and the first bottom surface 428. The second interior angle 408 is located between the second bottom surface 430 and the third wall 426. The third interior angle 410 is located between the second bottom surface 430 and the second wall 424. The size of the first interior angle 406 is approximately equal to the size of the second interior angle 408. The size of the third interior angle 410 is greater than the sizes of the first interior angle 406 and the second interior angle 408.

[0257] The 1L STI feature 400 has multiple STI outer angles (first outer angle 412, second outer angle 414, and third outer angle 416). The first outer angle 412 is located between the top surface 420 and the first wall 422. The second outer angle 414 is located between the first bottom surface 428 and the second wall 424. The third outer angle 416 is located between the top surface 420 and the third wall 426. The size of the first outer angle 412 is approximately equal to the size of the third outer angle 416. The size of the second outer angle 414 is greater than the sizes of both the first outer angle 412 and the third outer angle 416.

[0258] Figure 4B This is a schematic cross-sectional view of Example 1L STI feature 440. 1L STI feature 440 has two depths, namely a first depth 442 and a second depth 444, where the first depth 442 is greater than the second depth 444. 1L STI feature 440 has a top surface 460, a first wall 462, a second wall 464, a third wall 466, a first bottom surface 468, and a second bottom surface 470.

[0259] 1L STI feature 440 has multiple STI interior angles (first interior angle 446, second interior angle 448, and third interior angle 450). The first interior angle 446 is located between the first wall 462 and the first bottom surface 468. The second interior angle 448 is located between the second bottom surface 470 and the third wall 466. The third interior angle 450 is located between the second bottom surface 470 and the second wall 464. The size of the first interior angle 446 is approximately equal to the size of the second interior angle 448. The size of the third interior angle 450 is greater than the sizes of the first interior angle 446 and the second interior angle 448.

[0260] The 1L STI feature 440 has multiple STI outer angles (first outer angle 452, second outer angle 454, and third outer angle 456). The first outer angle 452 is located between the top surface 460 and the first wall 462. The second outer angle 454 is located between the first bottom surface 468 and the second wall 464. The third outer angle 456 is located between the top surface 460 and the third wall 466. The size of the first outer angle 452 is approximately equal to the size of the third outer angle 456. The size of the second outer angle 454 is greater than the sizes of both the first outer angle 452 and the third outer angle 456.

[0261] In various embodiments, the difference between the first depth 442 and the second depth 444 can be greater than 0 angstroms. The range extends up to approximately 3000 angstroms. In various embodiments, the ratio of the first depth 442 to the second depth 444 is approximately 1.2:1 to approximately 3:1. In various embodiments, each of the first interior angle 446, the second interior angle 448, the third interior angle 450, the first exterior angle 452, the second exterior angle 454, and the third exterior angle 456 has a size greater than (>) 90°. In various embodiments, each of the first interior angle 446, the second interior angle 448, the third interior angle 450, the first exterior angle 452, the second exterior angle 454, and the third exterior angle 456 has a size less than (<) 180°.

[0262] In various embodiments, traces of doped elements used to form deeper portions of STI features can be detected in the substrate near the deep trench region at an elemental concentration of approximately 1E+17 to 1E+18. In various embodiments, n-type materials such as arsenic / phosphorus / antimony can be used to form portions of STI features with greater depth in the substrate.

[0263] Figures 5A to 5D This is a schematic cross-sectional view of an exemplary trapezoidal STI configuration in a substrate according to various embodiments, and Figures 5E to 5H This is a schematic top view of the example trapezoidal STI configuration.

[0264] Figure 5A An example substrate 501 with a 1L trapezoidal STI structure 502 is shown, the 1L trapezoidal STI structure 502 having a higher depth region 504 and a lower depth region 506. In this example, the lower depth region 506 of the 1L trapezoidal STI structure 502 is located on the left side of the 1L trapezoidal STI structure 502, and the higher depth region 504 of the 1L trapezoidal STI structure 502 is located on the right side of the 1L trapezoidal STI structure 502. Figure 5E A top view of a substrate 501 with a 1L trapezoidal STI structure 502 is shown. The 1L trapezoidal STI structure 502 has a lower depth region 506 on the left and a higher depth region 504 on the right. This configuration can be considered as a left 1L STI structure.

[0265] Figure 5BAn example substrate 521 with a 1L trapezoidal STI structure 502 is shown, the 1L trapezoidal STI structure 502 having a higher depth region 524 and a lower depth region 526. In this example, the lower depth region 526 of the 1L trapezoidal STI structure 522 is located on both the left and right sides of the 1L trapezoidal STI structure 522. The higher depth region 524 of the 1L trapezoidal STI structure 522 is located at the center of the 1L trapezoidal STI structure 522. Figure 5F A top view of a substrate 521 with a 1L trapezoidal STI structure 522 is shown, the 1L trapezoidal STI structure 522 having a lower depth region 526 on the left and right sides of the 1L trapezoidal STI structure 522 and a higher depth region 524 at the center of the 1L trapezoidal STI structure 522. This configuration can be considered as an intermediate 1L STI structure.

[0266] Figure 5C An example substrate 541 with a 1L trapezoidal STI structure 542 is shown, the 1L trapezoidal STI structure 542 having a higher depth region 544 and a lower depth region 546. In this example, the lower depth region 546 of the 1L trapezoidal STI structure 542 is located on the right side of the 1L trapezoidal STI structure 542, and the higher depth STI region 544 of the 1L trapezoidal STI structure 542 is located on the left side of the 1L trapezoidal STI structure 542. Figure 5G A top view of a substrate 541 with a 1L trapezoidal STI structure 542 is shown. The 1L trapezoidal STI structure 542 has a lower depth STI region 546 located on the right side of the 1L trapezoidal STI structure 542 and a higher depth STI region 544 located on the left side of the 1L trapezoidal STI structure 542. This configuration can be considered a correct 1L STI structure.

[0267] Figure 5D An example substrate 561 with an xL trapezoidal STI structure 562 is shown, the xL trapezoidal STI structure 562 having multiple regions of different depths. In this example, x = 4 and there are 5 (e.g., x+1) depth regions. The 5 depth regions include a first depth region 564 (e.g., a higher depth region), a second depth region 566, a third depth region 568, a fourth depth region 570, and a fifth depth region 572 (a lower depth region). In this example, the lower depth region 572 of the xL trapezoidal STI structure 562 is located on the left side of the xL trapezoidal STI structure 562, and the higher depth region 564 of the xL trapezoidal STI structure 562 is located on the right side of the xL trapezoidal STI structure 562, with intermediate depth regions arranged in depth order between them. Figure 5HA top view of a substrate 561 with an xL trapezoidal STI structure 562 is shown. The xL trapezoidal STI structure 562 has a lower depth region 572 on the left and a higher depth region 564 on the right, with intermediate depth regions (second depth region 566, third depth region 568, and fourth depth region 570) arranged in depth sequence. This configuration can be considered a left-side 4L STI structure. The multiple depth levels in this configuration may result in faster device performance.

[0268] Figure 6A and Figure 6B This is a schematic cross-sectional view of an example device (e.g., an LDMOS device or other device) that includes a trapezoidal STI below the gate structure. Figure 6A This is a schematic cross-sectional view of an example device 600. Device 600 includes a gate structure 602 and a gate oxide 603 above a substrate 604, a source feature 606 in the substrate 604, and a drain feature 608 in the substrate 604. Device 600 also includes a left 1L STI structure 610 in the channel region of the substrate 604 below the gate structure 602 on the drain side of the channel region. This configuration can be considered an asymmetric LDMOS device configuration.

[0269] Figure 6B This is a schematic cross-sectional view of example device 620. Device 620 includes a gate structure 622 and a gate oxide 623 above a substrate 624, a source feature 626 in the substrate 624, and a drain feature 628 in the substrate 624. Device 620 also includes a left 1L STI structure 630 in the channel region of the substrate 624 below the gate structure 622 on the drain side of the channel region, and a right 1L STI structure 632 located in the channel region of the substrate 624 below the gate structure 622 on the source feature side of the channel region. This configuration can be considered a symmetrical device configuration.

[0270] Figure 7 This is a flowchart of an exemplary method 700 for manufacturing a semiconductor device having a trapezoidal STI feature, according to some embodiments. For illustrative purposes, reference will be made to... Figures 8A to 8I describe Figure 7 The operation shown, Figures 8A to 8I Cross-sectional views of a semiconductor device according to some embodiments are shown at various stages of its fabrication process. Depending on the specific application, the operations may be performed in different sequences or not at all. It should be noted that method 700 may not produce a complete semiconductor device. Therefore, it should be understood that additional processes may be provided before, during, and after the method, and only some of these other processes may be briefly described herein. In some figures, some reference numerals for components or features shown may be omitted to avoid obscuring other components or features; this is for convenience in depicting the figures.

[0271] Method 700 is merely an example and is not intended to limit this disclosure beyond what is expressly recited in the claims. Additional steps may be provided before, during, and after exemplary method 700, and some of the described steps may be moved, substituted, or eliminated for additional embodiments of exemplary method 700. Additional features may be added to the semiconductor device depicted in the figures, and some of the features described below may be replaced, modified, or eliminated in other embodiments of the semiconductor device.

[0272] It is understood that several parts of a semiconductor device can be manufactured using typical semiconductor technology manufacturing processes, and therefore only some processes are briefly described here. Furthermore, the exemplary semiconductor device may include various other devices and features, such as other types of devices, for example, additional transistors, bipolar junction transistors, resistors, capacitors, inductors, diodes, fuses, and / or other logic devices, but for ease of understanding of the concepts disclosed herein, the aforementioned devices are simplified. In some embodiments, the exemplary semiconductor device includes multiple semiconductor devices (such as transistors), including interconnectable p-type field-effect transistors, n-type field-effect transistors, etc. Secondly, it should be noted that the operation of method 700, including any description given with reference to the accompanying drawings, is merely illustrative and is not intended to limit the scope beyond what is expressly stated in the claims.

[0273] At box 710, method 700 includes providing a semiconductor substrate. (See reference...) Figure 8A As an example, in the embodiment of block 710, a semiconductor substrate 802 is provided. In various embodiments, the semiconductor substrate 802 is a planar surface having a uniform thickness. Further, the semiconductor substrate 802 can be p-type, for example, it can be a bulk silicon substrate or an SOI substrate.

[0274] At block 720, method 700 includes doping a substrate in one or more regions where a higher depth STI region is desired. In embodiments where an xL STI structure of x = 1 is desired, the substrate is doped at one depth. In embodiments where an xLSTI structure of x > 1 is desired, the substrate is doped at multiple depths. Each of the multiple depths will subsequently define the depth of the depth region in the subsequently formed xLSTI structure. In various embodiments, the doping depth is approximately equal to the depth difference between the desired lower depth STI region and the desired higher depth STI region. In various embodiments, the p-type substrate is doped with N+ implantation. In various embodiments, the N+ implantation includes arsenic, phosphorus, antimony, and / or other suitable materials.

[0275] refer to Figure 8BIn an example, in the embodiment of block 720, the semiconductor substrate 802 is doped with N+ implantation regions 804. This allows for the formation of a 1L STI structure with two depth levels. (See reference...) Figure 8C In another embodiment of block 720, the semiconductor substrate 802 is doped with a first N+ implantation region 803, a second N+ implantation region 805, and a third N+ implantation region 807. This allows for the formation of a 3L STI structure with four depth levels.

[0276] At frame 730, method 700 includes a masking layer above a patterned substrate, leaving an opening for the formation of the xL STI structure. (See reference) Figure 8D In an example, in the embodiment of frame 730, a patterned mask layer 808 is patterned over a substrate 802. The patterned mask layer 808 includes an opening 810 through which the substrate is subsequently etched to form an xL STI structure.

[0277] At frame 740, method 700 includes selectively etching the injection region within the opening to leave a groove. (Reference) Figure 8E In an example, in the embodiment of block 740, the implantation region 804 has been selectively etched from the substrate 802 within the opening 810 using a suitable etchant, leaving a groove 812. In various embodiments, each of the plurality of implantation regions is etched when it is accessible via the opening 810 (e.g., implantation region 803, implantation region 805, and implantation region 807).

[0278] At frame 750, method 700 includes etching the entire substrate area within an opening in the mask layer to form a trapezoidal STI recess. (Reference) Figure 8F In the embodiment of frame 750, the entire substrate region within the opening 810 is etched to create the STI recess region 814. The etching causes a previously etched area of ​​the substrate to be etched to a depth lower than a previously unetched area of ​​the substrate within the opening 810. This results in the STI recess region 814 having a first region 816 at a first depth and a second region 818 at a second depth. In various embodiments, etching the substrate region within the opening in the masking layer includes etching the substrate region using a dry etching technique.

[0279] At frame 760, method 700 includes filling the STI groove area with STI material to form a trapezoidal STI structure. (Reference) Figure 8G In the embodiment of frame 760, the STI groove region 814 is filled with STI material to form a trapezoidal STI structure 820.

[0280] At frame 770, method 700 includes forming a transistor device over a substrate and a trapezoidal STI structure. (Reference) Figure 8HIn the embodiment of block 770, an LDMOS device 822 is formed over a substrate 802 and a trapezoidal STI structure 820. The LDMOS device 822 includes a gate structure 824, a gate oxide 825, and a gate spacer 826 over the substrate 802. The LDMOS device 822 also includes a source feature 828 and a drain feature 830 in the substrate 802. The trapezoidal STI structure 820 is formed on the drain side of the channel region of the substrate 802.

[0281] At block 780, method 700 includes forming an interconnect structure including contacts and metal lines over a transistor device to connect the transistor device to other elements in a semiconductor device. Reference Figure 8I In the embodiment of block 780, the LDMOS device 822 is provided with contacts 832 and metal lines 834 to connect the LDMOS device 822 to other elements (not shown) in the semiconductor device.

[0282] At block 790, method 700 includes performing further manufacturing operations to complete the semiconductor device.

[0283] Figure 9 This is a flowchart of an exemplary method 900 for manufacturing a semiconductor device having a trapezoidal STI feature, according to some embodiments. For illustrative purposes, reference will be made to... Figures 8A to 8I describe Figure 9 The operation shown, Figures 8A to 8I Cross-sectional views of a semiconductor device according to some embodiments are shown at various stages of its fabrication process. Depending on the specific application, the operations may be performed in different sequences or not at all. It should be noted that method 900 may not produce a complete semiconductor device. Therefore, it should be understood that additional processes may be provided before, during, and after the method, and only some of these other processes may be briefly described herein. In some figures, some reference numerals for components or features shown may be omitted to avoid obscuring other components or features; this is for convenience in depicting the figures.

[0284] Method 900 is merely an example and is not intended to limit this disclosure beyond what is expressly recited in the claims. Additional steps may be provided before, during, and after exemplary method 900, and some of the described steps may be moved, substituted, or eliminated for additional embodiments of exemplary method 900. Additional features may be added to the semiconductor device depicted in the figures, and some of the features described below may be replaced, modified, or eliminated in other embodiments of the semiconductor device.

[0285] It is understood that several parts of a semiconductor device can be manufactured using typical semiconductor technology manufacturing processes, and therefore only some processes are briefly described here. Furthermore, the exemplary semiconductor device may include various other devices and features, such as other types of devices, for example, additional transistors, bipolar junction transistors, resistors, capacitors, inductors, diodes, fuses, and / or other logic devices, but for ease of understanding of the concepts disclosed herein, the aforementioned devices are simplified. In some embodiments, the exemplary semiconductor device includes multiple semiconductor devices (such as transistors), including interconnectable p-type field-effect transistors, n-type field-effect transistors, etc. Secondly, it should be noted that the operation of method 900, including any description given with reference to the accompanying drawings, is merely illustrative and is not intended to limit the scope beyond what is expressly stated in the claims.

[0286] At frame 910, method 900 includes identifying a first trapezoidal STI feature region in the substrate (e.g., the region where a trapezoidal STI structure 820 will be formed), wherein the first trapezoidal STI feature region includes at least a first depth portion region (e.g., first region 816) and a second depth portion region (e.g., second region 818).

[0287] At block 920, method 900 includes forming a charged implantation in a first depth portion region. In various embodiments, forming a charged implantation in the first depth portion includes doping the first depth portion region. In various embodiments, the charged implantation includes negatively charged (N+) implantation. Reference Figure 8B In the embodiment of block 920, an electrically charged injection is formed in the injection region 804 (e.g., a first depth portion region).

[0288] At frame 930, method 900 includes removing a first layer of substrate material from a first depth portion region. In various embodiments, removing the first layer of substrate material from the first depth portion region includes selectively etching the substrate with an etchant that is selective to charged injection.

[0289] At frame 940, method 900 includes removing a second layer of substrate material from a first depth portion region and a second depth portion region to form a trapezoidal STI groove. In various embodiments, removing the second layer of substrate material from the first depth portion region and the second depth portion region includes performing a dry etching operation on the first trapezoidal STI feature region.

[0290] At frame 950, method 900 includes filling a trapezoidal STI groove with an STI material to form a trapezoidal STI structure comprising a plurality of portions with different depths, said portions including a first depth portion and a second depth portion. In various embodiments, filling the trapezoidal STI groove with an STI material includes depositing the STI material using ALD, CVD, or other suitable techniques.

[0291] In various embodiments, the method further includes forming transistor devices over the substrate and the trapezoidal STI structure.

[0292] In various embodiments, the novel ladder-shaped STI structure and method disclosed herein can provide sufficient isolation and higher operating speeds for HV applications. While the foregoing ladder-shaped STI features are described with reference to their use in LDMOS devices, the ladder-shaped STI features are not limited to such applications. The ladder-shaped STI functionality can be used in other applications, such as CMOS transistors requiring higher operating voltages (e.g., driver ICs, power management integrated circuits (PMICs), sensors).

[0293] Figures 10A to 10E This is a schematic cross-sectional view of an exemplary LDMOS device including trapezoidal STI features according to some embodiments. Figure 10A An exemplary HV asymmetric NMOS device 1000 incorporating a trapezoidal STI feature 1002 is depicted. Figure 10B An exemplary HV-symmetric NMOS device 1010 comprising a first trapezoidal STI feature 1012 and a second trapezoidal STI feature 1014 is depicted. Figure 10C An exemplary HV asymmetric PMOS device 1020 incorporating a trapezoidal STI feature 1022 is depicted. Figure 10D An exemplary HV-symmetric PMOS device 1030 is shown, which includes a first trapezoidal STI feature 1032 and a second trapezoidal STI feature 1034. Figure 10E An exemplary HV-isolated NMOS device 1040 incorporating a trapezoidal STI feature 1042 is described. The various features and techniques described herein can be implemented in any of these and other devices.

[0294] In some aspects, the technology described herein relates to a semiconductor structure including a source feature and a drain feature disposed in a substrate; a gate structure disposed on the substrate and located between the source feature and the drain feature; and a first trapezoidal shallow trench isolation (STI) feature disposed in the substrate, which is at least partially located below the gate structure in a channel region between the source feature and the drain feature, the first trapezoidal shallow trench isolation feature including multiple portions of different depths, including a first depth portion and a second depth portion.

[0295] In some respects, the techniques described herein relate to a semiconductor structure in which the source features include a first doped region and the drain features include a second doped region, and wherein both the first and second doped regions are of a first polarity type.

[0296] In some respects, the technology described herein relates to a semiconductor structure in which the first polarity type is positive polarity.

[0297] In some respects, the technology described herein relates to a semiconductor structure in which the first polarity type is negative polarity.

[0298] In some respects, the technology described herein relates to a semiconductor structure in which a channel region has a drain side spanning between a second doped region and a region in the substrate located below the middle position of the gate structure in the lateral direction, and a first trapezoidal structure STI feature is disposed on the drain side of the channel region.

[0299] In some respects, the technology described herein relates to a semiconductor structure in which a first depth portion has a first depth, a second depth portion has a second depth, and the first depth is greater than the second depth.

[0300] In some respects, the techniques described herein relate to a semiconductor structure in which the ratio of a first depth to a second depth is about 1.2 to 1 to about 3 to 1.

[0301] In some aspects, the technology described herein relates to a semiconductor structure, further comprising a single-depth shallow trench isolation feature disposed on a substrate, at least partially located below a second gate structure in a second channel region between a second source feature and a second drain feature, wherein: the single-depth shallow trench isolation feature has a shallow trench isolation depth and a shallow trench isolation width; the first depth portion has a first depth equal to the shallow trench isolation depth; the second depth portion has a second depth less than the shallow trench isolation depth; and the first trapezoidal shallow trench isolation feature has a width equal to the shallow trench isolation width.

[0302] In some aspects, the technology described herein relates to a semiconductor structure, further comprising a single-depth shallow trench isolation feature disposed on a substrate, at least partially located below a second gate structure in a second channel region between a second source feature and a second drain feature, wherein: the single-depth shallow trench isolation feature has a shallow trench isolation depth and a shallow trench isolation width; the first depth portion has a first depth greater than the shallow trench isolation depth; the second depth portion has a second depth less than the shallow trench isolation depth; and the first trapezoidal shallow trench isolation feature has a width greater than the shallow trench isolation width.

[0303] In some aspects, the technology described herein relates to a semiconductor structure, further comprising a single-depth shallow trench isolation feature disposed on a substrate, at least partially located below a second gate structure in a second channel region between a second source feature and a second drain feature, wherein: the single-depth shallow trench isolation feature has a shallow trench isolation depth and a shallow trench isolation width; the first depth portion has a first depth less than the shallow trench isolation depth; the second depth portion has a second depth less than the shallow trench isolation depth; and the first trapezoidal shallow trench isolation feature has a width greater than the shallow trench isolation width.

[0304] In some respects, the technology described herein relates to a semiconductor structure in which: a substrate includes a high-voltage n-well (HVNW) and a high-voltage p-well (HVPW); a source feature is disposed in the HVNW; and a drain feature and a first trapezoidal STI feature are both disposed in the HVPW.

[0305] In some respects, the technology described herein relates to a semiconductor structure in which: a substrate includes a high-voltage n-well (HVNW) and a high-voltage p-well (HVPW); a source feature is disposed in the HVPW; and a drain feature and a first trapezoidal STI feature are both disposed in the HVNW.

[0306] In some aspects, the technology described herein relates to a semiconductor structure, further comprising a second trapezoidal shallow trench isolation feature disposed in the substrate, at least partially located below the gate structure in the channel region between the source feature and the drain feature, the second trapezoidal shallow trench isolation feature comprising a plurality of portions of different depths equal to the plurality of portions of different depths in the first trapezoidal shallow trench isolation feature, wherein: the channel region has a drain side spanning between the first doped region and a region in the substrate located in a lateral direction below a midpoint of the gate structure; and the second trapezoidal shallow trench isolation feature is disposed on the drain side of the channel region.

[0307] In some respects, the technology described herein relates to a semiconductor structure in which: a substrate includes a first high-voltage n-well (HVNW), a second HVNW, a first high-voltage p-well (HVPW), and a second HVPW; a drain feature and a first trapezoidal STI feature are disposed in the first HVNW; and a source feature and a second trapezoidal STI feature are disposed in the second HVNW.

[0308] In some respects, the technology described herein relates to a semiconductor structure in which: a substrate includes a first high-voltage n-well (HVNW), a second HVNW, a first high-voltage p-well (HVPW), and a second HVPW; a drain feature and a first trapezoidal STI feature are disposed in the first HVPW; and a source feature and a second trapezoidal STI feature are disposed in the second HVPW.

[0309] In some respects, the technology described herein relates to a semiconductor structure in which a first depth portion has a first depth, a second depth portion has a second depth, the first depth is greater than the second depth, and the first depth portion is located to the right of the second depth portion.

[0310] In some respects, the technology described herein relates to a semiconductor structure in which a first depth portion has a first depth, a second depth portion has a second depth, the first depth is greater than the second depth, and the first depth portion is located to the left of the second depth portion.

[0311] In some respects, the techniques described herein relate to a semiconductor structure in which the ratio of a first depth to a second depth is about 1.2 to 1 to about 3 to 1.

[0312] In some respects, the technology described herein relates to a semiconductor structure that further includes a third depth portion, wherein the first depth portion has a first depth, the second depth portion has a second depth, the third depth portion has a depth equal to the second depth, the first depth is greater than the second depth, and the first depth portion is located between the second depth portion and the third depth portion.

[0313] In some respects, the technology described herein relates to a semiconductor structure that further includes a third depth portion, wherein the first depth portion has a first depth, the second depth portion has a second depth, the third depth portion has a third depth, the first depth is greater than the second depth, the second depth is greater than the third depth, the first depth portion is located to the left of the second depth portion, and the second depth portion is located to the left of the third depth portion.

[0314] In some respects, the technology described herein relates to a semiconductor structure that further includes a third depth portion, wherein the first depth portion has a first depth, the second depth portion has a second depth, the third depth portion has a third depth, the first depth is greater than the second depth, the second depth is greater than the third depth, the first depth portion is located to the right of the second depth portion, and the second depth portion is located to the right of the third depth portion.

[0315] In some respects, the technology described herein relates to a semiconductor structure in which the first trapezoidal shallow trench isolation feature further includes a top surface, a curved first wall between the top surface and a curved first bottom surface, a curved second wall between the curved first bottom surface and a curved second bottom surface, and a curved third wall between the curved second bottom surface and the top surface.

[0316] In some aspects, the technology described herein relates to a manufacturing method comprising: identifying a first trapezoidal shallow trench isolation feature region in a substrate, wherein the first trapezoidal shallow trench isolation feature region includes at least a first depth portion region and a second depth portion region; forming a charged injection in the first depth portion region; removing a first layer of substrate material from the first depth portion region; removing a second layer of substrate material from the first depth portion region and the second depth portion region, thereby forming a trapezoidal shallow trench isolation recess; and filling the trapezoidal shallow trench isolation recess with a shallow trench isolation material, thereby forming a trapezoidal shallow trench isolation structure having a plurality of different depth portions, including a first depth portion and a second depth portion.

[0317] In some respects, the techniques described herein relate to a manufacturing method in which a charged implantation is formed in a first depth portion, comprising doping of a first depth portion region.

[0318] In some respects, the technology described herein relates to a manufacturing method in which forming the charged implantation in the first depth region includes doping the first depth region with a negatively charged implantation.

[0319] In some respects, the technology described herein relates to a manufacturing method in which removing the first layer of substrate material from the first depth region includes selectively etching the substrate using an etchant that is selective to the charge injection.

[0320] In some respects, the technology described herein relates to a manufacturing method in which removing the second layer substrate material from the first depth portion region and the second depth portion region includes performing a dry etching operation on the first trapezoidal shallow trench isolation feature region.

[0321] In some respects, the techniques described herein relate to a manufacturing method that further includes forming a transistor device over a substrate and a trapezoidal STI structure.

[0322] In some aspects, the technology described herein relates to a manufacturing method in which a trapezoidal shallow trench isolation structure includes a first external angle between a top surface of the trapezoidal shallow trench isolation structure and a first wall of the trapezoidal shallow trench isolation structure, a second external angle between a bottom surface of the trapezoidal shallow trench isolation structure in a second depth region and a third external angle between the top surface of the trapezoidal shallow trench isolation structure and a second wall of the trapezoidal shallow trench isolation structure, and wherein a size of the first external angle is equal to a size of the third external angle, and a size of the second external angle is less than the size of the first external angle and the size of the third external angle.

[0323] In some aspects, the technology described herein relates to a manufacturing method in which a trapezoidal shallow trench isolation structure includes a first interior angle between a first wall of the trapezoidal shallow trench isolation structure and a bottom surface of a second depth portion region of the trapezoidal shallow trench isolation structure, a second interior angle between a bottom surface of the first depth portion region and a third wall of the trapezoidal shallow trench isolation structure, and a third interior angle between the bottom surface of the first depth portion region and a second wall of the trapezoidal shallow trench isolation structure, wherein a size of the second interior angle is equal to a size of the third interior angle, and a size of the first interior angle is greater than the size of the second interior angle and the size of the third interior angle.

[0324] In some aspects, the technology described herein relates to a semiconductor structure including a substrate, source and drain features, a channel region, a gate structure, and a trapezoidal shallow trench isolation feature. The source and drain features are disposed in the substrate. The channel region is disposed in the substrate and located between the source and drain features. The gate structure is disposed above the channel region. The trapezoidal shallow trench isolation feature is located in the channel region. The trapezoidal shallow trench isolation feature includes multiple portions of different depths, including a first depth portion and a second depth portion, wherein the first depth portion has a first depth, the second depth portion has a second depth, and the first depth is greater than the second depth, wherein the ratio of the first depth to the second depth is between 1.2:1 and 3:1.

[0325] In some aspects, the technology described herein relates to a semiconductor structure comprising: a source feature including a first doped region and a drain feature including a second doped region disposed in a substrate; a channel region disposed in the substrate and located between the source feature and the drain feature; a gate structure disposed above the channel region, wherein the channel region has a drain side that spans between the second doped region and a region in the substrate located in a lateral direction below a midpoint of the gate structure; and a first trapezoidal shallow trench isolation feature disposed on the drain side of the channel region, the first trapezoidal shallow trench isolation feature including multiple portions of different depths, including a first depth portion and a second depth portion.

[0326] In some respects, the techniques described herein relate to a semiconductor structure that includes a laterally-diffused metal-oxide semiconductor (LDMOS) device.

[0327] In some aspects, the technology described herein relates to a semiconductor structure in which: a substrate includes a well region having a first conductivity type and a well region having a second conductivity type; a source feature is disposed in the well region having the first conductivity type; and a drain feature and a first trapezoidal STI feature are both disposed in the well region having the second conductivity type.

[0328] In some aspects, the technology described herein relates to a semiconductor structure, further comprising: a first outer angle between a top surface of the first trapezoidal shallow trench isolation feature and a first wall of the first trapezoidal shallow trench isolation feature; a second outer angle between a bottom surface of the second depth portion region and a third wall of the first trapezoidal shallow trench isolation feature; and a third outer angle between the top surface of the first trapezoidal shallow trench isolation feature and a second wall of the first trapezoidal shallow trench isolation feature, wherein a size of the first outer angle is equal to a size of the third outer angle, and a size of the second outer angle is smaller than the size of the first outer angle and the size of the third outer angle; the first wall of the first trapezoidal shallow trench isolation feature and the second wall of the first trapezoidal shallow trench isolation feature; ... the first outer angle between a top surface of the first trapezoidal shallow trench isolation feature and a first wall of the first trapezoidal shallow trench isolation feature; a second outer angle between a bottom surface of the second depth portion region and a third wall of the first trapezoidal shallow trench isolation feature; a third outer angle between the top surface of the first trapezoidal shallow trench isolation feature and a second wall of the first trapezoidal shallow trench isolation feature; a third outer angle between the top surface of the first trapezoidal shallow trench isolation feature and a second wall of the first trapezoidal shallow trench isolation feature; a third outer angle between A first interior angle between the bottom surfaces of the second depth region of a trapezoidal shallow trench isolation feature, a second interior angle between the bottom surface of the first depth region and the third wall of the first trapezoidal shallow trench isolation feature, and a third interior angle between the bottom surface of the first depth region and the second wall of the first trapezoidal shallow trench isolation feature, wherein a size of the second interior angle is equal to a size of the third interior angle, and a size of the first interior angle is greater than the size of the second interior angle and the size of the third interior angle; and a size of each of the first interior angle, the second interior angle, the third interior angle, the first exterior angle, the second exterior angle, and the third exterior angle is greater than (>) 90° and less than (<) 180°.

[0329] In some aspects, the technology described herein relates to a semiconductor structure, further comprising a second trapezoidal shallow trench isolation feature disposed in the substrate, at least partially located below the gate structure in the channel region between the source feature and the drain feature, the second trapezoidal shallow trench isolation feature comprising a plurality of portions of different depths equal to the plurality of portions of different depths in the first trapezoidal shallow trench isolation feature, wherein: the channel region has a drain side spanning between the first doped region and a region in the substrate located in a lateral direction below a midpoint of the gate structure; and the second trapezoidal shallow trench isolation feature is disposed on the drain side of the channel region.

[0330] In some aspects, the technology described herein relates to a semiconductor structure in which: a substrate includes a first well region having a first conductivity type, a second well region having a first conductivity type, a first well region having a second conductivity type, and a second well region having a second conductivity type; a drain feature and a first trapezoidal STI feature are disposed in the first well region having the first conductivity type; and a source feature and a second trapezoidal STI feature are disposed in the second well region having the second conductivity type.

[0331] While the foregoing detailed description has set forth at least one exemplary embodiment, it should be understood that many variations are possible. It should also be understood that these exemplary embodiments are not intended to limit the scope, applicability, or configuration of this disclosure in any way. Rather, the foregoing detailed description is intended to provide those skilled in the art with a convenient blueprint for embodying the exemplary embodiments of this disclosure, and it should be understood that the function and configuration of the elements mentioned in the exemplary embodiments may be changed without departing from the scope of this disclosure as described in the claims.

Claims

1. A semiconductor structure, characterized in that, include: A source feature and a drain feature are disposed in a substrate; A gate structure is disposed on the substrate and located between the source feature and the drain feature; as well as A first trapezoidal shallow trench isolation feature is disposed in the substrate and is at least partially located below the gate structure in a channel region between the source feature and the drain feature. The first trapezoidal shallow trench isolation feature includes multiple portions of different depths, including a first depth portion and a second depth portion.

2. The semiconductor structure as described in claim 1, characterized in that, The channel region has a drain side that spans between a doped region of the drain feature and a region in the substrate located in a lateral direction below a middle position of the gate structure.

3. The semiconductor structure as described in claim 1 or 2, characterized in that, It also includes a third depth portion, wherein the first depth portion has a first depth, the second depth portion has a second depth, the third depth portion has a depth equal to the second depth, the first depth is greater than the second depth, and the first depth portion is located between the second depth portion and the third depth portion.

4. The semiconductor structure as described in claim 1 or 2, characterized in that, It also includes a third depth portion, wherein the first depth portion has a first depth, the second depth portion has a second depth, the third depth portion has a third depth, the first depth is greater than the second depth, the second depth is greater than the third depth, the first depth portion is located to the left of the second depth portion, and the second depth portion is located to the left of the third depth portion.

5. The semiconductor structure as described in claim 1 or 2, characterized in that, The first trapezoidal shallow trench isolation feature further includes a top surface, a curved first wall located between the top surface and a curved first bottom surface, a curved second wall located between the curved first bottom surface and a curved second bottom surface, and a curved third wall located between the curved second bottom surface and the top surface.

6. A semiconductor structure, characterized in that, include: A source feature and a drain feature are disposed in a substrate; A channel region is disposed in the substrate and located between the source feature and the drain feature; A gate structure is disposed on the channel region; as well as A trapezoidal shallow trench isolation feature is located in the channel region. The trapezoidal shallow trench isolation feature includes multiple parts of different depths, including a first depth part and a second depth part, wherein the first depth part has a first depth, the second depth part has a second depth, and the first depth is greater than the second depth, wherein the ratio of the first depth to the second depth is 1.2:1 to 3:

1.

7. A semiconductor structure, characterized in that, include: A source feature including a first doped region and a drain feature including a second doped region are disposed in a substrate; A channel region is disposed in the substrate and located between the source feature and the drain feature; A gate structure is disposed on the channel region, wherein the channel region has a drain side that spans between the second doped region and a region in the substrate located in a lateral direction below a midpoint of the gate structure; and A first trapezoidal shallow trench isolation feature is disposed on the drain side of the channel region. The first trapezoidal shallow trench isolation feature includes multiple parts of different depths, including a first depth part and a second depth part.

8. The semiconductor structure as described in claim 7, characterized in that, It also includes a single-depth shallow trench isolation feature disposed in the substrate, which is at least partially located below a second gate structure in a second channel region between a second source feature and a second drain feature, wherein: The single-depth shallow trench isolation feature has a shallow trench isolation depth and a shallow trench isolation width; The first depth portion has a first depth, which is equal to the shallow trench isolation depth; The second depth portion has a second depth, which is less than the shallow trench isolation depth; and The first trapezoidal shallow trench isolation feature has a width equal to the width of the shallow trench isolation.

9. The semiconductor structure as described in claim 7 or 8, characterized in that, Also includes: A first outer angle between a top surface of the first trapezoidal shallow trench isolation feature and a first wall of the first trapezoidal shallow trench isolation feature, a second outer angle between a bottom surface of the second depth portion and a third wall of the first trapezoidal shallow trench isolation feature, and a third outer angle between the top surface of the first trapezoidal shallow trench isolation feature and a second wall of the first trapezoidal shallow trench isolation feature, wherein a size of the first outer angle is equal to a size of the third outer angle, and a size of the second outer angle is smaller than the size of the first outer angle and the size of the third outer angle; A first interior angle between the first wall of the first trapezoidal shallow trench isolation feature and the bottom surface of the second depth portion of the first trapezoidal shallow trench isolation feature; a second interior angle between the bottom surface of the first depth portion and the third wall of the first trapezoidal shallow trench isolation feature; and a third interior angle between the bottom surface of the first depth portion and the second wall of the first trapezoidal shallow trench isolation feature, wherein a size of the second interior angle is equal to a size of the third interior angle, and a size of the first interior angle is greater than both the size of the second interior angle and the size of the third interior angle; and The size of each of the first interior angle, the second interior angle, the third interior angle, the first exterior angle, the second exterior angle, and the third exterior angle is greater than 90° and less than 180°.

10. The semiconductor structure as described in claim 7 or 8, characterized in that, The substrate also includes a second trapezoidal shallow trench isolation feature disposed therein, which is at least partially located below the gate structure in the channel region between the source feature and the drain feature. The second trapezoidal shallow trench isolation feature includes multiple portions of different depths, which are equal to the multiple portions of different depths in the first trapezoidal shallow trench isolation feature, wherein: The channel region has the drain side, which spans between the first doped region and the region in the substrate located in a lateral direction below the intermediate position of the gate structure; and The second trapezoidal shallow trench isolation feature is disposed on the drain side of the channel region.

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