Semiconductor device and nanostructure field effect transistor

Abstract

Some embodiments of the present disclosure provide a semiconductor device and a nanostructure field effect transistor. The semiconductor device includes a substrate, a source / drain region, a relaxation layer between the substrate and the source / drain region, and a silicon through via electrically connecting the source / drain region to a backside of the semiconductor device, wherein the relaxation layer has an etch selectivity to silicon between 1.01 and 100.00, and the silicon through via passes through the substrate, the relaxation layer, and a portion of the source / drain region.

Description

Technical Field

[0001] This disclosure relates to semiconductor devices, and more particularly to semiconductor devices of the nanostructure field-effect transistor type. Background Technology

[0002] Semiconductor devices are used in a variety of electronic applications, such as personal computers, mobile phones, digital cameras, and other electronic devices. The fabrication of semiconductor devices typically involves depositing insulating or dielectric layers, conductive layers, and semiconductor layers sequentially on a semiconductor substrate, and using lithography to pattern the multiple material layers to form circuit components and elements on the semiconductor substrate.

[0003] The semiconductor industry continues to improve the integration density of various electronic components (such as transistors, diodes, resistors, capacitors, etc.) by continuously shrinking the minimum feature size, thereby allowing more components to be integrated into a given area. However, as the minimum feature size shrinks, additional problems also arise that need to be addressed. Utility Model Content

[0004] According to some embodiments of the present disclosure, a semiconductor device includes a substrate, a source / drain region, a mitigation layer between the substrate and the source / drain region, and a silicon via electrically connecting the source / drain region to the back side of the semiconductor device, wherein the etch selectivity of the mitigation layer relative to silicon is between 1.01 and 100.00, and the silicon via passes through the substrate, the mitigation layer, and a portion of the source / drain region.

[0005] According to some embodiments of this disclosure, a semiconductor device includes a substrate, a source / drain region, a mitigation layer located between the substrate and the source / drain region, a dielectric layer located between the mitigation layer and the source / drain region, and a silicon via through gaps and a portion of the source / drain region in the substrate, the mitigation layer, and the dielectric layer, wherein the etch selectivity of the mitigation layer relative to silicon is between 1.01 and 100.00, and the ratio of the thickness of the dielectric layer to the thickness of the mitigation layer is between 1.0 and 20.0.

[0006] According to some embodiments of this disclosure, a nanostructure field-effect transistor includes a substrate having fins, an isolation region above the substrate and along opposite sides of the fins, a plurality of nanostructures above the fins, source / drain regions adjacent to the nanostructures, a gate electrode above the nanostructures, a mitigation layer between the substrate and the source / drain regions with an etch selectivity relative to silicon between 1.01 and 100.00, and silicon vias through the substrate and the mitigation layer and electrically contacting the source / drain regions. Attached Figure Description

[0007] The various aspects of this disclosure can be best understood from the following detailed description when read in conjunction with the accompanying drawings. It should be noted that, in accordance with standard industrial methods, the various features are not drawn to scale. In fact, the dimensions of the various features may be arbitrarily increased or decreased for clarity of discussion.

[0008] Figure 1 Three-dimensional views of example nanostructured field-effect transistors are illustrated according to some embodiments;

[0009] Figure 2 , Figure 3 , Figure 4 , Figure 5 , Figure 6A , Figure 6B , Figure 7A , Figure 7B , Figure 8A , Figure 8B , Figure 9A , Figure 9B , Figure 9C , Figure 9D , Figure 9E , Figure 9F , Figure 10A , Figure 10B , Figure 11A , Figure 11B , Figure 11C and Figure 12A Cross-sectional views of intermediate stages in the fabrication of nanostructured field-effect transistors are illustrated according to some embodiments;

[0010] Figure 12B The outline of the gradual change in impurity concentration is illustrated according to some embodiments;

[0011] Figure 12C , Figure 12D , Figure 12E , Figure 12F , Figure 12G , Figure 13A , Figure 13B , Figure 13C , Figure 13D , Figure 14A , Figure 14B , Figure 14C , Figure 15A , Figure 15B , Figure 16A , Figure 16B , Figure 17A , Figure 17B , Figure 18A , Figure 18B , Figure 19A , Figure 19B , Figure 19C , Figure 20A , Figure 20B , Figure 20C , Figure 21A , Figure 21B and Figure 21C Cross-sectional views of intermediate stages in the fabrication of nanostructured field-effect transistors are illustrated according to some embodiments;

[0012] Figure 22A , Figure 22B and Figure 22C Cross-sectional views of nanostructured field-effect transistors are shown according to some embodiments;

[0013] Figure 23A and Figure 23B Cross-sectional views of intermediate stages in the fabrication of nanostructured field-effect transistors are illustrated according to some embodiments;

[0014] Figure 24 Cross-sectional views of nanostructured field-effect transistors are shown according to some embodiments.

[0015] [Symbol Explanation]

[0016] 20: Separator line

[0017] 50:Substrate

[0018] 50N: n-type region

[0019] 50P:p-type area

[0020] 51, 51A, 51B, 51C: First semiconductor layer

[0021] 52, 52A, 52B, 52C: First nanostructure

[0022] 53, 53A, 53B, 53C: Second semiconductor layer

[0023] 54, 54A, 54B, 54C: Second nanostructures

[0024] 55: Nanostructures

[0025] 64: Multi-layer stacking

[0026] 66: Fins

[0027] 68: Shallow trench isolation area / isolation area

[0028] 69: First bottom layer

[0029] 70: Virtual Dielectric Layer

[0030] 71: Virtual gate dielectric

[0031] 72: Virtual Gate Layer

[0032] 73: Mitigation Layer

[0033] 74: Masking layer

[0034] 75: Dielectric layer

[0035] 76: Virtual Gate

[0036] 77: Gap

[0037] 78: Mask

[0038] 80: First spacer layer

[0039] 81: First spacer

[0040] 82: Second spacer layer

[0041] 83: Second spacer

[0042] 86: First Groove

[0043] 88: Sidewall Groove

[0044] 90: First internal spacer

[0045] 92: Source / Drain Region

[0046] 92A: First semiconductor material layer

[0047] 92B: Second semiconductor material layer

[0048] 92C: Third semiconductor material layer

[0049] 94: Contact Etching Stop Layer

[0050] 96: First interlayer dielectric layer

[0051] 98: Second groove

[0052] 100: Gate dielectric layer

[0053] 102, 102N, 102P: Gate electrode / gate structure

[0054] 104: Gate Mask

[0055] 106: Second interlayer dielectric layer

[0056] 108: Third Groove

[0057] 110: Silicide region

[0058] 112: Contact element

[0059] 114: Contact element

[0060] 116: Silicon Through-Hole

[0061] 122: Silicon via opening

[0062] AA′,BB′,CC′: Cross-sections

[0063] H r :high

[0064] L D :length

[0065] R r :depth

[0066] S D :width

[0067] S VB Horizontal width

[0068] T bottom :bottom

[0069] T D, T r, :thickness

[0070] T top :top

[0071] T VB :depth

[0072] θ D ,θ G ,θ r ,θ VB :angle

[0073] [B],[B p ],[B s ]:concentration Detailed Implementation

[0074] To achieve the different features of the mentioned subject matter, the following disclosure provides many different embodiments or examples. Specific examples of components, configurations, etc., are described below to simplify this disclosure. Of course, these are merely examples and not limiting. For example, in the following description, forming a first feature on or over a second feature may include embodiments where the first and second features are formed in direct contact, and may also include embodiments where an additional feature is formed between the first and second features such that the first and second features do not need to be in direct contact. Additionally, reference numerals and / or letters may be repeated in various examples. This repetition is for simplicity and clarity and does not in itself represent a relationship between the various embodiments and / or configurations discussed.

[0075] Furthermore, this document may use spatial relative terms such as “below,” “under,” “lower,” “above,” “upper,” etc., to facilitate the description of the relationship between one element or feature and another element or feature as shown in the figure. In addition to the orientations shown in the figure, spatial relative terms are intended to include different orientations of the device in use or operation. The device may be oriented in other ways (rotated 90 degrees or in other directions), and the spatial relative descriptive symbols used herein may be interpreted accordingly.

[0076] The following describes several embodiments using a die comprising a nanostructure field-effect transistor (nano-FET) as a specific example. This die employs a retarding layer to limit the penetration of through-silicon vias (TSVs) into the source / drain regions of the nanostructure FET, thereby maintaining superior source / drain efficiency and operational characteristics. However, these embodiments can be applied to other types of transistors (e.g., fin field-effect transistors, planar transistors, or the like) to replace or incorporate the nanostructure FET die.

[0077] According to some embodiments, Figure 1 This illustration depicts a three-dimensional view of an example nanostructured field-effect transistor (e.g., a nanowire field-effect transistor, a nanosheet field-effect transistor, or the like). The nanostructured field-effect transistor includes a nanostructure 55 (e.g., a nanosheet, nanowire, or the like) above fins 66 on a substrate 50 (e.g., a semiconductor substrate), wherein the nanostructure 55 serves as a channel region for the nanostructured field-effect transistor. The nanostructure 55 may include a p-type nanostructure, an n-type nanostructure, or a combination thereof. Isolation regions 68 are disposed between adjacent fins 66, wherein the fins 66 may protrude from between adjacent isolation regions 68 above the isolation regions 68. Although the isolation regions 68 are described / illustrated herein as being separate from the substrate 50, the term "substrate" may refer to the semiconductor substrate itself or a combination of the semiconductor substrate and the isolation regions. Furthermore, although the bottom of the fins 66 is illustrated as being a single, continuous material with respect to the substrate 50, the bottom of the fins 66 and / or the substrate 50 may include a single material or multiple materials. In this document, fin 66 represents the portion extending between adjacent isolation regions 68.

[0078] The gate dielectric layer 100 is located above the top surface of the fin 66 and along the top, sidewalls, and bottom surfaces of the nanostructure 55. The gate electrode 102 is located above the gate dielectric layer 100. Epitaxial source / drain regions 92 are disposed on the fin 66 and located on opposite sides of the gate dielectric layer 100 and the gate electrode 102. Depending on the context, the source / drain regions 92 may represent a source or drain individually or collectively.

[0079] Figure 1 Further illustrations are provided for the reference cross sections used in the following figures. Cross section AA′ is along the longitudinal axis of the gate electrode 102, and in a direction, for example, perpendicular to the current direction between the epitaxial source / drain regions 92 of the nanostructured field-effect transistor. Cross section BB′ is perpendicular to cross section AA′, parallel to the longitudinal axis of the fin 66 of the nanostructured field-effect transistor, and in, for example, the current direction between the epitaxial source / drain regions 92 of the nanostructured field-effect transistor. Cross section CC′ is parallel to cross section AA′ and extends through the epitaxial source / drain regions of the nanostructured field-effect transistor. For clarity, the following figures will refer to these reference cross sections.

[0080] Some embodiments discussed herein are based on the use of a gate-last process to form nanostructured field-effect transistors. In other embodiments, a gate-first process may be used. Additionally, some embodiments may be considered for use with planar devices, such as planar field-effect transistors or fin field-effect transistors.

[0081] According to some embodiments, Figures 2 to 24 This is a cross-sectional view of an intermediate stage in the fabrication of nanostructured field-effect transistors. Figures 2 to 5 , Figure 6A , Figure 14A , Figure 15A , Figure 16A , Figure 17A , Figure 18A , Figure 19A , Figure 20A , Figure 21A and Figure 22A Draw Figure 1 The reference section AA′ in the diagram. Figure 6B , Figure 7B , Figure 8B , Figures 9B to 9F , Figure 10B , Figure 11B , Figure 11C , Figure 12A , Figures 12C to 12G , Figure 13B , Figure 13D , Figure 14B , Figure 15B , Figure 16B , Figure 17B , Figure 18B , Figure 19B , Figure 20B , Figure 21B ,and Figure 22B Draw Figure 1 The reference section BB′ in the diagram. Figure 7A , Figure 8A , Figure 9A , Figure 10A , Figure 11A , Figure 13A , Figure 13C , Figure 14C , Figure 19C , Figure 20C , Figure 21C and Figure 22C Draw Figure 1 The reference section CC′ in the diagram.

[0082] exist Figure 2 In this embodiment, a substrate 50 is provided. The substrate 50 may be a semiconductor substrate, such as a bulk semiconductor, a semiconductor-on-insulator (SOI) substrate, or the like, wherein the substrate 50 may be doped (e.g., having p-type or n-type dopants) or undoped. The substrate 50 may be a wafer, such as a silicon wafer. Generally, a semiconductor-on-insulator substrate has a layer of semiconductor material formed on an insulating layer. The insulating layer may be, for example, a buried oxide (BOX) layer, a silicon oxide layer, or the like. The insulating layer is provided on a substrate, typically a silicon or glass substrate. Other substrates may also be used, such as multilayer or gradient substrates. In some embodiments, the semiconductor material of the substrate 50 may include silicon, germanium, compound semiconductors (including silicon carbide, gallium arsenide, gallium phosphide, indium phosphide, indium arsenide, and / or indium antimonide), alloy semiconductors (including silicon germanium, gallium arsenide phosphide, aluminum indium arsenide, aluminum gallium arsenide, gallium indium arsenide, gallium phosphide, and / or gallium arsenide phosphide), or combinations thereof.

[0083] The substrate 50 has an n-type region 50N and a p-type region 50P. The n-type region 50N can be used to form an n-type device, such as an n-type metal oxide semiconductor (NMOS) transistor, exemplified by an n-type nanostructure field-effect transistor, and the p-type region 50P can be used to form a p-type device, such as a p-type metal oxide semiconductor (PMOS) transistor, exemplified by a p-type nanostructure field-effect transistor. The n-type region 50N can be physically separated from the p-type region 50P (separated by dividing line 20 as shown in the figures), and any number of device features (e.g., other active devices, doped regions, isolation structures, etc.) can be disposed between the n-type region 50N and the p-type region 50P. Although one n-type region 50N and one p-type region 50P are shown in the figures, any number of n-type regions 50N and p-type regions 50P can be provided.

[0084] Furthermore, in Figure 2 In this process, a multilayer stack 64 is formed above the substrate 50. The multilayer stack 64 includes alternating layers of first semiconductor layers 51A to 51C (collectively referred to as first semiconductor layers 51) and second semiconductor layers 53A to 53C (collectively referred to as second semiconductor layers 53). For illustrative purposes and as discussed in detail below, the second semiconductor layer 53 in the p-type region 50P is removed, and the first semiconductor layer 51 is patterned to form the channel region of the nanostructured field-effect transistor in the p-type region 50P. Similarly, the first semiconductor layer 51 in the n-type region 50N is removed, and the second semiconductor layer 53 is patterned to form the channel region of the nanostructured field-effect transistor in the n-type region 50N. However, in some embodiments, the first semiconductor layer 51 in the p-type region 50P can be removed, and the second semiconductor layer 53 can be patterned to form the channel region of the nanostructured field-effect transistor in the p-type region 50P, and the second semiconductor layer 53 in the n-type region 50N can be removed, and the first semiconductor layer 51 in the n-type region 50N can be patterned to form the channel region of the nanostructured field-effect transistor.

[0085] In some other embodiments, the first semiconductor layer 51 in both the n-type region 50N and the p-type region 50P can be removed, and the second semiconductor layer 53 can be patterned to form the channel region of the nanostructured field-effect transistor. In other embodiments, the second semiconductor layer 53 in both the n-type region 50N and the p-type region 50P can be removed, and the first semiconductor layer 51 can be patterned to form the channel region of the nanostructured field-effect transistor. In such embodiments, the channel regions in both the n-type region 50N and the p-type region 50P can have the same material composition (e.g., silicon or other semiconductor materials) and can be formed simultaneously. Figure 22A , Figure 22B , Figure 22C and Figure 24 The channel regions in both the n-type region 50N and the p-type region 50P are illustrated, including structures produced by embodiments such as silicon.

[0086] For illustrative purposes, the multilayer stack 64 is illustrated as comprising three first semiconductor layers 51 and three second semiconductor layers 53. In some embodiments, the multilayer stack 64 may include any number of first semiconductor layers 51 and second semiconductor layers 53. The layers of the multilayer stack 64 may be epitaxially grown using processes such as chemical vapor deposition (CVD), atomic layer deposition (ALD), vapor phase epitaxy (VPE), molecular beam epitaxy (MBE), or similar techniques. In several embodiments, the first semiconductor layer 51 may be formed of a first semiconductor material suitable for p-type nanostructure field-effect transistors, such as silicon germanium or the like, while the second semiconductor layer 53 may be formed of a second semiconductor material suitable for n-type nanostructure field-effect transistors, such as silicon, silicon carbide, or the like. For illustrative purposes, the multilayer stack 64 is illustrated as having a semiconductor layer suitable for p-type nanostructure field-effect transistors as the bottom layer. In some embodiments, the formed multilayer stack 64 may have a semiconductor layer suitable for n-type nanostructure field-effect transistors as the bottom layer.

[0087] The first semiconductor material and the second semiconductor material can be materials with high etch selectivity relative to each other. Therefore, in the n-type region 50N, the first semiconductor material of the first semiconductor layer 51 can be removed without significantly removing the second semiconductor material of the second semiconductor layer 53, allowing the second semiconductor layer 53 to be patterned to form the channel region of an n-type nanostructure field-effect transistor. Similarly, in the p-type region 50P, the second semiconductor material of the second semiconductor layer 53 can be removed without significantly removing the first semiconductor material of the first semiconductor layer 51, allowing the first semiconductor layer 51 to be patterned to form the channel region of a p-type nanostructure field-effect transistor.

[0088] Reference to Figure 3 According to some embodiments, fins 66 are formed in substrate 50, and nanostructures 55 are formed in multilayer stack 64. In some embodiments, the nanostructures 55 in multilayer stack 64 and the fins 66 in substrate 50 can be formed by etching trenches in multilayer stack 64 and substrate 50, respectively. Etching can be any acceptable etching process, such as reactive ion etching (RIE), neutral beam etching (NBE), or a combination thereof. Etching can be anisotropic. Etching multilayer stack 64 to form nanostructures 55 can further define first nanostructures 52A to 52C (collectively referred to as first nanostructure 52) from first semiconductor layer 51, and second nanostructures 54A to 54C (collectively referred to as second nanostructure 54) from second semiconductor layer 53. First nanostructure 52 and second nanostructure 54 can be further collectively referred to as nanostructure 55.

[0089] The fins 66 and nanostructures 55 can be patterned using any suitable method. For example, the patterned fins 66 and nanostructures 55 can be patterned using one or more photolithography processes, including dual-patterning or multi-patterning processes. Generally, dual-patterning or multi-patterning processes combine photolithography and self-alignment processes, thus allowing the created patterns to have, for example, a smaller spacing than that achievable using a single, direct photolithography process. For example, in one embodiment, a sacrificial layer is placed over a substrate, and the sacrificial layer is patterned using a photolithography process. Spacers are formed along the patterned sacrificial layer using a self-alignment process. The sacrificial layer is then removed, and the remaining spacers can then be used to pattern the fins 66.

[0090] For the purpose of explanation, Figure 3The fins 66 in the n-type region 50N and p-type region 50P are illustrated to have substantially equal widths. In some embodiments, the width of the fins 66 in the n-type region 50N may be greater than or less than the width of the fins 66 in the p-type region 50P. Furthermore, although the individual fins 66 and nanostructures 55 are illustrated to have a uniform width top to bottom, in other embodiments, the fins 66 and / or nanostructures 55 may have tapered sidewalls such that the width of the individual fins 66 and / or nanostructures 55 increases continuously in the direction toward the substrate 50. In such embodiments, the individual nanostructures 55 may have different widths and may have a trapezoidal shape.

[0091] exist Figure 4 Shallow trench isolation (STI) regions 68 are formed adjacent to the fins 66. The shallow trench isolation regions 68 can be formed by depositing an insulating material over the substrate 50, fins 66, and nanostructure 55, and between adjacent fins 66. The insulating material can be, for example, an oxide of silicon oxide, a nitride, the like, or a combination thereof, and can be formed by high-density plasma chemical vapor deposition (HDP-CVD), flowable chemical vapor deposition (FCVD), the like, or a combination thereof. Other insulating materials formed by any acceptable process can be used. In the illustrated embodiment, the insulating material is silicon oxide formed by a flowable chemical vapor deposition process. Once the insulating material is formed, an annealing process can be performed. In one embodiment, the insulating material is formed such that excess insulating material covers the nanostructure 55. Although the insulating material is illustrated as a single layer, some embodiments may use multiple layers. For example, in some embodiments, a liner (not specifically shown) can be formed first along the surfaces of the substrate 50, fins 66, and nanostructure 55. Next, a filling material, such as the one described above, can be formed on top of the liner.

[0092] Next, a removal process is applied to the insulating material to remove excess insulating material above the nanostructure 55. In some embodiments, a planarization process, such as chemical mechanical polishing (CMP), etch-back, a combination thereof, or similar, can be used. The planarization process exposes the nanostructure 55, so that after the planarization process is completed, the nanostructure 55 and the top surface of the insulating material are flush.

[0093] Next, the insulating material is recessed to form shallow trench isolation regions 68. The recessed insulating material causes the upper portions of the fins 66 in the n-type region 50N and p-type region 50P to protrude from between adjacent shallow trench isolation regions 68. Furthermore, the top surface of the shallow trench isolation region 68 can have a flat surface, a convex surface, a concave surface (e.g., dishing) as illustrated, or a combination thereof. The flat top surface, convex top surface, and / or concave top surface of the shallow trench isolation region 68 can be formed by appropriate etching. The recessed shallow trench isolation region 68 can be formed using an acceptable etching process, such as an etching process selective for the insulating material (e.g., etching the insulating material at a faster rate compared to the material of the fins 66 and the nanostructure 55). For example, oxides can be removed using, for example, diluted hydrofluoric acid (dHF).

[0094] The above regarding Figures 2 to 4 The process described is merely one example of how fins 66 and nanostructures 55 can be formed. In some embodiments, fins 66 and / or nanostructures 55 can be formed using masking and epitaxial growth processes. For example, a dielectric layer can be formed above the top surface of the substrate 50, and trenches can be etched through the dielectric layer to expose the underlying substrate 50. Epitaxial structures can be epitaxially grown in the trenches, and the dielectric layer can be recessed to allow the epitaxial structures to protrude from the dielectric layer to form fins 66 and / or nanostructures 55. The epitaxial structures can include the alternating semiconductor materials described above, such as a first semiconductor material and a second semiconductor material. In some embodiments of epitaxial growth of epitaxial structures, the epitaxial growth material can be in-situ doped during growth to exclude pre- and / or post-planting, but in-situ doping and planted doping can also be used together.

[0095] Additionally, for illustrative purposes only, one or more first semiconductor layers 51 (and the resulting one or more nanostructures 52) and one or more second semiconductor layers 53 (and the resulting one or more nanostructures 54) in the p-type region 50P and the n-type region 50N are illustrated and discussed as comprising the same material. Therefore, in some embodiments, one or both of the first semiconductor layer 51 and the second semiconductor layer 53 in the p-type region 50P and the n-type region 50N may be different materials or materials formed in a different order.

[0096] Furthermore, in Figure 4In this process, suitable traps (not specifically shown) can be formed in the fins 66, nanostructures 55, and / or shallow trench isolation regions 68. In embodiments with different trap types, different placement steps for the n-type region 50N and p-type region 50P can be implemented using photoresist or other masks (not specifically shown). For example, photoresist can be formed above the fins 66 and shallow trench isolation regions 68 in the n-type region 50N and p-type region 50P. The photoresist is patterned to expose the p-type region 50P. The photoresist can be formed using spin coating techniques and can be patterned using acceptable photolithography techniques. Once the photoresist is patterned, n-type impurities can be placed in the p-type region 50P, and the photoresist can act as a mask to substantially prevent the n-type impurities from being placed into the n-type region 50N. The n-type impurities can be phosphorus, arsenic, antimony, or the like, with a placement concentration of about 10 per cubic centimeter in the region. 13 atoms per centimeter cubed(atm / cm 3 )) to approximately 10 per cubic centimeter 14 Within the atomic range. After implantation, the photoresist can be removed using, for example, an acceptable ashing process.

[0097] After or before the placement of the p-type region 50P, a photoresist or other mask (not specifically shown) is formed over the fins 66, nanostructures 55, and shallow trench isolation regions 68 in the p-type region 50P and the n-type region 50N. The photoresist is patterned to expose the n-type region 50N. The photoresist can be formed using spin coating techniques and can be patterned using acceptable photolithography techniques. Once the photoresist is patterned, p-type impurity placement can be performed in the n-type region 50N, and the photoresist can act as a mask to substantially prevent p-type impurity placement into the p-type region 50P. The p-type impurity can be boron, boron fluoride, indium, or the like, with a placement concentration of approximately 10⁻¹¹ per cubic centimeter in the region. 13 Atoms to approximately 10 per cubic centimeter 14 Within the atomic range. After implantation, the photoresist can be removed using, for example, an acceptable ashing process.

[0098] After implanting the n-type region 50N and the p-type region 50P, annealing can be performed to repair implantation damage and activate the implanted p-type and / or n-type impurities. In some embodiments, the growth material of the epitaxial fins can be in-situ doped during growth to exclude implantation, but in-situ doping and implantation doping can also be used together.

[0099] exist Figure 5In this process, a virtual dielectric layer 70 is formed on the fin 66 and / or nanostructure 55. The virtual dielectric layer 70 may be, for example, silicon oxide, silicon nitride, a combination thereof, or the like, and may be deposited or thermally grown according to acceptable techniques. A virtual gate layer 72 is formed over the virtual dielectric layer 70, and a masking layer 74 is formed over the virtual gate layer 72. The virtual gate layer 72 may be deposited over the virtual dielectric layer 70 and planarized by, for example, chemical mechanical polishing. The masking layer 74 may be deposited over the virtual gate layer 72. The virtual gate layer 72 may be a conductive or non-conductive material and may be selected from the group including amorphous silicon, polysilicon, poly-SiGe, metal nitrides, metal silicides, metal oxides, and metals. The virtual gate layer 72 may be deposited by physical vapor deposition (PVD), chemical vapor deposition, sputtering deposition, or other techniques for depositing the selected material. The dummy gate layer 72 can be formed of other materials that have high etch selectivity relative to the etch isolation region. The mask layer 74 can include, for example, silicon nitride, silicon oxynitride, or the like. In this example, a single dummy gate layer 72 and a single mask layer 74 are formed across the n-type region 50N and the p-type region 50P. It is worth noting that, for illustrative purposes, the dummy dielectric layer 70 shown in the figure only covers the fin 66 and the nanostructure 55. In some embodiments, depositing the dummy dielectric layer 70 may cause the dummy dielectric layer 70 to cover the shallow trench isolation region 68, resulting in the dummy dielectric layer 70 extending between the dummy gate layer 72 and the shallow trench isolation region 68.

[0100] Figures 6A to 19C Several additional steps in manufacturing the apparatus of the embodiment are illustrated. Figure 6A , Figure 7A , Figure 8A , Figure 9A , Figure 10A , Figure 11A , Figure 13A , Figure 13C , Figure 14A , Figure 14C , Figure 15A , Figure 16A and Figure 19C Plot the characteristics of either the n-type region 50N or the p-type region 50P. Figure 6A and Figure 6B In this process, the mask layer 74 can be patterned using acceptable photolithography and etching techniques (see reference). Figure 5A mask 78 is formed. The pattern of the mask 78 can then be transferred to the dummy gate layer 72 and the dummy dielectric layer 70 to form a dummy gate 76 and a dummy gate dielectric 71, respectively. The dummy gate 76 covers individual channel regions of the fin 66. The pattern of the mask 78 can be used to physically separate each dummy gate 76 from adjacent dummy gates 76. The dummy gate 76 may also have a length direction substantially perpendicular to the length direction of the individual fin 66.

[0101] exist Figure 7A and Figure 7B In, respectively in Figure 6A and Figure 6B A first spacer layer 80 and a second spacer layer 82 are formed above the structure. The first spacer layer 80 and the second spacer layer 82 are then patterned to serve as spacers for forming self-aligned source / drain regions. Figure 7A and Figure 7B In this configuration, a first spacer layer 80 is formed on the top surface of the shallow trench isolation region 68; on the top surface and sidewalls of the fins 66, nanostructures 55, and mask 78; and on the sidewalls of the dummy gate 76 and dummy gate dielectric 71. A second spacer layer 82 is deposited over the first spacer layer 80. The first spacer layer 80 may be formed of silicon oxide, silicon nitride, silicon oxynitride, or the like, and may be formed using, for example, thermal oxidation, chemical vapor deposition, atomic layer deposition, or similar deposition techniques. The second spacer layer 82 may be formed of a material with a different etch rate than the material of the first spacer layer 80, such as silicon oxide, silicon nitride, silicon oxynitride, or the like, and may be deposited using chemical vapor deposition, atomic layer deposition, or the like.

[0102] After the formation of the first spacer layer 80 and before the formation of the second spacer layer 82, lightly doped source / drain (LDD) regions (not specifically shown) may be implanted. In embodiments with different device types, this is similar to the one above. Figure 4 The implantation discussed herein can be performed by forming a mask, such as a photoresist, over the n-type region 50N to expose the p-type region 50P, and implanting an appropriate type of impurity (e.g., p-type) into the exposed fins 66 and nanostructures 55 in the p-type region 50P. The mask can then be removed. Subsequently, a mask, such as a photoresist, can be formed over the p-type region 50P to expose the n-type region 50N, and implanting an appropriate type of impurity (e.g., n-type) into the exposed fins 66 and nanostructures 55 in the n-type region 50N. The mask can then be removed. The n-type impurity can be any of the aforementioned n-type impurities, and the p-type impurity can be any of the aforementioned p-type impurities. The lightly doped source / drain regions can have an impurity concentration of approximately 1 × 10⁻⁶ per cubic centimeter. 15 Atoms to approximately 1 × 10¹⁰ per cubic centimeter19 Within the atomic range, annealing can be used to repair implant damage and revitalize implant impurities.

[0103] exist Figure 8A and Figure 8B In the process, a first spacer layer 80 and a second spacer layer 82 are etched to form a first spacer 81 and a second spacer 83. As discussed in further detail below, the first spacer 81 and the second spacer 83 serve to self-align the subsequently formed source and drain regions, and to protect the sidewalls of the fin 66 and / or nanostructure 55 during subsequent processes. The first spacer layer 80 and the second spacer layer 82 can be etched using a suitable etching process, such as an isotropic etching process (e.g., wet etching process), anisotropic etching process (e.g., dry etching process), or the like. In some embodiments, the material of the second spacer layer 82 has an etch rate different from that of the material of the first spacer layer 80, so the first spacer layer 80 can serve as an etch stop layer when patterning the second spacer layer 82, and the second spacer layer 82 can serve as a mask when patterning the first spacer layer 80. For example, the second spacer layer 82 can be etched using an anisotropic etching process with the first spacer layer 80 as an etch stop layer, wherein the remaining portion of the second spacer layer 82 forms Figure 8A The second spacer 83 is illustrated in the diagram. Next, the second spacer 83 acts as a mask when the exposed portion of the first spacer layer 80 is etched, thereby forming... Figure 8A The first spacer 81 is shown in the middle.

[0104] like Figure 8A As illustrated, the first spacer 81 and the second spacer 83 are disposed on the sidewalls of the fin 66 and / or the nanostructure 55. Figure 8B As illustrated, in some embodiments, the second spacer layer 82 can be removed from above the first spacer layer 80 adjacent to the mask 78, dummy gate 76, and dummy gate dielectric 71, and the first spacer 81 is disposed on the sidewalls of the mask 78, dummy gate 76, and dummy gate dielectric 71. In other embodiments, a portion of the second spacer layer 82 may remain above the first spacer layer 80 adjacent to the mask 78, dummy gate 76, and dummy gate dielectric 71.

[0105] It should be noted that the above disclosure generally describes the process for forming the spacers and LDD regions. Other processes and sequences can be used. For example, fewer or additional spacers can be used, different step sequences can be used (e.g., the first spacer 81 can be patterned before depositing the second spacer layer 82), additional spacers and / or the like can be formed and removed. Furthermore, different structures and steps can be used to form n-type and p-type devices.

[0106] exist Figures 9A to 9CIn some embodiments, a first groove 86 is formed in the fin 66, nanostructure 55, and substrate 50. Epitaxial source / drain regions are subsequently formed in the first groove 86. The first groove 86 may extend through the first nanostructure 52 and the second nanostructure 54, and extend into the substrate 50. Figure 9A As illustrated, the top surface of the shallow trench isolation region 68 may be flush with the bottom surface of the first groove 86. In various embodiments, the fins 66 may be etched such that the bottom surface of the first groove 86 is located below the top surface of the shallow trench isolation region 68, or a similar structure. The first groove 86 can be formed by etching the fins 66, nanostructures 55, and substrate 50 using anisotropic etching processes, such as reactive ion etching, neutral particle beam etching, or the like. During the etching process for forming the first groove 86, the first spacer 81, the second spacer 83, and the mask 78 shield portions of the fins 66, nanostructures 55, and substrate 50. The individual layers of the nanostructures 55 and / or fins 66 may be etched using a single etching process or multiple etching processes. A timed etching process may be used to stop etching the first groove 86 after it has reached a desired depth.

[0107] like Figure 9B and Figure 9C As shown, different etching profiles can be formed in the substrate 50 according to various possible embodiments. Figure 9B The first groove 86 in the substrate 50 is shallowly etched, and a pure silicon substrate is used below the subsequently formed epitaxial source / drain region 92. Figure 9C The first groove 86 in the substrate 50 is deep and rounded, wherein, according to some embodiments, a subsequently formed mitigation layer 73 may be used below the epitaxial source / drain region 92.

[0108] According to some embodiments, Figures 9D to 9F Different profiles are shown, wherein the first bottom layer 69 in the first groove 86 of the substrate 50 has different growth surface profiles. Figures 9D to 9F In the embodiment where a deep first recess 86 is used in the illustrated substrate 50, a first bottom layer 69 is formed on top of the substrate 50 in the first recess 86 before the mitigation layer 73 is formed. In some embodiments, the first bottom layer 69 may be composed of silicon and germanium, wherein the ratio of silicon to germanium is described as Si 1-x Ge x And 0.0≤x≤0.4.

[0109] In some embodiments, a chemical vapor deposition (CVD) process with a temperature between 400°C and 750°C is used to form the first underlayer 69. In some embodiments, a pressure between 10 torr and 300 torr can be used during the CVD process. For example, all or part of the CVD process for growing the first underlayer 69 can be performed at a temperature between 520°C and 620°C and a pressure between 20 torr and 100 torr. Chemical precursors such as H2SiCl2 (DCS), SiH4, Si2H6, GeH4, GeCl4, HCl, and Cl2 can be used to control the composition of the first underlayer 69. However, any known method can be used to form the first underlayer 69.

[0110] According to some embodiments, Figure 9D This demonstrates the substantially flat surface profile of the first bottom layer 69. According to some embodiments, Figure 9E The arcuate surface profile of the first bottom layer 69 is drawn, wherein the edge of the arcuate surface profile closest to the edge of the first groove 86 is thinner. Figure 9F The second arcuate surface profile of the first bottom layer 69 is illustrated, wherein the edges of the second arcuate surface profile are deeper and the second arcuate surface profile becomes shallower towards the center of the first groove 86. For simplicity, unless necessary, further discussion and figures only show embodiments of shallow recesses in the substrate 50 (e.g., Figure 9B As shown in the figure, it does not have a first bottom layer 69. However, any of the following figures may additionally include elements like the first bottom layer 69.

[0111] exist Figure 10A and Figure 10B In the process of etching, a portion of the sidewalls of the material layer (e.g., the first nanostructure 52) formed of the first semiconductor material in the multilayer stack 64 exposed by the first groove 86 is etched to form a sidewall groove 88 in the n-type region 50N, and a portion of the sidewalls of the material layer (e.g., the second nanostructure 54) formed of the second semiconductor material in the multilayer stack 64 exposed by the first groove 86 is etched to form a sidewall groove 88 in the p-type region 50P. Although the sidewalls of the first nanostructure 52 and the second nanostructure 54 in the sidewall groove 88 are in Figure 10BThe first nanostructure 52 is depicted as a straight shape, but the sidewalls can be concave or convex. The sidewalls can be etched using an isotropic etching process, such as wet etching or similar. When the first nanostructure 52 is etched using an etchant selective for the first semiconductor material, such that the second nanostructure 54 in the n-type region 50N remains relatively unetched compared to the first nanostructure 52, a mask (not shown) can be used to protect the p-type region 50P. Similarly, when the second nanostructure 54 is etched using an etchant selective for the second semiconductor material, such that the first nanostructure 52 in the p-type region 50P remains relatively unetched compared to the second nanostructure 54, a mask (not shown) can be used to protect the n-type region 50N. In one embodiment where the first nanostructure 52 comprises, for example, SiGe and the second nanostructure 54 comprises, for example, Si or SiC, a dry etching process using tetramethylammonium hydroxide (TMAH), ammonium hydroxdie (NH4OH), or the like can be used to etch the sidewalls of the first nanostructure 52 in the n-type region 50N, and a wet or dry etching process using hydrogen fluoride, other fluorine-based etchants, or the like can be used to etch the sidewalls of the second nanostructure 54 in the p-type region 50P.

[0112] exist Figures 11A to 11C In the middle, a first internal spacer 90 is formed in the sidewall groove 88. The first internal spacer 90 can be formed by... Figure 10A and Figure 10B An internal spacer layer (not shown) is deposited above the illustrated structure. The first internal spacer 90 serves as an isolation feature between the subsequently formed source / drain regions and the gate structure. As discussed in further detail below, the source / drain regions will be formed in the first recess 86, and the first nanostructure 52 in the n-type region 50N and the second nanostructure 54 in the p-type region 50P will be replaced by the corresponding gate structures.

[0113] The internal spacer layer can be deposited using a conformal deposition process, such as chemical vapor deposition, atomic layer deposition, or the like. The internal spacer layer may comprise materials such as silicon nitride or silicon oxynitride, but any suitable material may be used, such as a low-k material having a dielectric constant value below about 3.5. The internal spacer layer can then be anisotropically etched to form a first internal spacer 90. Although the outer walls of the first internal spacer 90 are shown flush with the sidewalls of the second nanostructure 54 in the n-type region 50N and flush with the sidewalls of the first nanostructure 52 in the p-type region 50P, the outer walls of the first internal spacer 90 may extend beyond, respectively, the sidewalls of the second nanostructure 54 and / or the first nanostructure 52, or be recessed from, respectively, the sidewalls of the second nanostructure 54 and / or the first nanostructure 52.

[0114] Additionally, although the outer wall of the first internal spacer 90 is in Figure 11B The middle section is depicted as a straight shape, but the outer wall of the first internal spacer 90 can be concave or convex. As an example, Figure 11C The illustrated embodiment has a first nanostructure 52 with concave sidewalls, a first internal spacer 90 with concave outer sidewalls, and the first internal spacer 90 is recessed from the sidewalls of the second nanostructure 54 in the n-type region 50N. Figure 11C In the illustrated embodiment, in the p-type region 50P, the sidewalls of the second nanostructure 54 are concave, the outer sidewalls of the first internal spacer 90 are concave, and the first internal spacer 90 is recessed from the sidewall of the first nanostructure 52. The internal spacer layer can be etched using anisotropic etching processes, such as reactive ion etching, neutral particle beam etching, or the like. The first internal spacer 90 can be used to prevent subsequent etching processes (e.g., etching processes for forming gate structures) from damaging the subsequently formed source / drain regions (e.g., epitaxial source / drain regions 92, as referenced below). Figures 13A to 13C (As discussed).

[0115] According to some embodiments, a mitigation layer 73 may be formed. In some embodiments, when using back-side silicon via (TSV) contacts, the mitigation layer 73 can be used to slow down the back-side etch rate, increase etch control, and limit the penetration depth into the epitaxial source / drain region 92. Therefore, the penetration depth of the back-side silicon via into the source / drain region 92 can be limited, thereby improving the operation and efficiency of the associated device and limiting manufacturing defects. Specifically, by limiting the penetration of back-side etching into the epitaxial source / drain region 92, the overall size of the epitaxial source / drain region 92 increases, resulting in a more efficient epitaxial source / drain region 92 with low resistance, improved speed and performance, and a lower associated voltage drop. Therefore, energy losses, such as thermal losses, can be reduced, overall heat generation can be reduced, and lower energy requirements can be achieved. Therefore, increased manufacturing yield, lower manufacturing costs, increased manufacturing efficiency, and smaller device size and thickness can also be achieved.

[0116] In the first embodiment, as Figures 12A to 12E As shown, using a deep and flat etch profile in the substrate 50, a mitigation layer 73 is formed on top of the substrate 50 in the first recess 86. In some embodiments, the mitigation layer may be composed of silicon and germanium, wherein the ratio of silicon to germanium is described as Si... 1-x Ge xAnd 0.0 ≤ x ≤ 0.4. In some embodiments, the mitigation layer 73 may include impurities to further slow the etch rate of the substrate 50, while the impurities conform to the subsequently formed epitaxial source / drain regions 92. For example, according to some embodiments, for an n-type region 50N using p-type epitaxial source / drain regions 92, the mitigation layer 73 may be doped with boron. In some embodiments, the boron doping concentration ([B]) of the mitigation layer 73 may be between 1 × 10⁻⁶ per cubic centimeter. 20 Atoms up to 5 × 10⁵ per cubic centimeter 22 Between atoms.

[0117] In other embodiments, the mitigation layer 73 may be made of silicon boride (SiB), silicon carbide (SiC), or silicon oxide (SiO) doped with carbon, nitrogen, or oxygen. x It may be composed of silicon or germanium (SiGe), or other materials that can form a slowing layer as a substrate crystallization extension to maintain the integrity of the substrate in the final product. In addition, the etch selectivity of the slowing layer 73 relative to silicon should be between 1.01 and 100.00.

[0118] Several process parameters significantly affect the quality and properties of the formed mitigation layer 73. For example, when using chemical vapor deposition to form the mitigation layer 73, temperature control is advantageous because temperature affects the reaction rate and crystal structure formation; precise control within a small range is ideal for uniformity and desired properties. Gas flow rate and composition modulate the deposition rate and chemical reactions on the substrate surface, thus affecting layer thickness and composition. Pressure within the reaction chamber affects gas diffusion and surface interactions, thus influencing layer morphology and defect density. Furthermore, substrate orientation and surface preparation determine the nucleation site and crystal alignment, affecting epitaxial growth. Proper adjustment of these parameters can optimize epitaxial growth.

[0119] In some embodiments, a chemical vapor deposition (CVD) process with a temperature between 400°C and 750°C is used to form the mitigation layer 73. In some embodiments, a pressure between 10 Torr and 300 Torr can be used during the CVD process. For example, all or part of the CVD process used to grow the mitigation layer 73 can be between 520°C and 620°C and a pressure between 20 Torr and 100 Torr. Epitaxial growth performed within the above range can avoid phase transformation, resulting in a flatter surface and a higher quality growth layer. Chemical precursors such as H2SiCl2 (DCS), SiH4, Si2H6, GeH4, GeCl4, HCl, and Cl2 can be used to control the composition of the mitigation layer 73. For the mitigation layer 73 used in p-type epitaxial source / drain regions 92 (e.g., in n-type region 50N), dopant precursor gases including, for example, B2H6, BCl3, and Ga(CH3)3 can be used. For the mitigation layer 73 used in the n-type epitaxial source / drain region 92 (e.g., in the p-type region 50P), the dopant precursor gas may include PH3, AsH4, and the like. However, any known method can be used to form the mitigation layer 73.

[0120] In some embodiments, the dopant in the mitigation layer 73 may have a gradient concentration, wherein the gradient concentration varies with the thickness of the mitigation layer 73. According to some embodiments, Figure 12B An example boron doping concentration profile for mitigation layer 73 is illustrated. In the illustrated example concentration profile, the impurity in the p-type source / drain region is boron, and the boron concentration can be found at the boron baseline concentration [B]. s [baseline concentration] and boron peak concentration [B] p The peak concentration varies between different values. In some embodiments, the impurity peak concentration can be defined based on blank wafer data so that the impurity concentration does not affect the operation of the epitaxial source / drain region 92.

[0121] T r Indicates the location of relative concentration in the mitigation layer, with the left vertical axis located at the top of the mitigation layer (T). top ), and the right vertical axis is located at the bottom of the mitigation layer (T bottom According to some embodiments, the impurity concentration can be varied by controlling the flow rates of multiple precursor gases, for example, with the time of the chemical vapor deposition method for forming the mitigation layer 73. At a depth R of the mitigation layer 73... r When the boron peak concentration is reached [B] p ], where depth R r It is measured from the top of the mitigation layer 73. In some embodiments, the boron peak concentration [B] is... p The depth Rr The distance from the top surface of the mitigation layer 73 is between 1 nanometer and 15 nanometers. In some embodiments, the boron peak concentration [B p The location (depth R) r ) Distance to the bottom of the slowing layer (T) bottom The boron baseline concentration can be between 1 nanometer and 29 nanometers. In some embodiments, the boron baseline concentration [B] can be between 1 nanometer and 29 nanometers. s It can be between 1×10 per cubic centimeter. 20 Atoms up to 2 × 10 per cubic centimeter 22 Between atoms. In some embodiments, the boron peak concentration [B p It can be between 1×10 per cubic centimeter. 20 Atoms up to 5 × 10⁵ per cubic centimeter 22 Interatomic. Boron peak concentration [B] p [B] and baseline boron concentration s The ratio can be between 1.0 and 2.5.

[0122] like Figure 12C As shown, dielectric layer 75 can be further used to control the shape of portions of the back-side silicon through-hole etching into the source / drain region 92. In some embodiments, dielectric layer 75 can be silicon oxide, silicon nitride, silicon oxynitride, silicon carbide, or some other dielectric material that can resist selective etching of substrate 50. Dielectric layer 75 can be deposited on substrate 50 and mitigation layer 73, for example by spin coating, lamination, chemical vapor deposition, atomic layer deposition, physical vapor deposition, high-density plasma chemical vapor deposition, thermal oxidation, combinations of the above, and / or similar methods. However, any suitable materials and deposition processes can be used.

[0123] According to some embodiments, Figure 12D A patterned dielectric layer 75 is illustrated. In some embodiments, gaps 77 are formed in the dielectric layer 75 using a combination of photolithography and etching processes. For example, gaps 77 can be formed in a plasma etching process. Gap 77 can be formed in the dielectric layer 75 when the dielectric layer material is not easily affected by subsequent etching processes for the substrate 50, the mitigation layer 73, and the trenches in the epitaxial source / drain regions 92. Gap 77 can also be formed in the dielectric layer 75 when the dielectric layer 75 exhibits very high etch selectivity relative to silicon (e.g., etch selectivity greater than 100). The plasma etching process may include forming a patterned mask over the dielectric layer 75 and the substrate 50. The patterned mask may be a photomask deposited in a spin coating process and patterned using lithography (e.g., exposure and development) to define openings in the dielectric layer 75 that expose gaps 77. The etching process etches portions of the dielectric layer 75 through the patterns (e.g., openings) in the patterned mask.

[0124] In some embodiments, the etching process can be performed using plasma dry etching and / or reactive ion etching. For example, reactive ion etching can use reactive gases with low reactivity to the material of substrate 50, such as CF4, C4F8, CHF3, or CH3F, to preferentially etch through the dielectric layer 75. Etching can be controlled by varying the etching process time, among other process parameters. In some embodiments, wet etching can also be performed to repair any surface defects resulting from the dry etching process. In some embodiments, reactive ion etching uses argon-based plasma, oxygen-based plasma, nitrogen-based plasma, or the like. However, the gaps 77 in the dielectric layer 75 can be patterned using any suitable method.

[0125] According to some embodiments, Figure 12E yes Figure 12D The magnified portion of the n-type region 50N in the [image / structure]. In some embodiments, the thickness T of the mitigation layer 73 is [specified / determined]. r It can be between 1 nanometer and 30 nanometers (1 nanometer ≤ T). r ≤30 nm). In some embodiments, the bottommost part of the bottom gate electrode 102 is used as the reference plane, and the topmost part of the mitigation layer 73 can be located at a height H between -15 nm and +15 nm. r (-15 nanometers ≤ H) r ≤+15 nm). The height H of the mitigation layer 73 r Positive value (H) r A value >0 indicates that the top portion of the mitigation layer 73 is located above the top portion of the substrate 50. A positive height above the bottom portion of the bottom gate electrode can be used to increase design flexibility when a particular nanostructure field-effect transistor in a specific design implementation does not require or does not want all available channels. The height H of the mitigation layer 73 r Negative value (H) r <0) indicates that the top portion of the mitigation layer 73 is located below the top portion of the substrate 50. According to some embodiments, the thickness T of the dielectric layer 75... D It can be between 1 nanometer and 10 nanometers (1 nanometer ≤ T). D ≤10 nanometers). In some embodiments, the thickness T of dielectric layer 75 is... D and the thickness T of the mitigation layer 73 r The ratio can be between 1 and 20. In some embodiments, the gap 77 in the dielectric layer 75 is at the width S of the interface between the dielectric layer 75 and the mitigation layer 73. D It can be between 1 nanometer and 20 nanometers (1 nanometer ≤ S D ≤20 nanometers). In some embodiments, the length L of the dielectric layer 75 from the sidewall of the first groove 86 to the minimum portion of the gap 77 in the dielectric layer 75 is... D It can be between 1 nanometer and 10 nanometers (1 nanometer ≤ L)D ≤10 nanometers). In some embodiments, the width S of the gap 77 in the dielectric layer 75 D The length L of the dielectric layer 75 from the sidewall of the first groove 86 to the gap 77 in the minimum portion of the dielectric layer 75. D The ratio can be between 1 and 10. In some embodiments, the angle (θ) between the straight line perpendicular to the main plane of the substrate 50 and the angle of the etched sidewall of the dielectric layer 75 at the gap 77 is... G It can be between 10 degrees and 150 degrees (10°≤θ) D ≤150°).

[0126] Figure 12F and Figure 12G Other embodiments illustrating the formation of the mitigation layer 73 and dielectric layer 75 are shown, wherein substantially bent etching is used within the substrate. Similar to the embodiments described above... Figures 12A to 12E The process described forms a damping layer 73 and a dielectric layer 75, which are only substantially different in shape.

[0127] Figure 12F The illustrated embodiment shows a concave bottom of a first groove 86 formed in the substrate 50, causing the mitigation layer 73 and dielectric layer 75 to bend downwards. In some embodiments, the thickness T of the mitigation layer 73 is... r It can be between 1 nanometer and 30 nanometers (1 nanometer ≤ T). r ≤30 nm). In some embodiments, the top of the substrate 50 is used as a reference plane, and the top portion of the mitigation layer 73 can be located at a height H between -15 nm and +15 nm. r (-15 nanometers ≤ H) r ≤+15 nm). The height H of the mitigation layer 73 r Positive value (H) r >0) indicates that the top portion of the mitigation layer 73 is located above the top portion of the substrate 50. The height H of the mitigation layer 73 r Negative value (H) r <0) indicates that the topmost portion of the mitigation layer 73 is located below the topmost portion of the substrate 50. In some embodiments, the angle θ between a straight line perpendicular to the principal plane of the substrate 50 and the surface of the mitigation layer 73 closest to the wall of the first groove 86 is... r It can be between 5 degrees and 120 degrees (5°≤θ) r ≤120°).

[0128] According to some embodiments, the thickness T of the dielectric layer 75 is... D It can be between 1 nanometer and 10 nanometers (1 nanometer ≤ T). D ≤10 nanometers). In some embodiments, the gap 77 in the dielectric layer 75 is at the width S at the interface between the dielectric layer 75 and the mitigation layer 73. DIt can be between 1 nanometer and 20 nanometers (1 nanometer ≤ S D ≤20 nanometers). In some embodiments, the horizontal length L of the dielectric layer 75 from the sidewall of the first groove 86 to the minimum portion of the gap 77 in the dielectric layer 75 is... D It can be between 1 nanometer and 10 nanometers (1 nanometer ≤ L) D ≤10 nanometers). In some embodiments, the angle θ between a straight line perpendicular to the main plane of the substrate 50 and the tangent of the dielectric layer 75 at the sidewall interface of the first groove 86. D It can be between 5 degrees and 120 degrees (5°≤θ) D ≤120°). It should be understood that, Figure 12F Representing a possible cross-sectional view, the angle θ between a straight line perpendicular to the main plane of substrate 50 and the cross-section of dielectric layer 75 at the sidewall interface of the first groove 86. D Less than 90 degrees.

[0129] Figure 12G The illustrated embodiment shows a convex bottom forming a first groove 86 in the substrate 50, causing the mitigation layer 73 and dielectric layer 75 to bend upwards. In some embodiments, the thickness T of the mitigation layer 73 is... r It can be between 1 nanometer and 30 nanometers (1 nanometer ≤ T). r ≤30 nm). In some embodiments, the top of the substrate 50 is used as a reference plane, and the top portion of the mitigation layer 73 can be located at a height H between -15 nm and +15 nm. r (-15 nanometers ≤ H) r ≤+15 nm). The height H of the mitigation layer 73 r Positive value (H) r >0) indicates that the top portion of the mitigation layer 73 is located above the top portion of the substrate 50. The height H of the mitigation layer 73 r Negative value (H) r <0) indicates that the topmost portion of the mitigation layer 73 is located below the topmost portion of the substrate 50. In some embodiments, the angle θ between a straight line perpendicular to the principal plane of the substrate 50 and the surface of the mitigation layer 73 closest to the wall of the first groove 86 is... r It can be between 5 degrees and 120 degrees (5°≤θ) r ≤120°).

[0130] According to some embodiments, the thickness T of the dielectric layer 75 is... D It can be between 1 nanometer and 10 nanometers (1 nanometer ≤ T). D ≤10 nanometers). In some embodiments, the gap 77 in the dielectric layer 75 is at the width S at the interface between the dielectric layer 75 and the mitigation layer 73. D It can be between 1 nanometer and 20 nanometers (1 nanometer ≤ S D≤20 nanometers). In some embodiments, the horizontal length L of the dielectric layer 75 from the sidewall of the first groove 86 to the minimum portion of the gap 77 in the dielectric layer 75 is... D It can be between 1 nanometer and 10 nanometers (1 nanometer ≤ L) D ≤10 nanometers). In some embodiments, the angle θ between a straight line perpendicular to the main plane of the substrate 50 and the tangent of the dielectric layer 75 at the sidewall interface of the first groove 86. D It can be between 5 degrees and 120 degrees (5°≤θ) D ≤120°). It should be understood that, Figure 12G Representing a possible cross-sectional view, the angle θ between a straight line perpendicular to the main plane of substrate 50 and the cross-section of dielectric layer 75 at the sidewall interface of the first groove 86. D Less than 90 degrees.

[0131] To simplify the illustration, Figures 13A to 22C The drawing is based on such Figure 9B The shallowly etched substrate 50 shown does not have a mitigation layer 73 and / or a dielectric layer 75. However, it should be noted that... Figures 13B to 22B It may be appropriate to include Figures 9A to 9F and Figures 12A to 12G Various possible embodiments are shown. Dashed lines are added at appropriate locations in the figures to indicate the positions where a mitigation layer 73 and a dielectric layer 75 are included below the central epitaxial source / drain region 92.

[0132] exist Figures 13A to 13C In this process, an epitaxial source / drain region 92 is formed in the first groove 86. In some embodiments, the source / drain region 92 can apply stress to the second nanostructure 54 in the n-type region 50N and the first nanostructure 52 in the p-type region 50P, thereby improving performance. Figure 13B As illustrated, epitaxial source / drain regions 92 are formed in a first recess 86, such that each dummy gate 76 is disposed between individual adjacent pairs of epitaxial source / drain regions 92. In some embodiments, a first spacer 81 is used to separate the epitaxial source / drain regions 92 and the dummy gates 76, and a first internal spacer 90 is used to separate the epitaxial source / drain regions 92 and the nanostructure 55 at an appropriate lateral distance, so that the epitaxial source / drain regions 92 of the resulting nanostructure field-effect transistor will not be short-circuited with the subsequently formed gate.

[0133] The epitaxial source / drain region 92 forming in the n-type region 50N, such as an NMOS region, can be achieved by shielding the p-type region 50P, such as a PMOS region. The epitaxial source / drain region 92 is then epitaxially grown within a first recess 86 in the n-type region 50N. The epitaxial source / drain region 92 can comprise any acceptable material suitable for an n-type nanostructure field-effect transistor. For example, if the second nanostructure 54 is silicon, the epitaxial source / drain region 92 can comprise a material to which tensile strain is applied to the second nanostructure 54, such as silicon, silicon carbide, phosphorus-doped silicon carbide, silicon phosphide, or the like. The epitaxial source / drain region 92 can have a surface protruding from an individual upper surface of the nanostructure 55 and can have facets.

[0134] The epitaxial source / drain region 92 forming in the p-type region 50P, for example, a PMOS region, can be achieved by shielding the n-type region 50N, for example, an NMOS region. The epitaxial source / drain region 92 is then epitaxially grown within a first recess 86 in the p-type region 50P. The epitaxial source / drain region 92 can comprise any acceptable material suitable for a p-type nanostructure field-effect transistor. For example, if the first nanostructure 52 is silicon-germanium, the epitaxial source / drain region 92 can comprise a material to which compressive strain is applied to the first nanostructure 52, such as silicon-germanium, boron-doped silicon-germanium, germanium, germanium-tin, or the like. The epitaxial source / drain region 92 can also have a surface protruding from an individual upper surface of the nanostructure 55 and can have facets.

[0135] The epitaxial source / drain region 92, the first nanostructure 52, the second nanostructure 54, and / or the substrate 50 can be doped to form the source / drain region, similar to the aforementioned process for forming lightly doped source / drain regions, and can be followed by an annealing process. The source / drain region can have an impurity concentration between approximately 1 × 10⁻⁶ per cubic centimeter. 19 Atoms to approximately 1 × 10¹⁰ per cubic centimeter 21 Interatomic. The n-type and / or p-type impurities in the source / drain regions can be any of the aforementioned impurities. In some embodiments, the epitaxial source / drain regions 92 can be doped in situ during growth.

[0136] As a result of the epitaxial process forming the epitaxial source / drain regions 92 in the n-type region 50N and the p-type region 50P, the upper surface of the epitaxial source / drain regions 92 has facets that extend laterally outward beyond the sidewalls of the nanostructure 55. In some embodiments, these facets cause adjacent epitaxial source / drain regions 92 in the same nanostructure field-effect transistor to merge as... Figure 13A Illustration. In other embodiments, after the epitaxial process is completed, the adjacent epitaxial source / drain regions 92 remain separated, as shown. Figure 13CIllustration. In Figure 13A and Figure 13C In the illustrated embodiment, a first spacer 81 may be formed on the top surface of the shallow trench isolation region 68 to block epitaxial growth. In some other embodiments, the first spacer 81 may cover a portion of the sidewalls of the nanostructure 55 to further block epitaxial growth. In some other embodiments, the spacer etching step in forming the first spacer 81 may be modified to remove the spacer material, thereby allowing the epitaxial growth region to extend to the surface of the shallow trench isolation region 68.

[0137] The epitaxial source / drain region 92 may include one or more semiconductor material layers. For example, the epitaxial source / drain region 92 may include a first semiconductor material layer 92A, a second semiconductor material layer 92B, and a third semiconductor material layer 92C. The epitaxial source / drain region 92 may use any number of semiconductor material layers. Each of the first semiconductor material layer 92A, the second semiconductor material layer 92B, and the third semiconductor material layer 92C may be formed of different semiconductor materials and may be doped with different dopant concentrations. In some embodiments, the first semiconductor material layer 92A may have a lower dopant concentration than the second semiconductor material layer 92B and a higher dopant concentration than the third semiconductor material layer 92C. In some embodiments where the epitaxial source / drain region 92 includes three semiconductor material layers, the first semiconductor material layer 92A may be deposited, the second semiconductor material layer 92B may be deposited over the first semiconductor material layer 92A, and the third semiconductor material layer 92C may be deposited over the second semiconductor material layer 92B.

[0138] Figure 13D The illustrated embodiment shows that the sidewalls of the first nanostructure 52 in the n-type region 50N and the second nanostructure 54 in the p-type region 50P are concave, the outer sidewall of the first internal spacer 90 is concave, and the first internal spacer 90 is recessed from the sidewalls of the second nanostructure 54 and the first nanostructure 52, respectively. Figure 13D The epitaxial source / drain region 92 can contact the first internal spacer 90 and can extend beyond the sidewalls of the second nanostructure 54 in the n-type region 50N and the sidewalls of the first nanostructure 52 in the p-type region 50P.

[0139] exist Figures 14A to 14C In, respectively in Figure 6A , Figure 13B and Figure 13A The illustrated structure has a first interlayer dielectric (ILD) deposited on top. Figures 7A to 13D The process will not change substantially. Figure 6A(Illustrated cross-section). The first interlayer dielectric layer 96 can be formed of a dielectric material and can be deposited by any suitable method, such as chemical vapor deposition, plasma-enhanced chemical vapor deposition (PECVD), or flow-through chemical vapor deposition. The dielectric material may include phospho-silicate glass (PSG), boro-silicate glass (BSG), boron-doped phospho-silicate glass (BPSG), undoped silicate glass (USG), or the like. Other insulating materials can be formed using any acceptable process. In some embodiments, a contact etchstop layer (CESL) 94 is disposed between the first interlayer dielectric layer 96 and the epitaxial source / drain region 92, the mask 78, and the first spacer 81. The contact etch stop layer 94 may include a dielectric material with a different etch rate than the material covering the first interlayer dielectric layer 96, such as silicon nitride, silicon oxide, silicon oxynitride, or the like.

[0140] exist Figure 15A and Figure 15B In this process, a planarization process, such as chemical mechanical polishing, can be performed to flush the top surface of the first interlayer dielectric layer 96 with the top surface of the dummy gate 76 or the mask 78. The planarization process may also remove the mask 78 on the dummy gate 76 and a portion of the first spacer 81 along the sidewalls of the mask 78. After the planarization process, the top surfaces of the dummy gate 76, the first spacer 81, and the first interlayer dielectric layer 96 are flush within process tolerances. Therefore, the top surface of the dummy gate 76 is exposed through the first interlayer dielectric layer 96. In some embodiments, the mask 78 may be retained, wherein the planarization process flushes the top surface of the first interlayer dielectric layer 96 with the top surfaces of the mask 78 and the first spacer 81.

[0141] exist Figure 16A and Figure 16BIn one or more etching steps, the dummy gate 76 (and, if present, the mask 78) is removed, thus forming a second recess 98. A portion of the dummy gate dielectric 71 in the second recess 98 is also removed. In some embodiments, an anisotropic dry etching process is used to remove the dummy gate 76 and the dummy gate dielectric 71. For example, the etching process may include a dry etching process using a reactive gas, wherein the reactive gas selectively etches the dummy gate 76 at a faster rate than the first interlayer dielectric layer 96 or the first spacer 81. Each second recess 98 exposes and / or covers portions of nanostructures 55, which serve as channel regions in the subsequently completed nanostructured field-effect transistor. The portion of the nanostructures 55 serving as channel regions is disposed between adjacent pairs of epitaxial source / drain regions 92. During removal, the dummy gate dielectric 71 may serve as an etch stop layer when etching the dummy gate 76. After removing the dummy gate 76, the dummy gate dielectric 71 may then be removed.

[0142] exist Figure 17A and Figure 17B In this process, a first nanostructure 52 in the n-type region 50N and a second nanostructure 54 in the p-type region 50P are removed to extend the second groove 98. The removal of the first nanostructure 52 can be achieved by forming a mask (not shown) over the p-type region 50P and performing, for example, wet etching or a similar isotropic etching process, wherein the etchant used selectively etches the material of the first nanostructure 52, while the second nanostructure 54, the substrate 50, and the shallow trench isolation region 68 remain relatively unetched compared to the first nanostructure 52. In some embodiments where the first nanostructure 52 comprises, for example, SiGe and the second nanostructures 54A to 54C comprise, for example, Si or SiC, tetramethylammonium hydroxide, ammonium hydroxide, or the like can be used to remove the first nanostructure 52 in the n-type region 50N.

[0143] Removing the second nanostructure 54 from the p-type region 50P can be achieved by forming a mask (not shown) over the n-type region 50N and performing, for example, wet etching or a similar isotropic etching process, in which the etchant used selectively etches the material of the second nanostructure 54, while the first nanostructure 52, the substrate 50, and the shallow trench isolation region 68 remain relatively unetched compared to the second nanostructure 54. In some embodiments where the second nanostructure 54 comprises, for example, SiGe and the first nanostructure 52 comprises, for example, Si or SiC, hydrogen fluoride, other fluorine-based etchants, or the like can be used to remove the second nanostructure 54 from the p-type region 50P.

[0144] In other embodiments, channel regions in both the n-type region 50N and the p-type region 50P can be formed simultaneously, for example, by removing the first nanostructure 52 from both the n-type region 50N and the p-type region 50P, or by removing the second nanostructure 54 from both the n-type region 50N and the p-type region 50P. In such embodiments, the channel regions of the n-type nanostructure field-effect transistor and the p-type nanostructure field-effect transistor can have the same material composition, such as silicon, silicon germanium, or the like. Figure 22A , Figure 22B and Figure 22C The diagram illustrates the structure resulting from such an embodiment, wherein the second nanostructure 54 provides a channel region of either a p-type region 50P or an n-type region 50N, and the channel region comprises, for example, silicon.

[0145] exist Figure 18A and Figure 18B In the second trench 98, a gate dielectric layer 100 and a gate electrode 102 are formed as alternative gates. The gate dielectric layer 100 is conformally deposited in the second trench 98. In the n-type region 50N, the gate dielectric layer 100 can be formed on the top surface and sidewalls of the substrate 50, and on the top surface, sidewalls, and bottom surface of the second nanostructure 54. In the p-type region 50P, the gate dielectric layer 100 can be formed on the top surface and sidewalls of the substrate 50, and on the top surface, sidewalls, and bottom surface of the first nanostructure 52. The gate dielectric layer 100 can also be deposited on the top surface of the first interlayer dielectric layer 96, the contact etch stop layer 94, the first spacer 81, and the shallow trench isolation region 68.

[0146] According to some embodiments, the gate dielectric layer 100 includes one or more dielectric layers, such as oxides, metal oxides, the like, or combinations thereof. For example, in some embodiments, the gate dielectric may include silicon oxide and a metal oxide layer above the silicon oxide layer. In some embodiments, the gate dielectric layer 100 includes a high dielectric constant dielectric material, and in these embodiments, the gate dielectric layer 100 may have a dielectric constant greater than about 7.0, and may include metal oxides or silicates of hafnium, aluminum, zirconium, lanthanum, manganese, barium, titanium, lead, and combinations thereof. The structures of the gate dielectric layer 100 in the n-type region 50N and the p-type region 50P may be the same or different. Methods for forming the gate dielectric layer 100 may include molecular-beam deposition (MBD), atomic layer deposition, plasma-enhanced chemical vapor deposition, and the like.

[0147] Multiple gate electrodes 102 are deposited above the gate dielectric layer 100 and fill the remaining portion of the second trench 98. The gate electrodes 102 may comprise a metallic material, such as titanium nitride, titanium oxide, tantalum nitride, tantalum carbide, cobalt, ruthenium, aluminum, tungsten, combinations thereof, or multiple layers of the above materials. For example, although... Figure 18A and Figure 18B The diagram illustrates a single-layer gate electrode 102, but the gate electrode 102 may include any number of liner layers, any number of work function adjustment layers, and filler material. Any combination of layers forming the gate electrode 102 may be deposited between adjacent second nanostructures 54 in the n-type region 50N, between the second nanostructure 54A and the substrate 50, and may be deposited between adjacent first nanostructures 52 in the p-type region 50P.

[0148] Gate dielectric layers 100 can be formed simultaneously in n-type region 50N and p-type region 50P, such that the gate dielectric layers 100 in each region are formed of the same material, and gate electrodes 102 can be formed simultaneously, such that the gate electrodes 102 in each region are formed of the same material. In some embodiments, separate processes can be used to form the gate dielectric layers 100 in each region, such that the gate dielectric layers 100 can be of different materials and / or have different numbers of layers, and / or separate processes can be used to form the gate electrodes 102 in each region, such that the gate electrodes 102 can be of different materials and / or have different numbers of layers. When using separate processes, multiple masking steps can be used to mask and expose appropriate areas.

[0149] After filling the second recess 98, a planarization process, such as chemical mechanical polishing, can be performed to remove excess material from the gate dielectric layer 100 and the gate electrode 102, where this excess material is located above the top surface of the first interlayer dielectric layer 96. Thus, the remaining material of the gate electrode 102 and the gate dielectric layer 100 forms the alternative gate structure of the resulting nanostructured field-effect transistor. The gate electrode 102 and the gate dielectric layer 100 can be collectively referred to as the "gate structure".

[0150] exist Figures 19A to 19C In this recessed gate structure (including a gate dielectric layer 100 and a corresponding overlying gate electrode 102), a groove is formed between the gate structure directly above and the opposite portion of the first spacer 81. The gate mask 104 includes one or more layers of dielectric material, such as silicon nitride, silicon oxynitride, or the like, filled into the groove, and a planarization process is followed to remove excess dielectric material extending above the first interlayer dielectric layer 96. Gate contacts (e.g., gate contact 114, as described below) are then formed through the gate mask 104. Figure 21A and Figure 21B (as described above), to contact the top surface of the recessed gate electrode 102.

[0151] like Figures 19A to 19CFurther illustrated, a second interlayer dielectric layer 106 is deposited over the first interlayer dielectric layer 96 and on the gate mask 104. In some embodiments, the second interlayer dielectric layer 106 is a flowable film formed by flow chemical vapor deposition. In some embodiments, the second interlayer dielectric layer 106 is formed of a dielectric material, such as phosphosilicate glass, borosilicate glass, boron-doped phosphosilicate glass, undoped silicate glass, or the like, and can be deposited using any suitable method, such as chemical vapor deposition, plasma-enhanced chemical vapor deposition, or the like.

[0152] exist Figures 20A to 20C In the process, the second interlayer dielectric layer 106, the first interlayer dielectric layer 96, the contact etch stop layer 94, and the gate mask 104 are etched to form a third groove 108, wherein the third groove 108 exposes the surface of the epitaxial source / drain region 92 and / or the gate structure. Anisotropic etching processes, such as reactive ion etching, neutral particle beam etching, or the like, can be used to form the third groove 108. In some embodiments, the third groove 108 can be etched through the second interlayer dielectric layer 106 and the first interlayer dielectric layer 96 using a first etching process, etched through the gate mask 104 using a second etching process, and then etched through the contact etch stop layer 94 using a third etching process. A mask, such as photoresist, can be formed and patterned over the second interlayer dielectric layer 106 to shield portions of the second interlayer dielectric layer 106 during the first and second etching processes. In some embodiments, the etching process can over-etch, so that the third groove 108 extends into the epitaxial source / drain region 92 and / or gate structure, and the bottom of the third groove 108 can be flush with (e.g., at the same level or at the same distance from the substrate) or lower than (e.g., closer to the substrate) the epitaxial source / drain region 92 and / or gate structure. Although Figure 20BThe third recess 108 is illustrated to expose the epitaxial source / drain region 92 and the gate structure in the same cross section. However, in various embodiments, the epitaxial source / drain region 92 and the gate structure may be exposed in different cross sections, thereby reducing the risk of short circuits in subsequently formed contacts. After forming the third recess 108, a silicide region 110 is formed over the epitaxial source / drain region 92. In some embodiments, forming the silicide region 110 involves first depositing a metal (not shown), such as nickel, cobalt, titanium, tantalum, platinum, tungsten, other noble metals, other refractory metals, rare earth metals, or alloys thereof, over the exposed portion of the epitaxial source / drain region 92. This metal may react with the semiconductor material (e.g., silicon, silicon-germanium, germanium) of the underlying epitaxial source / drain region 92 to form a silicide or germanide region. A thermal annealing process is then performed to form the silicide region 110. Unreacted portions of the deposited metal are then removed using, for example, an etching process. Although the silicide region 110 is referred to as a silicide region, it can also be a germanide region or a silicon-germanide region (e.g., a region comprising both silicide and germanide). In one embodiment, the silicide region 110 comprises TiSi and has a thickness ranging from about 2 nanometers to about 10 nanometers.

[0153] Next, in Figures 21A to 21C In the third recess 108, contacts 112 and 114 (also referred to as contact plugs) are formed. Contacts 112 and 114 may each include one or more layers, such as a barrier layer, a diffusion layer, and a filler material. For example, in some embodiments, contacts 112 and 114 each include a barrier layer and a conductive material, and are electrically coupled to underlying conductive features (e.g., gate structure 102 and / or silicide region 110 illustrated in the embodiment). Contact 114 is electrically coupled to gate structure 102 and may be referred to as a gate contact, and contact 112 is electrically coupled to silicide region 110 and may be referred to as a source / drain contact. The barrier layer may include titanium, titanium nitride, tantalum, tantalum nitride, or the like. The conductive material may be copper, copper alloy, silver, gold, tungsten, cobalt, aluminum, nickel, or the like. A planarization process, such as chemical mechanical polishing, may be performed to remove excess material from the surface of the second interlayer dielectric layer 106.

[0154] According to some other embodiments, Figures 22A to 22C Draw a cross-sectional view of the device. Figure 22A Draw Figure 1 The reference section AA′ in the diagram. Figure 22B Draw Figure 1 The reference section BB′ in the diagram. Figure 22C Draw Figure 1 The reference section CC′ is shown in the figure. Figures 22A to 22C In, with Figures 22A to 22CIn the structure, similar reference numbers represent similar elements formed by similar processes. However, in Figures 22A to 22C In this configuration, the channel regions in the n-type region 50N and the p-type region 50P comprise the same material. For example, a second nanostructure 54 comprising silicon provides the channel regions for the p-type nanostructure field-effect transistor in the p-type region 50P and the n-type nanostructure field-effect transistor in the n-type region 50N. Figures 22A to 22C The structure can be achieved, for example, by simultaneously removing the first nanostructure 52 from both the p-type region 50P and the n-type region 50N; depositing a gate dielectric layer 100 and a gate electrode 102P (e.g., suitable for the gate electrode of a p-type nanostructure field-effect transistor) around the second nanostructure 54 in the p-type region 50P; and depositing a gate dielectric layer 100 and a gate electrode 102N (e.g., suitable for the gate electrode of an n-type nanostructure field-effect transistor) around the second nanostructure 54 in the n-type region 50N. In such an embodiment, as described above, the material of the epitaxial source / drain region 92 in the n-type region 50N can be different from that of the p-type region 50P.

[0155] When using the back-side silicon via 116 to provide more connections to the epitaxial source / drain regions 92, the structure may include, for example... Figures 9B to 9F The remaining etch contours of the substrate 50 and the first bottom layer 69, as well as the remaining etch contours of the mitigation layer 73 and / or dielectric layer 75, are shown. Through-silicon vias 116 are formed to connect the epitaxial source / drain regions 92 to an external connector (not shown). Any suitable method may be used to form and pattern the through-silicon vias 116, the external connector, and further dielectric and metallization materials included on the back side in some embodiments. For simplicity, the respective n-type regions 50N and p-type regions 50P are illustrated as having only one back-side through-silicon via 116 (e.g., Figure 24 However, this is not intended to limit the number of silicon vias 116 that can be fabricated to connect to multiple epitaxial source / drain regions 92.

[0156] According to some embodiments, Figure 23A The diagram illustrates the formation of a silicon through-hole (SHB) opening 122. At any desired point in the manufacturing process, but after the formation of the mitigation layer 73 and / or dielectric layer 75, a SHB 116 can be formed in the substrate 50 to provide an electrical connection from the epitaxial source / drain region 92 to the back side of the substrate 50. In one embodiment, forming the SHB 116 can be achieved by first forming the SHB opening 122 in the substrate 50, followed by any alternating layers of dielectric and conductive materials. Forming the SHB opening can be achieved by applying and developing a suitable photoresist, and removing portions of the underlying material to expose the underlying material to a desired depth.

[0157] In some embodiments, reactive ion etching can be performed using a gas such as SF6 or NF3 to preferentially etch into the substrate 50. The etching depth can be controlled by varying the etching process duration, among other process parameters. Because the mitigation layer 73 contains impurities, the etch rate of reactive ion etching during etching is slowed by the mitigation layer's exposure to the etch, thus allowing for better control over the depth at which the silicon via opening forms into the epitaxial source / drain region 92.

[0158] In some embodiments, a dielectric layer 75 is further included between the mitigation layer 73 and the epitaxial source / drain region 92, such as Figure 23A As shown, reactive ion etching can use a gas that exhibits high etch selectivity relative to the dielectric layer 75, as well as the substrate 50, the slowing layer 73 (which has a slower etch rate than the substrate 50), and the epitaxial source / drain regions 92. Figure 23B Pictured in the middle Figure 23A As shown in a magnified and further detailed manner, the sidewalls etched in the substrate and / or epitaxial source / drain regions 92 can be steeper than the sidewalls etched in the mitigation layer 73. Specifically, the angle θ of the sidewalls of the silicon via openings 122 in the substrate 50 and / or epitaxial source / drain regions 92... VB The angle θ is smaller than the sidewall of the silicon via opening 122 through the mitigation layer 73. VB .

[0159] Therefore, the penetration depth T of the back-side silicon via 116 etched into the source / drain region 92 can be limited. VB and horizontal width S VB In some embodiments, the penetration depth T etched into the epitaxial source / drain region 92 is... VB It can be between 5 nanometers and 15 nanometers (5 nanometers ≤ T). VB ≤15 nanometers). In some embodiments, the horizontal width S etched into the epitaxial source / drain region 92 VB It can be between approximately 0 nanometers and 10 nanometers (0 nanometers ≤ S). VB (≤10 nm). Therefore, defects and decreased conductivity in the epitaxial source / drain regions 92 can be minimized, the operation and efficiency of the associated devices can be improved, and manufacturing defects can be limited. As a result, increased manufacturing yield, reduced manufacturing costs, increased manufacturing efficiency, and smaller device size and thickness can be achieved.

[0160] According to some embodiments, Figure 24The completed silicon through-hole 116 is illustrated. Once the silicon through-hole opening 122 is formed in the substrate 50, a liner (not shown) can be used as a liner for the silicon through-hole opening 122. The liner can be, for example, an oxide formed of tetraethyl orthosilicate (TEOS) or silicon nitride, but any suitable dielectric material can also be used. The liner can be formed using a plasma-enhanced chemical vapor deposition process, but other suitable processes such as physical vapor deposition or thermal processes can also be used.

[0161] Once the liner is formed along the sidewalls and bottom of the silicon through-hole opening, a barrier layer (not shown) can be formed, and the remainder of the silicon through-hole opening can be filled with a first conductive material. The first conductive material may include copper, but other suitable materials may also be used, such as aluminum, alloys, doped polysilicon, combinations thereof, and the like. The first conductive material can be formed by electroplating copper onto a seed layer, filling, and overfilling the silicon through-hole opening. Once the silicon through-hole opening is filled, excess liner, barrier layer, seed layer, and conductive material outside the silicon through-hole opening can be removed by a planarization process, such as chemical mechanical polishing, but any suitable removal process may also be used.

[0162] Once the silicon via opening 122 is filled, the substrate can be thinned. In one embodiment, the substrate 50 can be thinned using, for example, a chemical mechanical polishing process, a grinding process, or the like. Furthermore, once the silicon via 116 is exposed, the silicon via 116 can be recessed using, for example, one or more etching processes, such as a wet etching process for recessing the substrate 50, to extend the silicon via 116 beyond the substrate 50.

[0163] In one embodiment, an external connector (not shown) electrically connected to the through-silicon via 116 can be placed on the substrate 50, and can be, for example, a ball grid array (BGA) comprising a eutectic material such as solder, but any suitable material can also be used. Alternatively, an underbump metallization or additional metallization layer (not shown) and dielectric layer (not shown) can be used between the substrate 50 and the external connector. In one embodiment where the external connector includes solder balls, the external connector can be formed using a ball drop method, such as a direct ball drop process. In another embodiment, solder bumps can be formed by first forming a layer of tin by any suitable method, such as vapor deposition, electroplating, printing, solder transfer, and then performing reflow to shape the material into the desired bump shape. Once the external connector is formed, testing can be performed to ensure the structure is suitable for further processing.

[0164] The embodiments disclosed herein can achieve several advantages. For example, defects and reduced conductivity in the epitaxial source / drain regions 92 can be minimized, the operation and efficiency of the associated devices can be enhanced, and manufacturing defects can be limited. Therefore, increased manufacturing yield, reduced manufacturing costs, increased manufacturing efficiency, and smaller device size and thickness can be achieved.

[0165] In a first embodiment, a semiconductor device includes a substrate, a source / drain region, a mitigation layer between the substrate and the source / drain region, and a silicon via electrically connecting the source / drain region to the back side of the semiconductor device, wherein the mitigation layer has a slower etch rate than the substrate and the source / drain region when exposed to etch, and the silicon via passes through the substrate, the mitigation layer, and a portion of the source / drain region.

[0166] In some embodiments, the semiconductor device further includes a dielectric layer between the mitigation layer and the source / drain regions, wherein through-silicon vias further penetrate a gap in the dielectric layer. In some embodiments, the dielectric layer has a thickness between 1 nm and 10 nm, the ratio of the dielectric layer thickness to the mitigation layer thickness is between 1.0 and 20.0, the dielectric layer has a gap spanning between 1 nm and 20 nm near the center of the dielectric layer, and the ratio of the gap spanning distance to the distance between the outer edge of the dielectric layer and the nearest gap sidewall is between 1 and 10. In some embodiments, the impurity concentration doped in the mitigation layer has a peak concentration to baseline concentration ratio between 1.0 and 2.5. In some embodiments, the impurity concentration is gradual, wherein the impurity concentration increases from a baseline concentration located at the top surface of the mitigation layer to a peak concentration located 1 nm to 15 nm below the top surface of the mitigation layer, and decreases back to a baseline concentration located at the bottom surface of the mitigation layer. In some embodiments, the semiconductor device is an n-type field-effect transistor, the substrate comprises silicon, and the mitigation layer comprises Si. 1-x Ge x Furthermore, 0.0 ≤ x ≤ 0.4, the source / drain regions are p-type materials, and the impurities are boron. In some embodiments, the top surface of the mitigation layer is located between 15 nm below and 15 nm above the top surface of the substrate, and the thickness of the mitigation layer is between 1 nm and 30 nm. In some embodiments, the mitigation layer is flat within the process parameters when spanning the width of the source / drain regions. In some embodiments, the mitigation layer is curved when spanning the width of the source / drain regions, and the angle between the top surface of the mitigation layer and the tangent of the trench interface surrounding the source / drain regions and the virtual line perpendicular to the main plane of the semiconductor device is between 5 degrees and 120 degrees.

[0167] In a second embodiment, a method of forming a semiconductor device includes the following steps: A trench is formed in the surface of the semiconductor device, including a substrate. A mitigation layer is formed at the bottom of the trench. Source / drain regions are formed above the mitigation layer in the trench. An opening is etched through the substrate, the mitigation layer, and a portion of the source / drain regions, wherein when the substrate, the mitigation layer, and a portion of the source / drain regions are exposed to the same etching process as etching the substrate, the etch rate of the substrate and the portion of the source / drain regions is higher than the etch rate of the mitigation layer. Through-silicon vias are formed in the opening.

[0168] In some embodiments, the method further includes forming a dielectric layer above the mitigation layer before forming the source / drain region, and forming a gap in the dielectric layer near the center of the dielectric layer, wherein the ratio of the gap spanning a distance to the distance from the outer edge of the dielectric layer to the nearest gap sidewall is between 1 and 10.

[0169] In a third embodiment, a nanostructure field-effect transistor includes a substrate having fins, an isolation region above the substrate and along opposite sides of the fins, a plurality of nanostructures above the fins, source / drain regions adjacent to the plurality of nanostructures, a gate electrode above the plurality of nanostructures, a mitigation layer between the substrate and the source / drain regions and having an etching rate slower than that of the source / drain regions and the substrate when exposed to an etching process, and a silicon via through the substrate and the mitigation layer and electrically contacting the source / drain regions.

[0170] In some embodiments, the nanostructured field-effect transistor further includes a dielectric layer between the mitigation layer and the source / drain regions, wherein the dielectric layer has a gap near its center, and silicon vias pass through the gap to electrically contact the source / drain regions. In some embodiments, the thickness of the dielectric layer is between 1 nanometer and 10 nanometers, the gap has a horizontal span between 1 nanometer and 20 nanometers, the horizontal distance between the gap and the edge of the source / drain regions is between 1 nanometer and 10 nanometers, and the angle of the inner edge of the gap measured from a line perpendicular to the principal plane of the top surface of the substrate is between 10 degrees and 150 degrees. In some embodiments, the mitigation layer comprises silicon and germanium in a ratio of Si. 1-x Ge x Furthermore, 0.0 ≤ x ≤ 0.4, and the mitigation layer includes a doped impurity concentration between 1 × 10⁻⁶ per cubic centimeter. 20 Atoms up to 5 × 10⁵ per cubic centimeter 20 Interatomic. In some embodiments, the impurity concentration is a gradient concentration across the height of the mitigation layer, wherein the gradient concentration begins at a baseline concentration at the top of the mitigation layer, rises to a peak concentration 1 to 15 nanometers below the top of the mitigation layer, and decreases back to the baseline concentration at the bottom of the mitigation layer. In some embodiments, the baseline concentration is between 1 × 10⁻⁶ per cubic centimeter. 20 Atoms up to 2 × 10 per cubic centimeter 22Between atoms, the peak concentration is between 1 × 10⁻⁶ per cubic centimeter. 20 Atoms up to 5 × 10⁵ per cubic centimeter 22 The ratio of baseline concentration to peak concentration is between 1.0 and 2.5, with the baseline concentration being lower than the peak concentration. In some embodiments, the thickness of the mitigation layer is between 1 nm and 30 nm, and the top of the mitigation layer is located between 15 nm above and 15 nm below the interface, wherein the interface is located between the substrate and the nanostructure closest to the substrate among a plurality of nanostructures. In some embodiments, silicon vias extend towards the source / drain region to between 5 nm and 15 nm above the top surface of the mitigation layer. In some embodiments, the mitigation layer is curved across the width of the source / drain region, and the angle between the cross-section of the top surface of the mitigation layer closest to the plurality of nanostructures and a line perpendicular to the main plane of the substrate is between 5 degrees and 120 degrees.

[0171] In a fourth embodiment, a semiconductor device includes a substrate, a source / drain region, a mitigation layer between the substrate and the source / drain region, and a silicon via electrically connecting the source / drain region to the back side of the semiconductor device, wherein the etch selectivity of the mitigation layer relative to silicon is between 1.01 and 100.00, and the silicon via passes through the substrate, the mitigation layer, and a portion of the source / drain region.

[0172] In a fifth embodiment, a semiconductor device includes a substrate, a source / drain region, a mitigation layer located between the substrate and the source / drain region, a dielectric layer located between the mitigation layer and the source / drain region, and a silicon via penetrating a gap in the substrate, the mitigation layer, the dielectric layer, and a portion of the source / drain region, wherein the etch selectivity of the mitigation layer relative to silicon is between 1.01 and 100.00, and the ratio of the thickness of the dielectric layer to the thickness of the mitigation layer is between 1.0 and 20.0.

[0173] In a sixth embodiment, a nanostructure field-effect transistor includes a substrate having fins, an isolation region above the substrate and along opposite sides of the fins, a plurality of nanostructures above the fins, source / drain regions adjacent to the plurality of nanostructures, a gate electrode above the plurality of nanostructures, a mitigation layer between the substrate and the source / drain regions and having an etch selectivity relative to silicon between 1.01 and 100.00, and a silicon via through the substrate and the mitigation layer and electrically contacting the source / drain regions.

[0174] The foregoing outlines features of some embodiments to enable those skilled in the art to better understand the ideas presented in this disclosure. Those skilled in the art should understand that they can readily use this disclosure as a basis for designing or modifying other processes and structures to achieve the same purpose and / or the same advantages as the embodiments described herein. Those skilled in the art should also understand that such equivalent constructions do not depart from the spirit and scope of this disclosure, and that various changes, substitutions, and modifications can be made without departing from the spirit and scope of this disclosure.

Claims

1. A semiconductor device, characterized in that, include: One substrate; One source / drain region; A mitigation layer is located between the substrate and the source / drain region, wherein the etch selectivity of the mitigation layer relative to silicon is between 1.01 and 100.00; and A silicon via electrically connects the source / drain region to a back side of the semiconductor device, wherein the silicon via passes through the substrate, the mitigation layer, and a portion of the source / drain region.

2. The semiconductor device as claimed in claim 1, characterized in that, It further includes a dielectric layer between the mitigation layer and the source / drain region, wherein the silicon via further passes through a gap in the dielectric layer.

3. The semiconductor device as claimed in claim 2, characterized in that, The ratio of the thickness of the dielectric layer to the thickness of the mitigation layer is between 1.0 and 20.0, the dielectric layer has the gap at a center, and the ratio of the distance spanned by the gap to the distance from the outer edge of the dielectric layer to the nearest gap sidewall is between 1 and 10.

4. The semiconductor device as claimed in claim 2, characterized in that, The top surface of the mitigation layer is located between 15 nanometers below and 15 nanometers above the top surface of the substrate, and the thickness of the mitigation layer is between 1 nanometer and 30 nanometers.

5. The semiconductor device as claimed in claim 2, characterized in that, The mitigation layer is curved across a width of the source / drain region, and the angle between the top surface of the mitigation layer at an interface of a trench surrounding the source / drain region and a virtual line perpendicular to a main plane of the semiconductor device is between 5 degrees and 120 degrees.

6. A semiconductor device, characterized in that, include: One substrate; One source / drain region; A mitigation layer is located between the substrate and the source / drain region, wherein the etch selectivity of the mitigation layer relative to silicon is between 1.01 and 100.00; A dielectric layer is located between the mitigation layer and the source / drain region, wherein the ratio of the thickness of the dielectric layer to the thickness of the mitigation layer is between 1.0 and 20.0; and A silicon via passes through a gap in the substrate, the mitigation layer, the dielectric layer, and a portion of the source / drain region.

7. A nanostructured field-effect transistor, characterized in that, include: A substrate, wherein the substrate includes a fin; Multiple isolation areas are located above the substrate and along the opposite sides of the fin; Multiple nanostructures are located above the fin; A source / drain region is adjacent to the plurality of nanostructures; A gate electrode is located above the plurality of nanostructures; A mitigation layer is located between the substrate and the source / drain region, wherein the etch selectivity of the mitigation layer relative to silicon is between 1.01 and 100.00; and A silicon via passes through the substrate and the mitigation layer and makes electrical contact with the source / drain region.

8. The nanostructured field-effect transistor as described in claim 7, characterized in that, Further includes: A dielectric layer is located between the mitigation layer and the source / drain region, wherein the dielectric layer has a gap near a center of the dielectric layer, and the silicon via passes through the gap to electrically contact the source / drain region.

9. The nanostructured field-effect transistor as described in claim 8, characterized in that, The thickness of the dielectric layer is between 1 nanometer and 10 nanometers, the horizontal span of the gap is between 1 nanometer and 20 nanometers, the horizontal distance between the gap and an edge of the source / drain region is between 1 nanometer and 10 nanometers, and the angle of an inner edge of the gap measured from a line perpendicular to a main plane of a top surface of the substrate is between 10 degrees and 150 degrees.

10. The nanostructured field-effect transistor as described in claim 7, characterized in that, The thickness of the mitigation layer is between 1 nanometer and 30 nanometers. One top of the mitigation layer is located between 15 nanometers above and 15 nanometers below an interface, and the interface is located between the substrate and the nanostructure closest to the substrate among the plurality of nanostructures.

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