Display panel and display device

Abstract

The application discloses a display panel and a display device, and relates to the technical field of display. The display panel comprises a substrate and a driving circuit layer. The first conductive layer in the driving circuit layer comprises a second wire part located in a transition area and a bending area, and the second conductive layer comprises a first wire part located in the transition area. The first wire part can be electrically connected with the connection part of the second wire part located in the transition area, so as to realize signal transmission. The thickness of the insulating layer part of the first insulating layer and / or the second insulating layer, which is located on the side of the connection part away from the substrate and covers the side surface of the connection part close to the display area, is large in the direction perpendicular to the surface of the substrate, so that the side surface of the connection part cannot be exposed, and the abnormal side surface morphology caused by the exposure of the side surface of the connection part can be avoided, the yield of other film layers on the side of the connection part away from the substrate can be ensured, and the reliability of the display panel can be ensured.

Description

Technical Field

[0001] This application relates to the field of display technology, and in particular to a display panel and display device. Background Technology

[0002] A display panel typically includes a display area and a surrounding area. Furthermore, a display panel typically includes multiple pixel units located within the display area, a driver chip for providing drive signals to the pixel units, and signal traces for connecting the pixel units and the driver chip.

[0003] In related technologies, with the continuous advancement of display technology, display devices are developing towards narrower bezels. Therefore, currently, the portion of the display panel containing the driver chip is typically bent to the non-display side to reduce the width of the display panel's bezel.

[0004] However, in related technologies, the signal traces in the bending area of ​​the display panel need to be replaced with new layers, which can easily lead to exposed edges of the signal traces and affect the yield of subsequent film layers, resulting in a low yield of the display panel. Utility Model Content

[0005] This application provides a display panel and a display device, which can solve the problem of low yield rate of display panels in related technologies. The technical solution is as follows:

[0006] On one hand, a display panel is provided, the display panel comprising:

[0007] A substrate, the substrate including a display area and a peripheral area surrounding the display area, the peripheral area including a bending area and a transition area located between the display area and the bending area, the portion of the display panel located in the bending area being bent;

[0008] A driving circuit layer is located on one side of the substrate. The driving circuit layer includes a first conductive layer and a first insulating layer stacked in a direction away from the substrate. The driving circuit layer also includes a second conductive layer and a second insulating layer stacked in a direction away from the substrate. The orthographic projection of the portion of the second conductive layer in the display area on the substrate and the orthographic projection of the portion of the first conductive layer in the display area on the substrate overlap.

[0009] The second conductive layer includes a first trace portion located in the transition region, the first conductive layer includes a second trace portion located in the transition region and the bending region, the second trace portion includes a connection portion located in the transition region, the connection portion and the first trace portion are electrically connected, the first insulating layer and / or the second insulating layer cover the side of the connection portion near the display area, and the thickness of the insulating layer portion of the first insulating layer and / or the second insulating layer covering the side of the connection portion near the display area in the direction perpendicular to the surface of the substrate is greater than a thickness threshold.

[0010] Optionally, the second conductive layer and the second insulating layer are located between the substrate and the first conductive layer;

[0011] The orthographic projection of the second insulating layer on the substrate and the orthographic projection of the side of the connecting portion near the display area on the substrate do not overlap.

[0012] Optionally, the orthographic projection of the second insulating layer on the substrate and the orthographic projection of the connecting portion on the substrate do not overlap;

[0013] The first insulating layer includes a first target insulating portion, the orthographic projection of which covers the side of the connection portion near the display area.

[0014] Optionally, the second insulating layer includes a second target insulating portion, a portion of the connecting portion is located on the side of the second target insulating portion away from the substrate, and the orthographic projection of the connecting portion on the substrate covers the orthographic projection of the second target insulating portion on the substrate; the orthographic projection of the side of the connecting portion near the display area on the substrate is located on the side of the orthographic projection of the second target insulating portion on the substrate near the display area.

[0015] The first insulating layer includes a first target insulating portion, the orthographic projection of which covers the side of the connection portion near the display area.

[0016] Optionally, the driving circuit layer further includes a third insulating layer located on the side of the first insulating layer away from the substrate.

[0017] The third insulating layer includes a third target insulating portion, and the orthographic projection of the third target insulating portion on the substrate and the orthographic projection of the connecting portion on the substrate overlap.

[0018] Optionally, the third target insulating portion is located near the boundary of the display area, the first target insulating portion is located near the boundary of the display area, and the side of the connecting portion near the display area is arranged sequentially in a direction away from the display area.

[0019] Optionally, the first target insulating portion is located near the boundary of the display area, the third target insulating portion is located near the boundary of the display area, and the side of the connecting portion near the display area is arranged sequentially in a direction away from the display area.

[0020] Optionally, the first target insulating portion is located near the boundary of the display area, the connecting portion is located near the side of the display area, and the third target insulating portion is located near the boundary of the display area, arranged sequentially in a direction away from the display area.

[0021] Optionally, the second conductive layer and the second insulating layer are located between the substrate and the first conductive layer; the orthographic projection of the second insulating layer on the substrate and the orthographic projection of the side of the connection portion near the display area on the substrate overlap;

[0022] The driving circuit layer further includes a third insulating layer located on the side of the first insulating layer away from the substrate. The third insulating layer includes a third target insulating portion. The orthographic projection of the third target insulating portion on the substrate covers the orthographic projection of the side of the connection portion near the display area on the substrate. The boundary of the third target insulating portion near the display area is closer to the display area than the side of the connection portion near the display area.

[0023] Optionally, the first insulating layer includes a first target insulating portion, the orthographic projection of which covers the side of the connection portion near the display area.

[0024] The boundary of the first target insulating portion near the display area is closer to the display area than the boundary of the third target insulating portion near the display area.

[0025] Optionally, the distance between the orthographic projection of the boundary of the third target insulating portion near the display area on the substrate and the orthographic projection of the side of the connecting portion near the display area on the substrate is greater than or equal to 3 μm.

[0026] Optionally, the first insulating layer includes a first target insulating portion, the orthographic projection of which covers the side of the connection portion near the display area.

[0027] The boundary of the third target insulation portion near the display area is closer to the display area than the boundary of the first target insulation portion near the display area.

[0028] Optionally, the driving circuit layer further includes a first passivation layer located between the second conductive layer and the second insulating layer, wherein the first passivation layer at least covers the portion of the first trace that is not covered by the first insulating layer and / or the second insulating layer.

[0029] Optionally, the second conductive layer and the second insulating layer are located on the side of the first insulating layer away from the substrate.

[0030] The first trace portion covers the side of the connection portion near the display area and covers at least a portion of the connection portion.

[0031] Optionally, the second insulating layer includes a second target insulating portion, the boundary of the second insulating target portion near the display area being closer to the display area than the side of the connecting portion near the display area.

[0032] Optionally, the driving circuit layer further includes a second passivation layer located between the second conductive layer and the second insulating layer, the second passivation layer at least covering the portion of the first trace portion not covered by the second target insulating portion.

[0033] Optionally, the second passivation layer is also located between the first trace portion and the second target insulation portion.

[0034] Optionally, the display panel may further include a blocking structure located in the transition area;

[0035] The orthographic projection of the blocking structure on the substrate surrounds the display area, and the orthographic projections of the blocking structure on the substrate and the orthographic projections of the first insulating layer and the second insulating layer on the substrate are spaced apart.

[0036] Optionally, the display panel includes a plurality of pixel units, each pixel unit including a pixel circuit and a light-emitting unit, the pixel circuit including a plurality of thin-film transistors and at least one storage capacitor; the driving circuit layer includes the pixel circuits of the plurality of pixel units; the driving circuit layer includes a buffer layer, an active layer, a first gate insulating layer, a first gate layer, a second gate insulating layer, a second gate layer, an interlayer dielectric layer, a first source-drain layer, a first passivation layer, a first planarization layer, a second source-drain layer, a second planarization layer, a third source-drain layer, and a third planarization layer stacked along a direction away from the substrate.

[0037] The active layer includes the active pattern of the plurality of thin-film transistors, and the active pattern includes a source region and a drain region;

[0038] The first gate layer includes the gate patterns of the plurality of thin-film transistors, and the first plate of the at least one storage capacitor;

[0039] The second gate layer includes the second substrate of the storage capacitor;

[0040] The first source-drain layer includes the source and drain of the plurality of thin-film transistors, wherein the source and the source region are connected, and the drain and the drain region are connected;

[0041] The second source-drain layer includes a plurality of first connection patterns, and the first connection patterns are connected to the drain.

[0042] The third source-drain layer includes a plurality of second connection patterns, and the second connection patterns are connected to the first connection pattern.

[0043] Wherein, the second source / drain layer is the first conductive layer, and the second planarization layer is the first insulating layer; when the second conductive layer and the second insulating layer are located between the substrate and the first conductive layer, the first source / drain layer is the second conductive layer, and the first planarization layer is the second insulating layer; when the second conductive layer and the second insulating layer are located on the side of the first insulating layer away from the substrate, the third source / drain layer is the second conductive layer, and the third planarization layer is the second insulating layer.

[0044] On the other hand, a display device is provided, the display device comprising: a power supply component and a display panel as described above;

[0045] The power supply component is connected to the display panel, and the power supply component is used to supply power to the display panel. Attached Figure Description

[0046] To more clearly illustrate the technical solutions in the embodiments of this application, the accompanying drawings used in the description of the embodiments will be briefly introduced below. Obviously, the accompanying drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0047] Figure 1 This is a schematic diagram of the structure of a display panel provided in an embodiment of this application;

[0048] Figure 2 This is a top view of a substrate provided in an embodiment of this application;

[0049] Figure 3 This is a schematic diagram of a partial cross-sectional structure of a display panel in the display area provided in an embodiment of this application;

[0050] Figure 4 This is a partial top view of the peripheral area of ​​a display panel provided in an embodiment of this application;

[0051] Figure 5 yes Figure 4 A partial schematic diagram of area A;

[0052] Figure 6 yes Figure 5 Cross-sectional view along the BB' direction;

[0053] Figure 7 yes Figure 5 Another cross-sectional view along the BB' direction;

[0054] Figure 8 This is a schematic diagram of a partial cross-sectional structure of another display panel in the display area provided in an embodiment of this application;

[0055] Figure 9 This is a schematic diagram of an incised structure appearing on the side of a connecting portion near the display area, as provided in this application.

[0056] Figure 10 yes Figure 5 Another cross-sectional view along the BB' direction;

[0057] Figure 11 yes Figure 4 A partial schematic diagram of region C;

[0058] Figure 12 yes Figure 4 Another partial schematic diagram of region C;

[0059] Figure 13 yes Figure 4 Another partial schematic diagram of region C;

[0060] Figure 14 yes Figure 4 Another partial schematic diagram of region C;

[0061] Figure 15 yes Figure 4 Another partial schematic diagram of region C;

[0062] Figure 16 yes Figure 4 Another partial schematic diagram of region C;

[0063] Figure 17 yes Figure 11 Cross-sectional view along the DD' direction;

[0064] Figure 18 yes Figure 4 Another partial schematic diagram of region C;

[0065] Figure 19 yes Figure 18 Cross-sectional view along the EE' direction;

[0066] Figure 20 yes Figure 4 Another partial schematic diagram of region C;

[0067] Figure 21 yes Figure 20 Cross-sectional view along the FF' direction;

[0068] Figure 22 yes Figure 4 Another partial schematic diagram of region C;

[0069] Figure 23 yes Figure 22 Cross-sectional view along the GG' direction;

[0070] Figure 24 yes Figure 4 Another partial schematic diagram of region C;

[0071] Figure 25 yes Figure 24 Cross-sectional view along the HH' direction;

[0072] Figure 26 yes Figure 4 Another partial schematic diagram of region C;

[0073] Figure 27 yes Figure 26 Cross-sectional view along direction II';

[0074] Figure 28 yes Figure 4 Another partial schematic diagram of region C;

[0075] Figure 29 yes Figure 28 Cross-sectional view along the JJ' direction;

[0076] Figure 30 yes Figure 4 Another partial schematic diagram of region C;

[0077] Figure 31 yes Figure 30 Cross-sectional view along the KK' direction;

[0078] Figure 32 yes Figure 5 Another cross-sectional view along the BB' direction;

[0079] Figure 33 This is a schematic diagram of a blocking structure provided in an embodiment of this application;

[0080] Figure 34 yes Figure 5 Cross-sectional view along the LL' direction;

[0081] Figure 35 yes Figure 5 Cross-sectional view along the MM' direction;

[0082] Figure 36 This is a schematic diagram of the structure of a display device provided in an embodiment of this application. Detailed Implementation

[0083] To make the objectives, technical solutions, and advantages of this application clearer, the embodiments of this application will be described in further detail below with reference to the accompanying drawings.

[0084] Figure 1 This is a schematic diagram of the structure of a display panel provided in an embodiment of this application. (Reference) Figure 1 The display panel 100 includes a substrate 101 and a driving circuit layer 102. The display panel 100 may include a display side and a non-display side. The display side can be used to display images.

[0085] Figure 2 This is a top view of a substrate provided in an embodiment of this application. (Reference) Figure 2 The substrate 101 includes a display area 101a and a peripheral area 101b surrounding the display area 101a. The peripheral area 101b may include a bending area 101b1 and a transition area 101b2 located between the display area 101a and the bending area 101b1. The portion of the display panel 100 located in the bending area 101b1 is bent to bend a portion of the display panel 100 to the non-display side, thereby reducing the bezel size of the display panel 100.

[0086] Figure 3 This is a schematic diagram of a partial cross-sectional structure of a display panel in the display area provided in an embodiment of this application. Figure 4 This is a partial top view of the surrounding area of ​​a display panel provided in an embodiment of this application. Figure 5 yes Figure 4 A partial schematic diagram of area A. Figure 6 yes Figure 5 Cross-sectional view along the BB' direction. Wherein, Figure 3 It can be Figure 2 A schematic diagram of a local cross-section in region P1. Figure 4 It can be Figure 2 A partial top view of area P2. (Reference) Figure 1 ,as well as Figures 3 to 6 The driving circuit layer 102 is located on one side of the substrate 101. The driving circuit layer 102 includes a first conductive layer 1021 and a first insulating layer 1022 stacked in a direction away from the substrate 101. Furthermore, referring to… Figure 6 The driving circuit layer 102 further includes a second conductive layer 1023 and a second insulating layer 1024 stacked in a direction away from the substrate 101. Figure 6 The second insulating layer 1024 is not shown.

[0087] The orthographic projection of the portion of the second conductive layer 1023 located in the display area 101a onto the substrate 101 overlaps with the orthographic projection of the portion of the first conductive layer 1021 located in the display area 101a onto the substrate 101.

[0088] Optional, see reference Figure 6 The second conductive layer 1023 and the second insulating layer 1024 may be located between the substrate 101 and the first conductive layer 1021. Alternatively, refer to... Figure 7 The second conductive layer 1023 and the second insulating layer 1024 are located on the side of the first insulating layer 1022 away from the substrate 101. Figure 7 The first insulating layer 1022 is not shown in the diagram.

[0089] In this embodiment, the display panel 100 may include signal traces. One end of the signal trace is connected to the pixel circuit Z1 in the driving circuit layer 102 of the display area 101a, and the signal trace is also located in the bending area 101b1 and on the side of the bending area 101b1 away from the display area 101a. The other end of the signal trace is connected to a driving chip disposed on the side of the bending area 101b1 of the peripheral area 101b away from the display area 101a. Thus, the driving chip can transmit driving signals to the pixel circuit Z1 through the signal traces, thereby causing the pixel circuit Z1 to drive the light-emitting unit Z2 to emit light.

[0090] The bending area 101b1 of the display panel 100 includes an inner bending side and an outer bending side when bent. The inner bending side can be the side of the bending area 101b1 of the display panel 100 that is compressed when bent, such as the non-display side of the display panel 100. The outer bending side can be the side of the bending area 101b1 of the display panel that is stretched when bent, such as the display side of the display panel 100. The outer bending curvature of the outer bending side is greater than the inner bending curvature of the inner bending side.

[0091] Since the signal trace is still located in the bending area 101b1, the signal trace will also bend accordingly when the display panel 100 is bent. Therefore, in order to reduce the possibility of cracks in the signal trace due to bending, the portion of the signal trace located in the bending area 101b1 can be positioned close to the bending neutral layer in the film layer of the display panel 100 located in the bending area 101b1. The length of the bending neutral layer before bending is the same as the length after bending.

[0092] Because the inner side of the bending area 101b1 of the display panel 100 is compressed and the outer side is stretched during the bending process, there must be a layer in the film layer of the display panel 100 located in the bending area 101b1 that is neither compressed nor stretched. This layer, which is neither compressed nor stretched, can be called the bending neutral layer. In this embodiment, the portion of the signal trace located in the bending area 101b1 is positioned close to the bending neutral layer, which can avoid the signal trace from generating large bending strain when the display panel 100 is bent, and reduce the risk of cracking of the signal trace.

[0093] In this embodiment, the first conductive layer 1021 can be a bending neutral layer in the film layer of the display panel 100 located in the bending region 101b1. Therefore, the first conductive layer 1021 can include a second trace portion 10211 located in the bending region 101b1. The second trace portion 10211 can be at least a portion of the signal trace located in the bending region 101b1. The provision of the second trace portion 10211 can prevent the signal trace from generating large bending strain when the display panel 100 is bent.

[0094] To improve the reliability of signal routing, signal traces can be routed using a second conductive layer 1023 in the transition area 101b2 of the display panel 100. The second conductive layer 1023 includes a first trace portion 10231 located in the transition area 101b2. To ensure signal connectivity, the second trace portion 10211 in the first conductive layer 1021 may further include a connection portion 10211a located in the transition area 101b2. Furthermore, the connection portion 10211a of the second trace portion 10211 in the transition area 101b2 can be electrically connected to the first trace portion 10231, enabling the signal trace to transition from the second conductive layer 1023 to the first conductive layer 1021.

[0095] In this embodiment, the first insulating layer 1022 and / or the second insulating layer 1024 cover the side a of the connection portion 10211a near the display area 101a. That is, the first insulating layer 1022 and / or the second insulating layer 1024 can be used to protect the side a of the connection portion 10211a near the display area 101a. Furthermore, the thickness of the insulating layer portion of the first insulating layer 1022 and / or the second insulating layer 1024 covering the side a of the connection portion 10211a near the display area 101a in the direction perpendicular to the surface of the substrate 101 is greater than a thickness threshold. The thickness of the film layer in this embodiment can refer to the thickness in the direction perpendicular to the surface of the substrate 101.

[0096] Optionally, the thickness of the first conductive layer 1021 can range from 0.5 μm (micrometers) to 0.8 μm, for example, the thickness of the first conductive layer 1021 can be 0.6 μm or 0.7 μm. The thickness of the single insulating layer can range from 1.2 μm to 2.5 μm, for example, it can be 1.5 μm or 2 μm. For example, the thickness of both the first insulating layer 1022 and the second insulating layer 1024 can range from 1.2 μm to 2.5 μm.

[0097] Optionally, the thickness threshold can be greater than or equal to 0.2 μm. For example, the insulating layer portion of the connection portion 10211a on the side away from the substrate 101 and covering the side a of the connection portion 10211a near the display area 101a has a thickness greater than 0.3 μm in the direction perpendicular to the surface of the substrate 101.

[0098] Because the insulating layer portion of the first insulating layer 1022 and / or the second insulating layer 1024 located on the side of the connection portion 10211a away from the substrate 101 and covering the side a of the connection portion 10211a near the display area 101a has a larger thickness in the direction perpendicular to the surface of the substrate 101, it can be ensured that the side a of the connection portion 10211a will not be exposed, thereby avoiding abnormal morphology of the side a due to exposure of the side a of the connection portion 10211a, ensuring the yield of other film layers on the side of the connection portion 10211a away from the substrate 101, and ensuring the reliability of the display panel 100.

[0099] In summary, this application provides a display panel including a substrate and a driving circuit layer. The first conductive layer in the driving circuit layer includes a second trace portion located in a transition region and a bending region, and the second conductive layer includes a first trace portion located in the transition region. The first trace portion and the second trace portion can be electrically connected to a connection portion located in the transition region to achieve signal transmission. The insulating layer portion of the first insulating layer and / or the second insulating layer located on the side of the connection portion away from the substrate and covering the side of the connection portion near the display area has a larger thickness in the direction perpendicular to the surface of the substrate. Therefore, it can ensure that the side of the connection portion is not exposed, thereby avoiding abnormal side morphology due to exposure of the side of the connection portion, ensuring the yield of other film layers on the side of the connection portion away from the substrate, and guaranteeing the reliability of the display panel.

[0100] Optionally, in order to further protect the side a of the connection portion 10211a near the display area 101a, the distance between the boundary of the first insulating layer 1022 and / or the second insulating layer 1024 and the side a in a direction parallel to the surface of the substrate 101 can be greater than or equal to 0.3 μm, ensuring that the first insulating layer 1022 and / or the second insulating layer 1024 completely covers the side a of the connection portion 10211a near the display area 101a.

[0101] Optionally, the distance between the boundary and the side a of the first insulating layer 1022 and / or the second insulating layer 1024 away from the substrate in the target direction is greater than or equal to 0.3 μm, ensuring that the first insulating layer 1022 and / or the second insulating layer 1024 completely covers the side a of the connecting portion 10211a near the display area 101a that is away from the substrate. The target direction can be a direction that passes through the side a of the connecting portion 10211a near the display area 101a that is away from the substrate and forms a 45° angle with the surface of the substrate.

[0102] Optionally, the signal traces may include a negative power supply line (VSS trace), a reset signal line (vinit trace), and a positive power supply line (VDD trace). Alternatively, it can be understood that the VSS trace, vinit trace, and VDD trace can all adopt the trace design method in the embodiments of this application to avoid exposing the side of the connection portion located in the first conductive layer near the display area.

[0103] In addition, the signal trace can also be other signal lines that pass through bends, such as a reference voltage signal line (Vref), etc. This application does not specifically limit the type of signal trace in its embodiments.

[0104] refer to Figure 4 As can be seen, the display panel 100 may also include multiple connection interfaces P that are connected to signal traces. Figure 4Multiple connection interfaces are represented by a large rectangle. Different signal traces can be connected to different connection interfaces P to achieve signal transmission.

[0105] In the embodiments of this application, reference is made to Figure 1 and Figure 3 The display panel 100 also includes a light-emitting device layer 103 located on the side of the driving circuit layer 102 away from the substrate 101. The display panel 100 includes a plurality of pixel units Z located in the display area 101a. Each pixel unit Z may include a pixel circuit Z1 and a light-emitting unit Z2. The pixel circuit Z1 may include a plurality of thin-film transistors and at least one storage capacitor. The pixel circuit Z1 in the plurality of pixel units Z may be located in the driving circuit layer 102, and the light-emitting unit Z2 in the plurality of pixel units Z may be located in the light-emitting device layer 103.

[0106] refer to Figure 3 The driving circuit layer 102 includes: a buffer layer n1, an active layer n2, a first gate insulator (GI1) n3, a first gate layer (gate1) n4, a second gate insulator (GI2) n5, a second gate layer (gate2) n6, an inter-level dielectric (ILD) n7, a first source-drain layer (SD1) n8, a first passivation layer (PVX) n9, a first planarization layer (PLN1) n10, a second source-drain layer (SD2) n11, and a second planarization layer (PLN2) n12, which are sequentially stacked along a direction away from the substrate 101.

[0107] The active layer n2 can be a polysilicon layer (P-Si). The active layer includes multiple active patterns of thin-film transistors, each including a source region and a drain region. The first gate layer n4 includes multiple first gate patterns n41 and multiple second gate patterns n42. The first gate pattern n41 can be the gate of a thin-film transistor, and the second gate pattern n42 can be the first electrode of a storage capacitor Cst. The second gate layer n6 includes multiple third gate patterns n61, each serving as the second electrode of the storage capacitor Cst.

[0108] The first source-drain layer n8 includes the source and drain of the thin-film transistor. The source is connected through vias in the interlayer dielectric layer n7, the second gate insulating layer n5, and the first gate insulating layer n3, as well as the source region of the active pattern. The drain is connected through vias in the interlayer dielectric layer n7, the second gate insulating layer n5, and the first gate insulating layer n3, as well as the drain region of the active pattern.

[0109] The second source-drain layer n11 includes a first connection pattern n111, which is connected to the drain of the thin-film transistor through vias in the first planarization layer n10. The first connection pattern n111 is also used to connect the light-emitting unit Z2. For example, the light-emitting unit Z2 can be connected to the first connection pattern n111 through vias in the second planarization layer n12.

[0110] Further reference Figure 8 The driving circuit layer 102 may further include a third source-drain layer (SD3) n13 and a third planarization layer (PLN3) n14 located on the side of the second planarization layer n12 away from the substrate 1011.

[0111] The third source-drain layer n13 includes a second connection pattern n131, which is connected to the first connection pattern n111 through a via in the second planarization layer n12. The second connection pattern n131 is also used to connect the light-emitting unit Z2. For example, the light-emitting unit Z2 can be connected through a via in the third planarization layer n14 and the second connection pattern n131.

[0112] Optionally, the first source / drain layer n8, the second source / drain layer n11, and the third source / drain layer n13 can be a three-layer structure of titanium (Ti), aluminum (Al), and titanium, denoted as Ti / Al / Ti. Since the first source / drain layer n8, the second source / drain layer n11, and the third source / drain layer n13 are made of the same material, the etching solution used to form these three source / drain layers can be similar, for example, the same. It should be noted that the etching rate of aluminum is higher than that of titanium.

[0113] In this embodiment, the light-emitting device layer 103 includes an anode layer m1, a pixel definition layer (PDL) m2, a light-emitting layer m3, and a cathode layer m4, which are sequentially stacked along a direction away from the driving circuit layer 102 and away from the substrate 101.

[0114] The anode layer m1 includes multiple anode patterns m11, which can be connected to a first connecting pattern n111. The pixel defining layer m2 has multiple cutout areas, each of which can be used to expose at least a portion of an anode pattern m11.

[0115] The light-emitting layer m3 may include multiple light-emitting patterns m31, which can be connected through a cutout area and an anode pattern m11. The cathode layer m4 is connected to the light-emitting patterns m31 of multiple light-emitting units Z2.

[0116] Each light-emitting unit Z2 may include an anode pattern m11 located in the anode layer m1 (the anode pattern m11 serves as the anode of the light-emitting unit Z2), a light-emitting pattern m31 located in the light-emitting layer m3 (the light-emitting pattern m31 serves as the light-emitting layer of the light-emitting unit Z2), and a cathode layer m4. The cathode layer m4 of multiple light-emitting units Z2 may be a shared film layer, that is, the cathode layer m4 may serve as the cathode of each light-emitting unit Z2.

[0117] As an optional implementation, refer to Figure 6 The second conductive layer 1023 and the second insulating layer 1024 are located between the substrate 101 and the first conductive layer 1021. Optionally, the second source / drain layer n11 can be the first conductive layer 1021, and the second planarization layer n12 can be the first insulating layer 1022. The first source / drain layer n8 can be the second conductive layer 1023, and the first planarization layer n10 can be the second insulating layer 1024. Furthermore, in this case, the display panel 100 may not need to include the third source / drain layer n13 and the third planarization layer n14; that is, the structure of the display area 101a of the display panel can be referenced... Figure 3 As shown.

[0118] Optionally, since only the first insulating layer 1022 is located on the side of the first conductive layer 1021 away from the substrate 101, the second insulating layer 1024 will not be located on the side of the connection portion 10211a of the second trace portion 10211 of the first conductive layer 1021 away from the substrate 101. Only the first insulating layer 1022 can be located on the side of the connection portion 10211a of the second trace portion 10211 of the first conductive layer 1021 away from the substrate 101. Therefore, to avoid the side a of the connection portion 10211a near the display area 101a being exposed, the thickness d1 of the portion of the first insulating layer 1022 located on the side of the connection portion 10211a away from the substrate 101 and covering the side a of the connection portion 10211a near the display area 101a can be made larger in the direction perpendicular to the surface of the substrate 101. Figure 6 The direction the middle arrow points (leftward) can refer to the direction closer to the display area 101a.

[0119] Typically, during the curing of the second planarization layer n12 (i.e., the first insulating layer 1022), it preferentially flows to the lower-lying areas. Therefore, to ensure that the second planarization layer n12 can protect the side a of the connection portion 10211a, the orthographic projection of the first planarization layer n10 (the second insulating layer 1024) on the substrate 101 and the orthographic projection of the side a of the connection portion 10211a near the display area 101a on the substrate 101 should not overlap. This prevents the side a of the connection portion 10211a near the display area 101a from being located on the side of the second insulating layer 1024 away from the substrate 101, thereby preventing the second insulating layer 1024 from raising the side a of the connection portion 10211a near the display area 101a. Therefore, the first insulating layer 1022 at the location of the side a of the connection portion 10211a near the display area 101a can be avoided from being too thin in the direction perpendicular to the surface of the substrate 101, thus exposing the side a of the connection portion 10211a near the display area 101a. This can prevent abnormal morphology of the side a due to exposure of the side a of the connection portion 10211a, ensure the yield of other film layers on the side of the connection portion 10211a away from the substrate 101, and guarantee the reliability of the display panel 100.

[0120] Among them, reference Figure 9 The abnormal morphology of the side a of the connecting part 10211a near the display area 101a may refer to the following: the etching rate of aluminum by the etching solution is greater than that of titanium, which leads to an undercut structure on the side a of the connecting part 10211a near the display area 101a.

[0121] In some embodiments, reference Figure 6 The first planarization layer n10 (i.e., the second insulating layer 1024) at the location of the connecting portion 10211a is directly removed. Alternatively, it can be understood that the orthographic projection of the second insulating layer 1024 on the substrate 101 and the orthographic projection of the connecting portion 10211a on the substrate 101 do not overlap.

[0122] refer to Figure 6 The first insulating layer 1022 includes a first target insulating portion 10221, and the orthographic projection of the first target insulating portion 10221 on the substrate 101 covers the side a of the connection portion 10211a near the display area 101a.

[0123] exist Figure 6In the illustrated scheme, since the second insulating layer 1024 at the location of the connecting portion 10211a is removed, the presence of the second insulating layer 1024 can prevent the side a of the connecting portion 10211a near the display area 101a from being raised. This prevents the first insulating layer 1022 from flowing into the trench formed by the second insulating layer 1024 during film formation and curing, ensuring that the thickness of the first insulating layer 1022 covering the side a of the connecting portion 10211a near the display area 101a in the direction perpendicular to the surface of the substrate 101 can be relatively thick. This avoids abnormal morphology of the side a due to exposure of the connecting portion 10211a, ensuring the yield of other film layers on the side of the connecting portion 10211a away from the substrate 101, and guaranteeing the reliability of the display panel.

[0124] In some embodiments, reference Figure 10 The connecting portion 10211a wraps the pattern of the first planarization layer n10 (i.e. the second insulating layer 1024) located in the transition region 101b2, thereby making the side a of the connecting portion 10211a closer to the display area 101a closer to the display area 101a than the pattern of the second insulating layer 1024 located in the transition region 101b2.

[0125] For example, the second insulating layer 1024 includes a second target insulating portion 10241 (the second target insulating portion 10241 may refer to the pattern of the second insulating layer 1024 located in the transition region 101b2), a portion of the connecting portion 10211a is located on the side of the second target insulating portion 10241 away from the substrate 101, and the orthographic projection of the connecting portion 10211a on the substrate 101 covers the orthographic projection of the second target insulating portion 10241 on the substrate 101. Furthermore, the orthographic projection of the side a of the connecting portion 10211a near the display area 101a on the substrate 101 is located on the side of the orthographic projection of the second target insulating portion 10241 on the substrate 101 near the display area 101a. Figure 10 The direction the middle arrow points (leftward) can refer to the direction closer to the display area 101a, as shown in the attached diagram below (e.g.). Figure 17 , Figure 19 , Figure 21 , Figure 23 , Figure 25 , Figure 27 , Figure 29 , Figure 31 as well as Figure 32 The direction the arrow in the image points (leftward) can also refer to the direction closer to the display area 101a.

[0126] refer to Figure 10The first insulating layer 1022 includes a first target insulating portion 10221, and the orthographic projection of the first target insulating portion 10221 on the substrate 101 covers the side a of the connection portion 10211a near the display area 101a.

[0127] exist Figure 10 In the illustrated scheme, although the second target insulating portion 10241 of the second insulating layer 1024 located in the transition region 101b2 is not removed, the side a of the connecting portion 10211a near the display area 101a has a lower elevation. Therefore, when the first insulating layer 1022 is formed and cured, it can flow towards the side a of the connecting portion 10211a near the display area 101a. This ensures that the thickness d1 of the first insulating layer 1022 covering the side a of the connecting portion 10211a near the display area 101a can be relatively thick in the direction perpendicular to the surface of the substrate 101. This avoids abnormal morphology of the side a due to exposure of the side a of the connecting portion 10211a, ensuring the yield of other film layers on the side of the connecting portion 10211a away from the substrate 101, and ensuring the reliability of the display panel 100.

[0128] Furthermore, a portion of the connecting portion 10211a is located on the side of the second target insulating portion 10241 away from the substrate 101. Therefore, the second target insulating portion 10241 will elevate this portion of the connecting portion 10211a. Thus, when the first insulating layer 1022 is formed and cured, the portion above this portion of the connecting portion 10211a may be thinner in the direction perpendicular to the surface of the substrate 101, and may even expose the upper surface of this portion of the connecting portion 10211a. However, since the material of the first conductive layer 1021 to which the connecting portion 10211a belongs is titanium, and the etching solution used to form the third source / drain layer has a low etching rate for titanium, the formation of the third source / drain layer has a small impact on the morphology of the connecting portion 10211a.

[0129] In the embodiments of this application, reference is made to Figures 11 to 17 In the case where the driving circuit layer 102 also includes a third planarization layer n14, the third planarization layer n14 can serve as a third insulating layer 1025 located on the side of the first insulating layer 1022 away from the substrate 101. For example, the third insulating layer 1025 includes a third target insulating portion 10251 located at least in the transition region 101b2, and the orthographic projection of the third target insulating portion 10251 on the substrate 101 may overlap with the orthographic projection of the connecting portion 10211a on the substrate 101.

[0130] Due to the above Figure 6 and Figure 10The design in the scheme can ensure that the side a of the connection portion 10211a near the display area 101a will not be exposed. Therefore, the orthographic projection of the third target insulating portion 10251 on the substrate 101 can cover the side a of the connection portion 10211a near the display area 101a, or it can not cover the side a of the connection portion 10211a near the display area 101a.

[0131] Optional, see reference Figures 11 to 19 The third target insulating portion 10251 is located near the boundary b of the display area 101a, the first target insulating portion 10221 is located near the boundary c of the display area 101a, and the side a of the connecting portion 10211a near the display area 101a is arranged sequentially in a direction away from the display area 101a. That is, the third target insulating portion 10251 can be located on the side of the connecting portion 10211a away from the substrate 101, and can also cover the side a of the connecting portion 10211a near the display area 101a. In this case, the third target insulating portion 10251, like the first target insulating portion 10221, can also serve as an insulating layer portion protecting the side a of the connecting portion 10211a near the display area 101a. Figure 17 yes Figures 11 to 16 Cross-sectional view along the DD' direction. Figure 19 yes Figure 18 Cross-sectional view along the EE' direction.

[0132] For ease of illustration, the following is adopted: Figures 11 to 16 The dashed boxes in the diagram represent different film layers or components. (See reference) Figure 11 The dashed box indicates the excavation area of ​​the first leveling layer. That is, label PLN1 can refer to the boundary of the first leveling layer. The upper left, lower left, and upper right areas formed by the intersection of the two boundaries constitute the excavation area of ​​the first leveling layer. (Reference) Figure 12 The dashed box represents the second trace section 10211, specifically the left-hand area comprised of SD1 / SD2 and SD1. (Reference) Figure 13 The dashed box represents the first trace portion 10231, specifically the lower left area comprised of labels SD1 / SD2 and SD2 / a. Label SD2 / a further indicates the side of the connecting portion 10211a near the display area 101a. (Reference) Figure 14 The dashed box indicates the area to be removed from the third planarization layer. Specifically, the upper area marked PLN3 / b is the area to be removed from the third planarization layer. PLN3 / b also indicates the boundary b of the third target insulation portion 10251 near the display area 101a. (Reference) Figure 15The dashed box indicates the area to be removed from the second planarization layer, specifically the upper area marked PLN2 / c. PLN2 / c also indicates the boundary c of the first target insulating portion 10221 near the display area 101a. (Reference) Figure 16 The dashed box represents the area where the first passivation layer n9 was removed, that is, the lower left area formed by the two labeled PVX1 is the area where the first passivation layer n9 was removed.

[0133] Figure 18 The meanings of the various labels in the text can be similar to those described above. Figures 11 to 16 Detailed explanation. In Figure 18 In the diagram, the upper area marked PLN1-1 is the removal area for the first planarization layer, and the lower left area marked PLN1-2 is also the removal area for the first planarization layer. The left side area marked SD1 / SD2 and SD1 is the second wiring portion 10211. The lower left area marked SD1 / SD2 and SD2 / a is the first wiring portion 10231. SD2 / a also indicates the side of the connection portion 10211a near the display area 101a. The upper area marked PLN3 / b is the removal area for the third planarization layer, and PLN3 / b also indicates the boundary b of the third target insulation portion 10251 near the display area 101a. The upper area marked PLN2 / c is the removal area for the second planarization layer, and PLN2 / c also indicates the boundary c of the first target insulation portion 10221 near the display area 101a. The lower left region, marked with two labels PVX1, is the area where the first passivation layer n9 was removed.

[0134] Or, refer to Figure 20 , Figure 21 , Figure 22 and Figure 23 The first target insulating portion 10221 is located near the boundary c of the display area 101a, the third target insulating portion 10251 is located near the boundary b of the display area 101a, and the side a of the connecting portion 10211a near the display area 101a is arranged sequentially in a direction away from the display area 101a. That is, the third target insulating portion 10251 can be located on the side of the connecting portion 10211a away from the substrate 101, and can cover the side a of the connecting portion 10211a near the display area 101a, but does not cover the boundary c of the first target insulating portion 10221 near the display area 101a. In this case, the third target insulating portion 10251, like the first target insulating portion 10221, can also serve as an insulating layer portion protecting the side a of the connecting portion 10211a near the display area 101a. Figure 21 yes Figure 20 Cross-sectional view along the FF' direction. Figure 23 yes Figure 22Cross-sectional view along the GG' direction.

[0135] Figure 20 The meanings of the various labels in the text can be similar to those described above. Figures 11 to 16 Detailed explanation. In Figure 20 In the diagram, PLN1 can refer to the boundary of the first planarization layer. The upper left, lower left, and upper right regions formed by the intersection of the two boundaries are the removal areas of the first planarization layer. The left-side region formed by SD1 / SD2 and SD1 is the second routing portion 10211. The lower left region formed by SD1 / SD2 and SD2 / a is the first routing portion 10231. SD2 / a also indicates the side of the connection portion 10211a near the display area 101a. The upper region formed by PLN3 / b is the removal area of ​​the third planarization layer. PLN3 / b also indicates the boundary b of the third target insulation portion 10251 near the display area 101a. The upper region formed by PLN2 / c is the removal area of ​​the second planarization layer. PLN2 / c also indicates the boundary c of the first target insulation portion 10221 near the display area 101a. The lower left region, marked with two labels PVX1, is the area where the first passivation layer n9 was removed.

[0136] Figure 22 The meanings of the various labels in the text can be similar to those described above. Figures 11 to 16 Detailed explanation. In Figure 22 In the diagram, the upper area marked PLN1-1 is the removal area for the first planarization layer, and the lower left area marked PLN1-2 is also the removal area for the first planarization layer. The left side area marked SD1 / SD2 and SD1 is the second wiring portion 10211. The lower left area marked SD1 / SD2 and SD2 / a is the first wiring portion 10231. SD2 / a also indicates the side of the connection portion 10211a near the display area 101a. The upper area marked PLN3 / b is the removal area for the third planarization layer, and PLN3 / b also indicates the boundary b of the third target insulation portion 10251 near the display area 101a. The upper area marked PLN2 / c is the removal area for the second planarization layer, and PLN2 / c also indicates the boundary c of the first target insulation portion 10221 near the display area 101a. The lower left region, marked with two labels PVX1, is the area where the first passivation layer n9 was removed.

[0137] Or, refer to Figure 24 , Figure 25 , Figure 26 and Figure 27The first target insulating portion 10221 is located near the boundary c of the display area 101a, the connecting portion 10211a is located near the side a of the display area 101a, and the third target insulating portion 10251 is located near the boundary b of the display area 101a, arranged sequentially in a direction away from the display area 101a. That is, the third target insulating portion 10251 can be located on the side of the connecting portion 10211a away from the substrate 101, and does not cover the side a of the connecting portion 10211a near the display area 101a, but does not cover the boundary c of the first target insulating portion 10221 near the display area 101a. In this case, the first target insulating portion 10221 serves solely as an insulating layer portion protecting the side a of the connecting portion 10211a near the display area 101a. Figure 25 yes Figure 24 Cross-sectional view along the HH' direction. Figure 27 yes Figure 26 Cross-sectional view along direction II'.

[0138] Figure 22 The meanings of the various labels in the text can be similar to those described above. Figures 11 to 16 Detailed explanation. In Figure 24 In the diagram, PLN1 can refer to the boundary of the first planarization layer. The upper left, lower left, and upper right regions formed by the intersection of the two boundaries are the removal areas of the first planarization layer. The left-side region formed by SD1 / SD2 and SD1 is the second routing portion 10211. The lower left region formed by SD1 / SD2 and SD2 / a is the first routing portion 10231. SD2 / a also indicates the side of the connection portion 10211a near the display area 101a. The upper region formed by PLN3 / b is the removal area of ​​the third planarization layer. PLN3 / b also indicates the boundary b of the third target insulation portion 10251 near the display area 101a. The upper region formed by PLN2 / c is the removal area of ​​the second planarization layer. PLN2 / c also indicates the boundary c of the first target insulation portion 10221 near the display area 101a. The lower left region, marked with two labels PVX1, is the area where the first passivation layer n9 was removed.

[0139] Figure 26 The meanings of the various labels in the text can be similar to those described above. Figures 11 to 16 Detailed explanation. In Figure 26In the diagram, the upper area marked PLN1-1 is the removal area for the first planarization layer, and the lower left area marked PLN1-2 is also the removal area for the first planarization layer. The left side area marked SD1 / SD2 and SD1 is the second wiring portion 10211. The lower left area marked SD1 / SD2 and SD2 / a is the first wiring portion 10231. SD2 / a also indicates the side of the connection portion 10211a near the display area 101a. The upper area marked PLN3 / b is the removal area for the third planarization layer, and PLN3 / b also indicates the boundary b of the third target insulation portion 10251 near the display area 101a. The upper area marked PLN2 / c is the removal area for the second planarization layer, and PLN2 / c also indicates the boundary c of the first target insulation portion 10221 near the display area 101a. The lower left region, marked with two labels PVX1, is the area where the first passivation layer n9 was removed.

[0140] As another alternative implementation, refer to Figure 28 and Figure 29 The second conductive layer 1023 and the second insulating layer 1024 are located between the substrate 101 and the first conductive layer 1021, and the orthographic projection of the second insulating layer 1024 on the substrate 101 overlaps with the orthographic projection of the side a of the connection portion 10211a near the display area 101a on the substrate 101. In this case, in order to ensure that the insulating layer portion above the side a of the connection portion 10211a near the display area 101a has a thicker thickness d1 in the direction perpendicular to the surface of the substrate 101, the display panel 100 can include a third insulating layer 1025 located on the side of the first insulating layer 1022 away from the substrate 101. The third insulating layer 1025 includes a third target insulating portion 10251. The orthographic projection of the third target insulating portion 10251 onto the substrate 101 covers the orthographic projection of the side a of the connecting portion 10211a near the display area 101a onto the substrate 101. Furthermore, the boundary b of the third target insulating portion 10251 near the display area 101a is closer to the display area 101a than the side a of the connecting portion 10211a near the display area 101a. Figure 29 yes Figure 28 Cross-sectional view along the JJ' direction.

[0141] Therefore, the third target insulating portion 10251, like the first target insulating portion 10221, can also serve as an insulating layer portion protecting the side a of the connection portion 10211a near the display area 101a. In this way, the insulating layer portion covering the side a of the connection portion 10211a near the display area 101a can have a thicker thickness d1 in the direction perpendicular to the surface of the substrate 101. This avoids abnormal morphology of the side a due to exposure of the connection portion 10211a, ensuring the yield of other film layers on the side of the connection portion 10211a away from the substrate 101, and guaranteeing the reliability of the display panel.

[0142] Figure 28 The meanings of the various labels in the text can be similar to those described above. Figures 11 to 16 Detailed explanation. In Figure 28 In the diagram, the upper area marked PLN1-1 is the removal area for the first planarization layer, and the lower left area marked PLN1-2 is also the removal area for the first planarization layer. The left side area marked SD1 / SD2 and SD1 is the second wiring portion 10211. The lower left area marked SD1 / SD2 and SD2 / a is the first wiring portion 10231. SD2 / a also indicates the side of the connection portion 10211a near the display area 101a. The upper area marked PLN3 / b is the removal area for the third planarization layer, and PLN3 / b also indicates the boundary b of the third target insulation portion 10251 near the display area 101a. The upper area marked PLN2 / c is the removal area for the second planarization layer, and PLN2 / c also indicates the boundary c of the first target insulation portion 10221 near the display area 101a. The lower left region, marked with two labels PVX1, is the area where the first passivation layer n9 was removed.

[0143] In some embodiments, reference Figure 28 and Figure 29 The first insulating layer 1022 includes a first target insulating portion 10221, the orthographic projection of which onto the substrate 101 covers the side a of the connection portion 10211a near the display area 101a. The boundary c of the first target insulating portion 10221 near the display area 101a is closer to the display area 101a than the boundary b of the third target insulating portion 10251 near the display area 101a. In this case, the third target insulating portion 10251 may expose a portion of the first target insulating portion 10221 near the display area 101a.

[0144] In some embodiments, reference Figure 30 and Figure 31The first insulating layer 1022 includes a first target insulating portion 10221, the orthographic projection of which onto the substrate 101 covers the side a of the connection portion 10211a near the display area 101a. The boundary b of the third target insulating portion 10251 near the display area 101a is closer to the display area 101a than the boundary c of the first target insulating portion 10221 near the display area 101a. In this case, the third target insulating portion 10251 can cover the boundary c of the first target insulating portion 10221 near the display area 101a.

[0145] exist Figure 30 In the diagram, the upper area marked PLN1-1 is the removal area for the first planarization layer, and the lower left area marked PLN1-2 is also the removal area for the first planarization layer. The left side area marked SD1 / SD2 and SD1 is the second wiring portion 10211. The lower left area marked SD1 / SD2 and SD2 / a is the first wiring portion 10231. SD2 / a also indicates the side of the connection portion 10211a near the display area 101a. The upper area marked PLN3 / b is the removal area for the third planarization layer, and PLN3 / b also indicates the boundary b of the third target insulation portion 10251 near the display area 101a. The upper area marked PLN2 / c is the removal area for the second planarization layer, and PLN2 / c also indicates the boundary c of the first target insulation portion 10221 near the display area 101a. The lower left region, marked with two labels PVX1, is the area where the first passivation layer n9 was removed.

[0146] refer to Figure 29 and Figure 31The second insulating layer 1024 includes a second target insulating portion 10241, which is located on the side a of the connection portion 10211a near the display area 101a and close to the substrate 101. That is, the side a of the connection portion 10211a near the display area 101a is raised by the second target insulating portion 10241. When the first insulating layer 1022 is formed and cured, it will flow into the trench formed by the second target insulating portion 10241, which may result in the portion of the first target insulating portion 10221 located on the side a of the connection portion 10211a near the display area 101a having a thinner thickness in the direction perpendicular to the surface of the substrate 101. Therefore, by ensuring that the orthographic projection of the third target insulating layer on the substrate 101 covers the orthographic projection of the side a of the connection portion 10211a near the display area 101a on the substrate 101, even if the thickness of the first target insulating portion 10221 covering the side a of the connection portion 10211a near the display area 101a is relatively thin in the direction perpendicular to the surface of the substrate 101, it is possible to ensure that the insulating layer portion covering the side a of the connection portion 10211a near the display area 101a is relatively thick in the direction perpendicular to the surface of the substrate 101. This avoids abnormal morphology of the side a due to exposure of the side a of the connection portion 10211a, ensures the yield of other film layers on the side of the connection portion 10211a away from the substrate 101, and guarantees the reliability of the display panel 100.

[0147] Since there may be alignment errors in the film preparation, in order to ensure that the third target insulating portion 10251 can protect the side a of the connecting portion 10211a near the display area 101a, the distance between the orthographic projection of the boundary b of the third target insulating portion 10251 near the display area 101a on the substrate 101 and the orthographic projection of the side a of the connecting portion 10211a near the display area 101a on the substrate 101 can be large, so as to avoid the problem that the third target insulating portion 10251 cannot cover the side a of the connecting portion 10211a near the display area 101a due to process deviation.

[0148] Optionally, the distance between the orthographic projection of the boundary b of the third target insulating portion 10251 near the display area 101a onto the substrate 101 and the orthographic projection of the side a of the connecting portion 10211a near the display area 101a onto the substrate 101 is greater than or equal to 3 μm (micrometers). For example, the distance between the orthographic projection of the boundary b of the third target insulating portion 10251 near the display area 101a onto the substrate 101 and the orthographic projection of the side a of the connecting portion 10211a near the display area 101a onto the substrate 101 is 5 μm, 10 μm, etc.

[0149] In the embodiments of this application, reference is made to Figure 6 , Figure 7 , Figure 10 , Figure 17 , Figure 19 , Figure 21 , Figure 23 , Figure 25 , Figure 27 , Figure 29 and Figure 31 The driving circuit layer 102 also includes a first passivation layer n9 located between the second conductive layer 1023 (first source-drain layer n8) and the second insulating layer 1024 (first planarization layer n10). The first passivation layer n9 can cover the portion of the first trace portion 10231 in the second conductive layer 1023 that is not covered by the first insulating layer 1022 and / or the second insulating layer 1024.

[0150] Optionally, the first passivation layer n9 can protect the portion of the first trace 10231 located in the transition region 101b2, preventing the first trace 10231 from being exposed and thus preventing damage to the morphology of the first trace 10231.

[0151] As another optional implementation method, refer to Figure 7 The second conductive layer 1023 and the second insulating layer 1024 are located on the side of the first insulating layer 1022 away from the substrate 101. The first trace portion 10231 covers the side a of the connection portion 10211a near the display area 101a, and covers at least a portion of the connection portion 10211a. Optionally, the second source-drain layer n11 can be the first conductive layer 1021, and the second planarization layer n12 can be the first insulating layer 1022. The third source-drain layer n13 can be the second conductive layer 1023, and the third planarization layer n14 can be the third insulating layer 1025. That is, in this case, the display panel 100 can include the third source-drain layer n13 and the third planarization layer n14, that is, the structure of the display area 101a of the display panel 100 can be referred to Figure 8 As shown.

[0152] Since the first trace portion 10231 covers the side a of the connection portion 10211a near the display area 101a and covers at least a portion of the connection portion 10211a, the side a of the connection portion 10211a near the display area 101a can be protected by the first trace portion 10231, and the connection between the first trace portion 10231 and the connection portion 10211a can be achieved.

[0153] Optionally, since the first trace portion 10231 is provided above the side a of the connection portion 10211a near the display area 101a, the etching solution will not remove the portion above the side a of the connection portion 10211a near the display area 101a when etching to form the second conductive layer 1023 (third source / drain layer n13). This avoids the etching solution affecting the side a of the connection portion 10211a near the display area 101a and prevents abnormal morphology of the side a of the connection portion 10211a near the display area 101a. This ensures the yield of other film layers on the side of the connection portion 10211a away from the substrate 101, guaranteeing the reliability of the display panel 100.

[0154] refer to Figure 7 The second insulating layer 1024 includes a second target insulating portion 10241, the boundary of which is closer to the display area 101a than the side a of the connecting portion 10211a near the display area 101a. This allows the second target insulating portion 10241 to cover the side a of the connecting portion 10211a near the display area 101a, providing further protection to the side a of the connecting portion 10211a.

[0155] Optional, see reference Figure 32 The driving circuit layer 102 further includes a second passivation layer n15 located between the second conductive layer 1023 (third source / drain layer n13) and the second insulating layer 1024 (third planarization layer n14). The second passivation layer n15 at least covers the portion of the first trace portion 10231 that is not covered by the second target insulating portion 10241. This allows the second passivation layer n15 to protect the second target insulating portion 10241 from the surface of the substrate 101, avoiding the influence of subsequent processes.

[0156] Of course for Figure 7 In the scheme where a second passivation layer n15 is not provided, since the third source / drain layer n13 is the source / drain layer furthest from the substrate 101 among the three source / drain layers, and the etching solution used for the subsequent film layers is usually different from the etching solution used for the source / drain layers, even if the third source / drain layer n13 is not protected by a second passivation layer n15, the impact on the third source / drain layer n13 when etching the subsequent film layers is relatively small.

[0157] refer to Figure 7 and Figure 32As can be seen, the first planarization layer n10 and the second planarization layer n12 located in the transition region 101b2 are removed. Therefore, there are no trenches formed by the first planarization layer n10 and the second planarization layer n12 on both sides of the side a of the connection portion 10211a near the display area 101a. During the film formation and curing process of the third planarization layer n14 (i.e. the second insulating layer 1024), the third source and drain layer n13 can be well covered.

[0158] It should be noted that if the first passivation layer n9 is not provided on the side of the first source-drain layer n8 away from the substrate 101 in the display panel 100, then if the first source-drain layer n8 is used as the second conductive layer 1023 on which the first trace portion 10231 is provided, the first trace portion 10231 will be etched away during the subsequent etching to form the second source-drain layer n11 and the third source-drain layer n13. Therefore, in this case, the third source-drain layer n13 can be used as the second conductive layer 1023. Of course, it should be noted that if the first passivation layer n9 is provided on the side of the first source-drain layer n8 away from the substrate 101 in the display panel 100, but the first passivation layer n9 is not provided in the transition region 101b2 to protect the first source-drain layer n8, the third source-drain layer n13 can also be used as the second conductive layer 1023.

[0159] In the embodiments of this application, reference is made to Figure 33 The display panel 100 also includes a dam 104 located in the transition region 101b2. The orthographic projection of the dam 104 on the substrate 101 surrounds the display region 101a, and the orthographic projection of the dam 104 on the substrate 101 and the orthographic projections of the first insulating layer 1022 and the second insulating layer 1024 on the substrate 101 are spaced apart.

[0160] Optionally, if the display panel 100 also includes a third insulating layer 1025, the orthographic projection of the blocking structure 104 on the substrate 101 and the orthographic projection of the third insulating layer 1025 on the substrate 101 are also spaced apart.

[0161] Since the organic materials used to fabricate the first insulating layer 1022, the second insulating layer 1024, and the third insulating layer 1025 are typically hydrophilic, by ensuring that the orthographic projections of the first insulating layer 1022, the second insulating layer 1024, and the third insulating layer 1025 onto the substrate 101 are spaced apart from the orthographic projections of the blocking structure 104 onto the substrate 101, the portions of the first insulating layer 1022, the second insulating layer 1024, and the third insulating layer 1025 located on the blocking structure 104 away from the display area 101a do not contact the portions of the blocking structure 104 located near the display area 101a. This reduces the amount of water vapor or oxygen introduced at one end of the signal traces and introduced into the pixel units Z of the display area 101a through the first insulating layer 1022, the second insulating layer 1024, and the third insulating layer 1025, ensuring the yield of the display panel 100 and improving the display effect of the display device.

[0162] The blocking structure 104 can be a ring-shaped structure surrounding the display area 101a, used to block the overflow of organic materials within the area enclosed by the blocking structure 104 in the display panel 100. The blocking structure 104 may include at least one blocking dam. For example, refer to... Figure 33 The blocking structure 104 may include a first blocking dam 1041 and a second blocking dam 1042. The first blocking dam 1041 is located away from the display area 101a relative to the second blocking dam 1042, and the thickness of the first blocking dam 1041 may be greater than the thickness of the second blocking dam 1042. The thickness of the first blocking dam 1041 may refer to the thickness of the first blocking dam 1041 in a direction perpendicular to the surface of the substrate 101. The thickness of the second blocking dam 1042 may refer to the thickness of the second blocking dam 1042 in a direction perpendicular to the surface of the substrate 101.

[0163] By setting two barrier dams, with the thickness of the first barrier dam 1041, which is farther from the display area 101a, being greater than the thickness of the second barrier dam 1042, which is closer to the display area 101a, the overflow of organic materials within the area enclosed by the barrier structure 104 can be further prevented. Of course, the barrier structure 104 may also include one barrier dam or two or more barrier dams, and this embodiment of the application does not limit this.

[0164] Optionally, the orthographic projections of the first barrier dam 1041 and the second barrier dam 1042 on the substrate 101 can both be annular, and the first barrier dam 1041 surrounds the second barrier dam 1042.

[0165] In this embodiment, both the first barrier 1041 and the second barrier 1042 can be formed by patterns in the organic layer of the display panel 100. Furthermore, in order to make the thickness of the first barrier 1041 greater than the thickness of the second barrier 1042, the first barrier 1041 can be formed by more patterns in the organic layer, while the second barrier 1042 can be formed by fewer patterns in the organic layer.

[0166] Optionally, the organic layers in the display panel 100 used to form the barrier layer may include, but are not limited to, a first planarization layer n10, a second planarization layer n12, a third planarization layer n14, and a pixel defining layer m2. Optionally, the first planarization layer n10, the second planarization layer n12, the third planarization layer n14, and the pixel defining layer m2 may all be made of organic materials. For example, they may be made of resin materials.

[0167] For example, the first barrier dam 1041 may include patterns in the first planarization layer n10, the second planarization layer n12, the third planarization layer n14, and the pixel-defining layer. The second barrier dam 1042 may include patterns in the second planarization layer n12, the third planarization layer n14, and the pixel-defining layer. Thus, the first barrier dam 1041 has one more layer of organic pattern than the second barrier dam 1042, allowing the thickness of the first barrier dam 1041 to be greater than the thickness of the second barrier dam 1042, preventing the overflow of organic materials.

[0168] In the embodiments of this application, reference is made to Figure 3 and Figure 8 The display panel 100 further includes an encapsulation film layer 105 located on the side of the light-emitting device layer 103 away from the substrate 101. The encapsulation film layer 105 may include a first film layer 1051, a second film layer 1052, and a third film layer 1053 stacked in a direction away from the substrate 101.

[0169] Optionally, the first film layer 1051 and the third film layer 1053 can be made of inorganic materials, and the second film layer 1052 can be made of organic materials. For example, the first film layer 1051 and the third film layer 1053 can be made of one or more inorganic oxides such as SiNx (silicon nitride), SiOx (silicon oxide), and SiOxNy (silicon oxynitride). The second film layer 1052 can be made of a resin material. The resin can be a thermoplastic resin or a thermosetting resin. Thermoplastic resins can include acrylic (PMMA) resin, and thermosetting resins can include epoxy resin.

[0170] It should be noted that the second film layer 1052 can be located within the area enclosed by the barrier structure 104, and the first film layer 1051 and the third film layer 1053 can cover the area enclosed by the barrier structure 104, and also cover the barrier structure 104. That is, the orthogonal projection of the barrier structure 104 on the substrate 101 is located within the area covered by the encapsulation film layer 105, thereby ensuring that the encapsulation film layer 105 effectively encapsulates the various structures located within the area enclosed by the barrier structure 104.

[0171] In this embodiment, the second film layer 1052 can be fabricated using inkjet printing (IJP). The first film layer 1051 and the third film layer 1053 can be fabricated using chemical vapor deposition (CVD).

[0172] In this embodiment, since the structural design ensures that the side a of the connection portion 10211a near the display area 101a will not be exposed, the undercut structure of the side a of the connection portion 10211a near the display area 101a can be avoided. This can prevent the encapsulation film layer 105 from breaking at the undercut structure and causing encapsulation failure, thus avoiding the problem of growing dark spot (GDS) caused by encapsulation failure.

[0173] refer to Figure 3 and Figure 8 As can be seen, the display panel 100 may further include a touch functional layer 106 located on the side of the encapsulation film layer 105 away from the substrate 101. The touch functional layer 106 includes a touch buffer layer 1061, a first touch conductive layer 1062, a touch insulating layer 1063, a second touch conductive layer 1064, and a touch protective layer 1065, which are sequentially stacked along the direction away from the substrate 101. The first touch conductive layer 1062 may be referred to as the first touch metal (TMA) layer. The touch insulating layer 1063 may be referred to as the dielectric layer (TLD) of the touch screen panel (TSP). The second touch conductive layer 1064 may be referred to as the second touch metal (TMB) layer.

[0174] Optionally, if the display panel 100 includes a touch function layer 106, the display panel 100 can be a touch display panel with flexible multi-layer on cell (FMLOC) technology.

[0175] Optionally, the touch buffer layer 1061 can be made of SiN (silicon nitride). The first touch conductive layer 1062 and the second touch conductive layer 1064 can both be made of a triple-layer structure of Ti (titanium), Al (aluminum), and Ti (titanium), and the materials of the first touch conductive layer 1062 and the second touch conductive layer 1064 can be denoted as Ti / Al / Ti. The touch insulating layer 1063 can be made of SiN (silicon nitride).

[0176] Optionally, the first touch conductive layer 1062 and the second touch conductive layer 1064 may include multiple touch traces, which may form a first touch electrode s1 and a second touch electrode s2 that are insulated from each other.

[0177] Optionally, the first touch conductive layer 1062 includes a bridging electrode s12 of the first touch electrode s1, and the second touch conductive layer 1064 includes a main electrode s11 of the first touch electrode s1 and a second touch electrode s2. The bridging electrode s12 and the main electrode s11 of the first touch electrode s1 are electrically connected through a via in the touch insulating layer 1063.

[0178] Optionally, one of the first touch electrode s1 and the second touch electrode s2 can be a transmitting (TX) electrode, and the other touch electrode can be a sensing (RX) electrode.

[0179] Since the touch function layer 106 is also located on the side of the first conductive layer 1021 away from the substrate 101, by avoiding exposing the side a of the connection portion 10211a of the second trace portion 10211 in the first conductive layer 1021 near the display area 101a, the formed touch function layer 106 can also be prevented from breaking at the undercut structure and affecting the touch effect.

[0180] In this embodiment, since the bending area 101b1 of the display panel 100 needs to be bent, therefore, reference is made to... Figure 34 In order to further avoid the second trace portion 10211 in the first conductive layer 1021 located in the bending area from affecting the bending, the second trace portion 10211 can be made to include multiple sub-trace portions 10211b extending along the first direction X and arranged along the second direction Y. Figure 34 yes Figure 5 A cross-sectional view along the LL' direction. It should be noted, of course, that... Figure 34 The sub-routing section 10211b shown is only illustrative; the actual design can be tailored to the specific needs of the product.

[0181] Figure 35 yes Figure 5 Cross-sectional view along the MM' direction. (Reference) Figure 35It can be seen that the second trace portion 10211 located in the transition region 101b2 can be a sheet-like structure. Among them, Figure 34 and Figure 35 Taking the example that the second conductive layer 1023 and the second insulating layer 1024 can be located between the substrate 101 and the first conductive layer 1021.

[0182] In summary, this application provides a display panel including a substrate and a driving circuit layer. The first conductive layer in the driving circuit layer includes a second trace portion located in a transition region and a bending region, and the second conductive layer includes a first trace portion located in the transition region. The first trace portion and the second trace portion can be electrically connected to a connection portion located in the transition region to achieve signal transmission. The insulating layer portion of the first insulating layer and / or the second insulating layer located on the side of the connection portion away from the substrate and covering the side of the connection portion near the display area has a larger thickness in the direction perpendicular to the surface of the substrate. Therefore, it can ensure that the side of the connection portion is not exposed, thereby avoiding abnormal side morphology due to exposure of the side of the connection portion, ensuring the yield of other film layers on the side of the connection portion away from the substrate, and guaranteeing the reliability of the display panel.

[0183] Figure 36 This is a schematic diagram of the structure of a display device provided in an embodiment of this application. (Reference) Figure 36 The display device includes a power supply component 200 and a display panel 100 as provided in the above embodiment. The power supply component 200 is connected to the display panel 100 and is used to supply power to the display panel 100.

[0184] Optionally, the display device can be an organic light-emitting diode (OLED) display device. The display device can be any suitable display device, including but not limited to mobile phones, tablets, televisions, monitors, laptops, digital photo frames, car navigation systems, and e-readers, as well as any product or component with display functionality.

[0185] Since the display device can have essentially the same technical effects as the display panel described in the previous embodiments, the technical effects of the display panel will not be described again here for the sake of brevity.

[0186] The terminology used in the embodiments section of this application is for explaining the embodiments of this application only and is not intended to limit this application. Unless otherwise defined, the technical or scientific terms used in the embodiments of this application should have the ordinary meaning understood by one of ordinary skill in the art to which this application pertains.

[0187] The Description of Embodiments section of this application describes several embodiments; however, this description is exemplary and not restrictive, and it will be apparent to those skilled in the art that many more embodiments and implementations are possible within the scope of the embodiments described herein. Although many possible combinations of features are shown in the drawings and discussed in the detailed description, many other combinations of the disclosed features are also possible. Unless specifically limited, any feature or element of any embodiment may be used in combination with, or may replace, any feature or element of any other embodiment.

[0188] This application includes and contemplates combinations of features and elements known to those skilled in the art. The embodiments, features, and elements disclosed in this application may also be combined with any conventional features or elements to form a unique inventive scheme as defined by the claims. Any feature or element of any embodiment may also be combined with features or elements from other inventive schemes to form another unique inventive scheme as defined by the claims. Therefore, it should be understood that any feature shown and / or discussed in this application may be implemented individually or in any suitable combination. Therefore, the embodiments are not limited except by the limitations imposed by the appended claims and their equivalents. Furthermore, various modifications and changes may be made within the scope of the appended claims.

[0189] Furthermore, in describing representative embodiments, the specification may have presented methods and / or processes as a specific sequence of steps. However, the method or process should not be limited to the specific order of steps described herein, to the extent that it does not depend on such a specific order. As will be understood by those skilled in the art, other sequences of steps are also possible. Therefore, the specific order of steps set forth in the specification should not be construed as a limitation of the claims. Moreover, the claims concerning the method and / or process should not be limited to the steps performed in the written order, and those skilled in the art will readily understand that these orders can be varied and still remain within the spirit and scope of the embodiments of this application.

[0190] In the accompanying drawings, the size of one or more constituent elements, the thickness of layers, or areas are sometimes exaggerated for clarity. Furthermore, the drawings schematically illustrate ideal examples, and this application is not limited to the shapes or numerical values ​​shown in the drawings.

[0191] The ordinal numbers "first," "second," and "third" used in this specification are for the purpose of avoiding confusion among the constituent elements, not for limiting the quantity. The term "multiple" in this application refers to two or more quantities.

[0192] The thickness range of the film layer in this specification is A to B, which means that the thickness is between A and B, including the two endpoints of A and B.

[0193] In this specification, for convenience, terms such as "middle," "upper," "lower," "front," "rear," "vertical," "horizontal," "top," "bottom," "inner," and "outer" are used to indicate orientation or positional relationships in conjunction with the accompanying drawings. This is solely for the purpose of facilitating the description and simplification, and does not imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation. Therefore, it should not be construed as a limitation of this application. The positional relationships of the constituent elements may be appropriately varied depending on the orientation of the described constituent elements. Therefore, the use of terms not limited to those described in the specification may be appropriately replaced as needed.

[0194] In this specification, unless otherwise expressly specified and limited, the terms "connected" or "linked" should be interpreted broadly. For example, it can refer to a fixed connection, a detachable connection, or an integral connection; it can refer to a mechanical connection or an electrical connection; it can refer to a direct connection, an indirect connection via an intermediate component, or a connection within two components. Those skilled in the art will understand the meaning of the above terms in this application according to the specific circumstances.

[0195] In this specification, a transistor is a device that includes at least three terminals: a gate electrode, a drain electrode (drain terminal, drain region, or drain), and a source electrode (source terminal, source region, or source). A transistor has a channel region between the drain and source electrodes, and current can flow through the drain electrode, the channel region, and the source electrode. Note that in this specification, the channel region refers to the region through which current primarily flows.

[0196] In this specification, the first terminal of a transistor can be the drain electrode and the second terminal of a transistor can be the source electrode, or vice versa. In cases where transistors with opposite polarities are used or where the current direction changes during circuit operation, the functions of the "source electrode" and "drain electrode" are sometimes interchanged. Therefore, in this specification, the "source electrode" and "drain electrode" can be interchanged, and the "source terminal" and "drain terminal" can be interchanged.

[0197] In this specification, "connection" includes the situation where constituent elements are connected together by a component that has a certain electrical function. There are no particular limitations on the "component that has a certain electrical function," as long as it enables the transmission of electrical signals between the connected constituent elements. Examples of "components that have a certain electrical function" include not only electrodes and wiring, but also switching elements such as transistors, resistors, inductors, capacitors, and other components with various functions.

[0198] In this specification, the terms "film" and "layer" may be interchanged. For example, "conductive layer" may sometimes be replaced with "conductive film." Similarly, "insulating film" may sometimes be replaced with "insulating layer."

[0199] The above description is merely an optional embodiment of this application and is not intended to limit this application. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of this application should be included within the protection scope of this application.

Claims

1. A display panel, wherein, The display panel includes: A substrate, the substrate including a display area and a peripheral area surrounding the display area, the peripheral area including a bending area and a transition area located between the display area and the bending area, the portion of the display panel located in the bending area being bent; A driving circuit layer is located on one side of the substrate. The driving circuit layer includes a first conductive layer and a first insulating layer stacked in a direction away from the substrate. The driving circuit layer also includes a second conductive layer and a second insulating layer stacked in a direction away from the substrate. The orthographic projection of the portion of the second conductive layer in the display area on the substrate and the orthographic projection of the portion of the first conductive layer in the display area on the substrate overlap. The second conductive layer includes a first trace portion located in the transition region, the first conductive layer includes a second trace portion located in the transition region and the bending region, the second trace portion includes a connection portion located in the transition region, the connection portion and the first trace portion are electrically connected, the first insulating layer and / or the second insulating layer cover the side of the connection portion near the display area, and the insulating layer portion of the first insulating layer and / or the second insulating layer covering the side of the connection portion near the display area has a thickness greater than a thickness threshold in the direction perpendicular to the surface of the substrate.

2. The display panel according to claim 1, wherein, The second conductive layer and the second insulating layer are located between the substrate and the first conductive layer; The orthographic projection of the second insulating layer on the substrate and the orthographic projection of the side of the connecting portion near the display area on the substrate do not overlap.

3. The display panel according to claim 2, wherein, The orthographic projection of the second insulating layer on the substrate and the orthographic projection of the connecting portion on the substrate do not overlap; The first insulating layer includes a first target insulating portion, the orthographic projection of which covers the side of the connection portion near the display area.

4. The display panel according to claim 2, wherein, The second insulating layer includes a second target insulating portion, a portion of the connecting portion is located on the side of the second target insulating portion away from the substrate, and the orthographic projection of the connecting portion on the substrate covers the orthographic projection of the second target insulating portion on the substrate; the orthographic projection of the side of the connecting portion near the display area on the substrate is located on the side of the orthographic projection of the second target insulating portion on the substrate near the display area; The first insulating layer includes a first target insulating portion, the orthographic projection of which covers the side of the connection portion near the display area.

5. The display panel according to claim 3 or 4, wherein, The driving circuit layer further includes a third insulating layer located on the side of the first insulating layer away from the substrate. The third insulating layer includes a third target insulating portion, and the orthographic projection of the third target insulating portion on the substrate and the orthographic projection of the connecting portion on the substrate overlap.

6. The display panel according to claim 5, wherein, The third target insulating portion is located near the boundary of the display area, the first target insulating portion is located near the boundary of the display area, and the side of the connecting portion near the display area is arranged sequentially in a direction away from the display area.

7. The display panel according to claim 5, wherein, The first target insulating portion is located near the boundary of the display area, the third target insulating portion is located near the boundary of the display area, and the connecting portion is located on the side of the display area away from the display area in sequence.

8. The display panel according to claim 5, wherein, The first target insulating portion is located near the boundary of the display area, the connecting portion is located near the side of the display area, and the third target insulating portion is located near the boundary of the display area, arranged sequentially in a direction away from the display area.

9. The display panel according to claim 1, wherein, The second conductive layer and the second insulating layer are located between the substrate and the first conductive layer; the orthographic projection of the second insulating layer on the substrate and the orthographic projection of the side of the connection portion near the display area on the substrate overlap; The driving circuit layer further includes a third insulating layer located on the side of the first insulating layer away from the substrate. The third insulating layer includes a third target insulating portion. The orthographic projection of the third target insulating portion on the substrate covers the orthographic projection of the side of the connection portion near the display area on the substrate. The boundary of the third target insulating portion near the display area is closer to the display area than the side of the connection portion near the display area.

10. The display panel according to claim 9, wherein, The first insulating layer includes a first target insulating portion, the orthographic projection of which covers the side of the connection portion near the display area. The boundary of the first target insulating portion near the display area is closer to the display area than the boundary of the third target insulating portion near the display area.

11. The display panel according to claim 10, wherein, The distance between the orthographic projection of the boundary of the third target insulating portion near the display area on the substrate and the orthographic projection of the side of the connecting portion near the display area on the substrate is greater than or equal to 3 μm.

12. The display panel according to claim 9, wherein, The first insulating layer includes a first target insulating portion, the orthographic projection of which covers the side of the connection portion near the display area. The boundary of the third target insulation portion near the display area is closer to the display area than the boundary of the first target insulation portion near the display area.

13. The display panel according to any one of claims 2 to 4, or any one of claims 6 to 12, wherein, The driving circuit layer further includes a first passivation layer located between the second conductive layer and the second insulating layer, wherein the first passivation layer at least covers the portion of the first trace that is not covered by the first insulating layer and / or the second insulating layer.

14. The display panel according to claim 1, wherein, The second conductive layer and the second insulating layer are located on the side of the first insulating layer away from the substrate. The first trace portion covers the side of the connection portion near the display area and covers at least a portion of the connection portion.

15. The display panel according to claim 14, wherein, The second insulating layer includes a second target insulating portion, the boundary of which is closer to the display area than the side of the connecting portion that is closer to the display area.

16. The display panel according to claim 15, wherein, The driving circuit layer further includes a second passivation layer located between the second conductive layer and the second insulating layer, the second passivation layer covering at least the portion of the first trace portion not covered by the second target insulating portion.

17. The display panel according to claim 16, wherein, The second passivation layer is also located between the first trace portion and the second target insulation portion.

18. The display panel according to any one of claims 1 to 4, or any one of claims 6 to 12, or any one of claims 14 to 16, wherein, The display panel also includes a blocking structure located in the transition area; The orthographic projection of the blocking structure on the substrate surrounds the display area, and the orthographic projections of the blocking structure on the substrate and the orthographic projections of the first insulating layer and the second insulating layer on the substrate are spaced apart.

19. The display panel according to any one of claims 1 to 4, or any one of claims 6 to 12, or any one of claims 14 to 16, wherein, The display panel includes multiple pixel units, each pixel unit including a pixel circuit and a light-emitting unit. The pixel circuit includes multiple thin-film transistors and at least one storage capacitor. The driving circuit layer includes the pixel circuits of the multiple pixel units. The driving circuit layer includes a buffer layer, an active layer, a first gate insulating layer, a first gate layer, a second gate insulating layer, a second gate layer, an interlayer dielectric layer, a first source-drain layer, a first passivation layer, a first planarization layer, a second source-drain layer, a second planarization layer, a third source-drain layer, and a third planarization layer stacked along a direction away from the substrate. The active layer includes the active pattern of the plurality of thin-film transistors, and the active pattern includes a source region and a drain region; The first gate layer includes the gate patterns of the plurality of thin-film transistors, and the first plate of the at least one storage capacitor; The second gate layer includes the second substrate of the storage capacitor; The first source-drain layer includes the source and drain of the plurality of thin-film transistors, wherein the source and the source region are connected, and the drain and the drain region are connected; The second source-drain layer includes a plurality of first connection patterns, and the first connection patterns are connected to the drain. The third source-drain layer includes a plurality of second connection patterns, and the second connection patterns are connected to the first connection pattern. Wherein, the second source / drain layer is the first conductive layer, and the second planarization layer is the first insulating layer; when the second conductive layer and the second insulating layer are located between the substrate and the first conductive layer, the first source / drain layer is the second conductive layer, and the first planarization layer is the second insulating layer; when the second conductive layer and the second insulating layer are located on the side of the first insulating layer away from the substrate, the third source / drain layer is the second conductive layer, and the third planarization layer is the second insulating layer.

20. A display device, wherein, The display device includes: a power supply component and a display panel as described in any one of claims 1 to 19; The power supply component is connected to the display panel, and the power supply component is used to supply power to the display panel.

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