Chip tiling structure, wafer

Abstract

A chip layout structure and a wafer, the chip layout structure comprising: a substrate; a first chip unit and a second chip unit, both arranged on the substrate, each chip unit comprising a device region and a pad region arranged along a preset direction; a cutting path arranged in the substrate and located between the first chip unit and the second chip unit; wherein the preset direction of the first chip unit is opposite to the preset direction of the second chip unit, and the pad region of the first chip unit and the pad region of the second chip unit are respectively located on both sides of the cutting path and arranged adjacent to the cutting path, and the device region of the first chip unit and the device region of the second chip unit are respectively located on a side of the respective pad region away from the cutting path. The present application reduces the dispersed cutting path to be processed in the Pad Open cutting operation, thereby significantly shortening the total cutting length, effectively improving the WPH, and improving the cutting operation efficiency.

Description

Technical Field

[0001] This utility model relates to the field of semiconductor technology, and more specifically to a chip panel structure and a wafer. Background Technology

[0002] In the field of semiconductor chip manufacturing and packaging, for chips that require reserved single-sided pads for subsequent packaging operations such as wire bonding, their structure typically includes a device area and a pad area. The device area is where the functional components of the chip are located, and the pad area is where the pads used for electrical connections are located.

[0003] In related technologies, when the chips are arranged in a panel layout, the device area and the pad area are arranged alternately in a repeating pattern of "device area-pad area-device area-pad area" (abbreviated as AB alternating arrangement). Adjacent chip units are separated by dicing channels to meet the process requirements of subsequent cutting and separation.

[0004] However, the existing arrangement has at least the following drawbacks: due to the long total length to be cut in the Pad Open (pad exposed) dicing operation, the number of wafers cut per unit time (WPH) is low, and the dicing efficiency is significantly limited. Utility Model Content

[0005] The utility model description section introduces a series of simplified concepts, which will be further explained in detail in the detailed description section. This utility model description section is not intended to limit the key features and essential technical features of the claimed technical solution, nor is it intended to determine the scope of protection of the claimed technical solution.

[0006] To address the existing problems, this utility model provides a chip panel structure, including:

[0007] Base;

[0008] The first chip unit and the second chip unit are both disposed on the substrate, and each chip unit includes a device area and a pad area arranged along a preset direction;

[0009] A cutting channel is disposed within the substrate and located between the first chip unit and the second chip unit;

[0010] The preset direction of the first chip unit is opposite to that of the preset direction of the second chip unit, and the pad areas of the first chip unit and the second chip unit are respectively located on both sides of the dicing channel and are adjacent to the dicing channel. The device areas of the first chip unit and the second chip unit are respectively located on the side of their respective pad areas away from the dicing channel.

[0011] In some embodiments of this application, the dicing track and the pad areas on both sides constitute a channel area, and the chip panel structure further includes a pad protection layer, which fills the gap between the dicing track and the pad area and the channel area.

[0012] In some embodiments of this application, the material of the pad protective layer includes silicone material.

[0013] In some embodiments of this application, the cutting channel has opposing first and second sides;

[0014] The first side is provided with at least one first chip unit. When the first side is provided with multiple first chip units, the multiple first chip units are arranged along the length extension direction of the dicing channel, and the device areas and pad areas of adjacent first chip units are adjacent to each other.

[0015] The second side has the same number of second chip units as the first chip units on the first side along the length of the cutting channel, and the second chip units on the second side and the first chip units on the first side are symmetrically distributed about the cutting channel.

[0016] In some embodiments of this application, the length extension direction of the cutting channel is perpendicular to the preset direction.

[0017] In some embodiments of this application, the preset direction is the length direction or width direction of the chip unit.

[0018] In some embodiments of this application, the device region includes a transistor, and the pad region includes metal pads for electrically connecting the transistor.

[0019] In some embodiments of this application, the material of the metal pads includes aluminum.

[0020] In another aspect, this utility model provides a wafer on which the chip panel structure described in any one of the above descriptions is provided.

[0021] The chip panel structure and wafer of this application, by reversing the preset directions of the first chip unit and the second chip unit, concentrates the pad areas of the two on both sides of the dicing track and arranges them adjacently, while the device area is located on the side of the pad area away from the dicing track, so that the pad areas corresponding to the same dicing track form a concentrated distribution structure. This layout avoids the scattered distribution on both sides of the dicing track caused by the dispersion of the pad areas, reduces the scattered dicing paths that need to be processed in the Pad Open dicing operation, thereby significantly shortening the total dicing length, effectively increasing the number of wafers diced per unit time (WPH), and improving the dicing operation efficiency. Attached Figure Description

[0022] The following drawings, which are incorporated herein by reference as part of this invention, are provided for understanding the invention. The drawings illustrate embodiments of the invention and their descriptions, serving to explain the principles of the invention.

[0023] In the attached image:

[0024] Figure 1 A schematic diagram of a vertically arranged chip panel structure is shown in the related technology.

[0025] Figure 2 A schematic diagram of a horizontally arranged chip panel structure is shown in the related technology.

[0026] Figure 3 A schematic diagram of a vertically arranged chip panel structure according to a specific embodiment of this application is shown.

[0027] Figure 4 This diagram illustrates a horizontally arranged chip panel structure according to a specific embodiment of this application.

[0028] Figure 5 A schematic diagram of a vertically arranged chip panel structure is shown in another specific embodiment of this application.

[0029] Figure 6 A schematic diagram of a horizontally arranged chip panel structure according to another specific embodiment of this application is shown. Detailed Implementation

[0030] The following description provides numerous specific details to offer a more thorough understanding of this application. However, it will be apparent to those skilled in the art that this application can be practiced without one or more of these details. In other instances, certain technical features well-known in the art have not been described to avoid confusion with this application.

[0031] It should be understood that this application can be implemented in various forms and should not be construed as limited to the embodiments set forth herein. Rather, providing these embodiments will make the disclosure thorough and complete, and will fully convey the scope of this application to those skilled in the art. In the drawings, for clarity, the dimensions and relative dimensions of layers and regions may be exaggerated. The same reference numerals denote the same elements throughout.

[0032] It should be understood that when an element or layer is referred to as "on," "adjacent to," "connected to," or "coupled to" other elements or layers, it may be directly on, adjacent to, connected to, or coupled to other elements or layers, or there may be intervening elements or layers. Conversely, when an element is referred to as "directly on," "directly adjacent to," "directly connected to," or "directly coupled to" other elements or layers, there are no intervening elements or layers. It should be understood that although the terms first, second, third, etc., may be used to describe various elements, components, areas, layers, and / or portions, these elements, components, areas, layers, and / or portions should not be limited by these terms. These terms are only used to distinguish one element, component, area, layer, or portion from another element, component, area, layer, or portion. Therefore, without departing from the teachings of this application, the first element, component, area, layer, or portion discussed below may be referred to as the second element, component, area, layer, or portion.

[0033] Spatial relation terms such as “below,” “under,” “below,” “under,” “above,” “above,” etc., are used herein for convenience of description to describe the relationship between one element or feature shown in the figure and other elements or features. It should be understood that, in addition to the orientation shown in the figure, spatial relation terms are intended to also include different orientations of the device in use and operation. For example, if the device in the figure is flipped, then the element or feature described as “below” or “under” the other element or feature will be oriented “above” the other element or feature. Therefore, the exemplary terms “below” and “under” can include both upper and lower orientations. The device may be otherwise oriented (rotated 90 degrees or otherwise) and the spatial descriptive terms used herein will be interpreted accordingly.

[0034] The terminology used herein is for the purpose of describing particular embodiments only and is not intended to limit the scope of this application. When used herein, the singular forms “a,” “an,” and “the” are also intended to include the plural forms unless the context clearly indicates otherwise. It should also be understood that the terms “comprising” and / or “including,” when used in this specification, identify the presence of the stated features, integers, steps, operations, elements, and / or components, but do not exclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and / or groups. When used herein, the term “and / or” includes any and all combinations of the associated listed items.

[0035] In related technologies, such as Figure 1As shown, taking a chip panel structure arranged along the length direction (which can be regarded as longitudinal) of chip unit 110 as an example, it includes two chip units 110 and two dicing tracks 120. Each chip unit 110 includes a device area 111 and a pad area 112, which are arranged in the pattern of "device area-pad area-dicing track-device area-pad area-dicing track" (abbreviated as AB alternating arrangement).

[0036] like Figure 2 As shown, taking a chip panel structure arranged along the width direction (which can be regarded as horizontal) of the chip unit 110 as an example, it includes two chip units 110 and two dicing tracks 120. Each chip unit 110 includes a device area 111 and a pad area 112, which are arranged in the pattern of "device area-pad area-dicing track-device area-pad area-dicing track" (abbreviated as AB alternating arrangement).

[0037] The existing layout has at least the following drawbacks: due to the long total length to be cut in the Pad Open cutting operation, the WPH is low, and the cutting efficiency is significantly limited.

[0038] On the other hand, a pad protection layer needs to be formed in the pad area 112 to avoid damage. In the current arrangement, the relevant materials need to diffuse through the entire wafer to complete the formation of the pad protection layer during the deposition process, which results in the pad protection layer deposition taking too long and seriously affects the overall process efficiency.

[0039] Therefore, in view of the aforementioned technical problems, this application proposes a chip panel structure, including:

[0040] Base;

[0041] The first chip unit and the second chip unit are both disposed on the substrate, and each chip unit includes a device area and a pad area arranged along a preset direction;

[0042] A cutting channel is disposed within the substrate and located between the first chip unit and the second chip unit;

[0043] The preset direction of the first chip unit is opposite to that of the preset direction of the second chip unit, and the pad areas of the first chip unit and the second chip unit are respectively located on both sides of the dicing channel and are adjacent to the dicing channel. The device areas of the first chip unit and the second chip unit are respectively located on the side of their respective pad areas away from the dicing channel.

[0044] In this embodiment, by reversing the preset directions of the first chip unit and the second chip unit, the pad areas of the two are concentrated on both sides of the dicing track and arranged adjacently, while the device area is located on the side of the pad area away from the dicing track, so that the pad areas corresponding to the same dicing track form a concentrated distribution structure. This layout avoids the scattered distribution on both sides of the dicing track caused by the dispersion of the pad areas, reduces the scattered cutting paths that need to be processed in the Pad Open cutting operation, thereby significantly shortening the total cutting length, effectively increasing the number of wafers cut per unit time (WPH), and improving the cutting operation efficiency.

[0045] To fully understand this application, detailed steps and structures will be presented in the following description to illustrate the technical solutions proposed in this application. Preferred embodiments of this application are described in detail below; however, in addition to these detailed descriptions, this application may have other implementation methods.

[0046] The following is for reference. Figures 3-6 A chip panel structure according to an embodiment of this application is described. The chip panel structure includes:

[0047] Base;

[0048] The first chip unit 201 and the second chip unit 202 are both disposed on the substrate, and each chip unit includes a device area 211 and a pad area 212 arranged along a preset direction.

[0049] The cutting channel 220 is disposed within the substrate and located between the first chip unit 201 and the second chip unit 202;

[0050] The preset direction of the first chip unit 201 is opposite to that of the preset direction of the second chip unit 202. The pad area 212 of the first chip unit 201 and the pad area 212 of the second chip unit 202 are located on both sides of the dicing channel 220 and are adjacent to the dicing channel 220. The device area 211 of the first chip unit 201 and the device area 211 of the second chip unit 202 are located on the side of their respective pad areas 212 away from the dicing channel 220.

[0051] By aligning the first chip unit 201 and the second chip unit 202 in opposite directions, and positioning their pad areas 212 adjacent to each other on both sides of the dicing track 220, a concentrated distribution of the pad areas 212 near the dicing track 220 is achieved. Compared to the dispersed state caused by the alternating arrangement of pad areas 212 and device areas 211 in related technologies, in this structure, the pad areas 212 corresponding to the same dicing track 220 are no longer scattered in multiple locations, but are concentrated on both sides of the dicing track 220 to form a continuous corresponding area, thus eliminating redundant paths of scattered cutting in terms of spatial arrangement.

[0052] The centralized pad distribution described above directly shortens the total length of the Pad Open dicing operation. Since the pad areas 212 on both sides of the dicing path 220 are adjacent and concentrated, there is no need to perform multiple independent cuts on the dispersed pad positions during the dicing process. Only the corresponding boundary between the concentrated pad area 212 and the dicing path 220 needs to be processed, significantly reducing invalid dicing strokes. The reduction in the total dicing length directly increases the number of wafers diced per unit time (WPH), effectively overcoming the efficiency bottleneck caused by the dispersed dicing path in existing technologies, and greatly improving the overall efficiency of the Pad Open dicing operation.

[0053] In some embodiments, such as Figure 3 and Figure 4 As shown, the length extension direction of the cutting channel 220 is perpendicular to the preset direction.

[0054] In some embodiments, the preset direction is the length direction or the width direction of the chip unit.

[0055] For example, such as Figure 3 As shown, a chip panel structure is illustrated, in which chip cells are arranged along their length (which can be considered as longitudinal). In this chip panel structure, the preset direction is the length direction of the chip cells. Figure 4 As shown, a chip panel structure is illustrated, which is arranged along the width direction (which can be considered as horizontal) of the chip cells. In this chip panel structure, the preset direction is the width direction of the chip cells.

[0056] It should also be noted that a pad protective layer needs to be formed in pad area 212 to prevent damage. In chip panel structures in related technologies, such as... Figure 1 and Figure 2 As shown, the dicing channel 120 and the adjacent pad area 112 together constitute the channel area 130. Because the channel area 130 is relatively dispersed, the material of the pad protective layer needs to diffuse throughout the entire wafer to complete the formation of the pad protective layer, which in turn causes the deposition time of the pad protective layer to be too long, seriously affecting the overall process efficiency.

[0057] In some embodiments, such as Figure 3 and Figure 4 As shown, the dicing track 220 and the pad areas 212 on both sides constitute the channel area 230. The chip panel structure also includes a pad protection layer. The pad protection layer is formed by overfilling the channel area 230 with the material of the pad protection layer, so that the pad protection layer fills the gap between the dicing track 220 and the pad area 212 and the channel area 230.

[0058] In this embodiment, the channel region 230 is composed of a dicing channel 220 and two side pad regions 212. The concentrated and continuous distribution of the side pad regions 212 makes the channel region 230 form a wider overall space (compared to the channel region 130 in related technologies, the width of the channel region 230 in this embodiment is increased by nearly 50%). Compared with the fragmented channel region 130 caused by the scattered distribution of the existing dispersed pad regions 112, this concentrated and continuous channel region 230 significantly shortens the diffusion path of the pad protection layer material—the pad protection layer material does not need to diffuse through the entire wafer segment by segment; it only needs to be overfilled within the concentrated channel region 230 to quickly cover all pad regions 212, fundamentally reducing the time required for material diffusion and significantly improving the deposition efficiency of the pad protection layer.

[0059] In addition, in the chip panel structure of the related technology, since the channel area 130 is distributed relatively dispersedly, when the size of the pad area 112 along the die extension direction is small, the dispersed channel area 130 requires frequent positioning adjustments during test pin insertion, which further increases the difficulty of operation.

[0060] In this embodiment, the channel region 230 is composed of the cutting path 220 and the pad regions 212 on both sides. The concentrated and continuous distribution of the pad regions 212 on both sides makes the channel region 230 form a wider overall space (compared to the channel region 130 in related technologies, the width of the channel region 230 in this embodiment is increased by nearly 50%). When the size of the pad region 212 along the die extension direction is small, the concentrated channel region 230 makes the target area for test pin insertion more continuous and regular, reduces the need for frequent positioning adjustments, effectively reduces the difficulty of test pin insertion, and further improves the stability and efficiency of the overall process.

[0061] In some embodiments, the material of the pad protective layer may be an organosilicon material, such as perfluorooctyltrimethoxysilane (FDTS) or any other suitable material, without limitation.

[0062] In some embodiments, device region 211 includes transistors, and pad region 212 includes metal pads for electrically connecting transistors.

[0063] The metal pads can be made of aluminum, copper, silver, etc., and there are no restrictions on the material.

[0064] In some embodiments, the cutting channel 220 has opposing first and second sides;

[0065] At least one first chip unit 201 is provided on the first side. When multiple first chip units 201 are provided on the first side, the multiple first chip units 201 are arranged along the length extension direction of the dicing channel, and the device area 211 between adjacent first chip units 201 is adjacent to each other and the pad area 212 is adjacent to each other.

[0066] The second side has the same number of second chip units 202 as the first chip units 201 on the first side along the length of the cutting channel, and the second chip units 202 on the second side and the first chip units 201 on the first side are symmetrically distributed about the cutting channel 220.

[0067] For example, such as Figure 5 As shown, three first chip units 201 are disposed on the first side of the dicing channel 220. The three first chip units 201 are arranged along the length of the dicing channel, and the device regions 211 and pad regions 212 of adjacent first chip units 201 are adjacent to each other. Similarly, three second chip units 202 are disposed on the second side of the dicing channel 220. The three second chip units 202 are arranged along the length of the dicing channel, and the device regions 211 and pad regions 212 of adjacent second chip units 202 are adjacent to each other. In addition, the second chip units 202 on the second side and the first chip units 201 on the first side are symmetrically distributed about the dicing channel 220.

[0068] For example, such as Figure 6 As shown, two first chip units 201 are provided on the first side of the dicing channel 220. The two first chip units 201 are arranged along the length of the dicing channel, and the device regions 211 and pad regions 212 of adjacent first chip units 201 are adjacent to each other. Similarly, two second chip units 202 are provided on the second side of the dicing channel 220. The two second chip units 202 are arranged along the length of the dicing channel, and the device regions 211 and pad regions 212 of adjacent second chip units 202 are adjacent to each other. In addition, the second chip units 202 on the second side and the first chip units 201 on the first side are symmetrically distributed about the dicing channel 220.

[0069] On the one hand, by concentrating the pad areas 212 of multiple chip units on the first and second sides of the dicing track 220, and with adjacent pad areas 212 being adjacent to each other, a continuous pad concentration area is formed on both sides of the dicing track 220. This centralized arrangement significantly shortens the dispersion path of the Pad Open dicing operation, reduces unnecessary dicing redundancy length, and significantly improves the dicing efficiency per unit time (WPH).

[0070] On the other hand, when the pad areas 212 of multiple chip units are concentrated, the width of their corresponding protection channels increases significantly due to continuous arrangement, and the continuity of the channels is enhanced. This structure allows the material of the pad protection layer (such as FDTS) to quickly cover the entire channel through overfilling, avoiding the time-consuming problem of material needing to diffuse segment by segment under dispersed arrangement, greatly shortening the deposition time of the protection layer and improving the efficiency of the filling operation.

[0071] Furthermore, the device regions 211 and pad regions 212 of multiple chip units are respectively concentrated, making the pad regions 212 that need to be pinned during testing a large-scale, centralized target area. Compared to scattered pad sites in a dispersed arrangement, the centralized pad regions 212 reduce the frequency of alignment adjustments for testing equipment. Especially for scenarios where the pad size is small along the die extension direction, it significantly reduces the alignment difficulty of pinning operations and improves the stability and efficiency of the testing process.

[0072] According to another aspect of this application, a wafer is provided, on which a chip panel structure is disposed.

[0073] The chip panel layout can be implemented as described above, and will not be repeated here.

[0074] In summary, according to the chip panel structure and wafer of the embodiments of this application, by making the preset directions of the first chip unit 201 and the second chip unit 202 opposite, the pad areas 212 of the two are respectively concentrated on both sides of the dicing track 220 and arranged adjacently, while the device area 211 is located on the side of the pad area 212 away from the dicing track 220, so that the pad areas 212 corresponding to the same dicing track 220 form a concentrated distribution structure. This layout avoids the situation of scattered distribution on both sides of the dicing track 220 caused by the dispersion of the pad areas 212, reduces the scattered cutting paths that need to be processed in the Pad Open cutting operation, thereby significantly shortening the total cutting length, effectively increasing the number of wafers cut per unit time (WPH), and improving the cutting operation efficiency.

[0075] Although exemplary embodiments have been described herein with reference to the accompanying drawings, it should be understood that the above exemplary embodiments are merely illustrative and are not intended to limit the scope of this application. Various changes and modifications can be made therein by those skilled in the art without departing from the scope and spirit of this application. All such changes and modifications are intended to be included within the scope of this application as claimed in the appended claims.

[0076] Similarly, it should be understood that, in order to simplify this application and aid in understanding one or more aspects of the application, various features of this application may sometimes be grouped together in a single embodiment, figure, or description thereof in the description of exemplary embodiments of this application. However, this approach should not be construed as reflecting an intention that the claimed application requires more features than are expressly recited in each claim. Rather, as reflected in the corresponding claims, the point of application is that the corresponding technical problem can be solved with fewer features than all of a single disclosed embodiment. Therefore, the claims following the detailed description are hereby expressly incorporated into that detailed description, wherein each claim itself is a separate embodiment of this application.

[0077] Furthermore, those skilled in the art will understand that although some embodiments described herein include certain features but not others included in other embodiments, combinations of features from different embodiments are intended to be within the scope of this application and form different embodiments. For example, in the claims, any one of the claimed embodiments can be used in any combination.

[0078] It should be noted that the above embodiments are illustrative of this application and not limiting of it, and that those skilled in the art can devise alternative embodiments without departing from the scope of the appended claims. In the claims, any reference signs placed between parentheses should not be construed as limiting the claims. The use of the words first, second, and third, etc., does not indicate any order. These words can be interpreted as names.

Claims

1. A chip panel structure, characterized in that, include: Base; The first chip unit and the second chip unit are both disposed on the substrate, and each chip unit includes a device area and a pad area arranged along a preset direction; A cutting channel is disposed within the substrate and located between the first chip unit and the second chip unit; The preset direction of the first chip unit is opposite to that of the preset direction of the second chip unit, and the pad areas of the first chip unit and the second chip unit are respectively located on both sides of the dicing channel and are adjacent to the dicing channel. The device areas of the first chip unit and the second chip unit are respectively located on the side of their respective pad areas away from the dicing channel.

2. The chip panel structure as described in claim 1, characterized in that, The dicing track and the pad areas on both sides constitute a channel area. The chip panel structure also includes a pad protection layer, which fills the gap between the dicing track and the pad area and the channel area.

3. The chip panel structure as described in claim 2, characterized in that, The material of the pad protective layer includes silicone.

4. The chip panel structure as described in claim 1, characterized in that, The cutting channel has a first side and a second side opposite to each other; The first side is provided with at least one first chip unit. When the first side is provided with multiple first chip units, the multiple first chip units are arranged along the length extension direction of the dicing channel, and the device areas and pad areas of adjacent first chip units are adjacent to each other. The second side has the same number of second chip units as the first chip units on the first side along the length of the cutting channel, and the second chip units on the second side and the first chip units on the first side are symmetrically distributed about the cutting channel.

5. The chip panel structure as described in claim 1, characterized in that, The length extension direction of the cutting channel is perpendicular to the preset direction.

6. The chip panel structure as described in claim 1, characterized in that, The preset direction is the length direction or width direction of the chip unit.

7. The chip panel structure as described in claim 1, characterized in that, The device region includes transistors, and the pad region includes metal pads for electrically connecting the transistors.

8. The chip panel structure as described in claim 7, characterized in that, The metal pads are made of aluminum.

9. A wafer, characterized in that, The wafer is provided with a chip panel structure as described in any one of claims 1 to 8.

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