A shared capacitor fingerprint CSP chip package substrate

Abstract

The utility model discloses a kind of common capacitor fingerprint CSP chip packaging substrates, it is used to utilize the packaging substrate of old CSP chip to package new CSP chip, it includes substrate body and multiple silk screen contour marks being set on substrate body, multiple silk screen contour marks are arrayed and arranged in multiple rows and multiple columns, the appearance of silk screen contour mark is the minimum circumscribed rectangle of old CSP chip, the first plane size of the minimum circumscribed rectangle of new CSP chip is between 1 times-2 times the first plane size of the minimum circumscribed rectangle of old CSP chip, the second plane size of the minimum circumscribed rectangle of new CSP chip is between 0 times-1 times the second plane size of the minimum circumscribed rectangle of old CSP chip, new CSP chip is arranged in alternate rows in the first plane size direction of silk screen contour mark, new CSP chip is sequentially arranged in the second plane size direction of silk screen contour mark. Save the cost and time of re-opening substrate, improve new CSP chip initial trial production efficiency, reduce initial trial production cost.

Description

Technical Field

[0001] This utility model relates to the field of chip packaging technology, and more specifically, to a shared capacitive fingerprint CSP chip packaging substrate. Background Technology

[0002] A fingerprint module project needs to go through multiple trial productions before it can enter mass production. The purpose of the first trial production is to install it on a device for structural verification and simple functional verification. As a part of the phone's appearance, the appearance and size of the capacitive fingerprint module may be adjusted during the first trial production. The fingerprint module chip must be packaged using CSP. The utilization rate of the substrate used for packaging is the most critical factor. Therefore, it is necessary to open a new dedicated substrate for each project. However, the mold opening cost of the substrate is high. If the appearance needs to be changed after the first trial production, the substrate needs to be redesigned, resulting in waste. Utility Model Content

[0003] The technical problem to be solved by this invention is how to design a universal packaging substrate so that new CSP chips can be packaged on the packaging substrate of old CSP chips.

[0004] The technical problem to be solved by this utility model is achieved through the following technical solution:

[0005] To address the aforementioned technical problems, this utility model provides a shared capacitive fingerprint CSP chip packaging substrate, which is used to package a new CSP chip using a packaging substrate of an older CSP chip. It includes a substrate body and multiple silkscreen outline marks disposed on the substrate body. The multiple silkscreen outline marks are arranged in a multi-row, multi-column array. The shape of each silkscreen outline mark is the smallest circumscribed rectangle of the older CSP chip. The first planar dimension of the smallest circumscribed rectangle of the new CSP chip is between 1 and 2 times the first planar dimension of the smallest circumscribed rectangle of the older CSP chip. The second planar dimension of the smallest circumscribed rectangle of the new CSP chip is between 0 and 1 times the second planar dimension of the smallest circumscribed rectangle of the older CSP chip. The new CSP chips are arranged in alternating rows along the first planar dimension direction of the silkscreen outline marks, and sequentially along the second planar dimension direction of the silkscreen outline marks.

[0006] In a preferred embodiment of the shared capacitive fingerprint CSP chip packaging substrate provided by this utility model, the first plane dimension is the width and the second plane dimension is the length.

[0007] In a preferred embodiment of the shared capacitive fingerprint CSP chip packaging substrate provided by this utility model, the second plane dimension of the silkscreen outline mark is 11.72 mm, and the first plane dimension of the silkscreen outline mark is 8.92 mm.

[0008] In a preferred embodiment of the shared capacitive fingerprint CSP chip packaging substrate provided by this utility model, the spacing between two adjacent silkscreen outline marks is 0.30 mm.

[0009] In a preferred embodiment of the shared capacitive fingerprint CSP chip packaging substrate provided by this utility model, positioning holes are provided on the edge of the upper surface of the substrate body.

[0010] In a preferred embodiment of the shared capacitive fingerprint CSP chip packaging substrate provided by this utility model, there are four positioning holes, which are respectively disposed at the four vertices of the substrate body.

[0011] In a preferred embodiment of the shared capacitive fingerprint CSP chip packaging substrate provided by this utility model, the positioning hole is circular in shape.

[0012] In a preferred embodiment of the shared capacitive fingerprint CSP chip packaging substrate provided by this utility model, the silkscreen outline markings have 7 rows and 19 columns.

[0013] In a preferred embodiment of the shared capacitive fingerprint CSP chip packaging substrate provided by this utility model, the substrate body is provided with a plurality of feature marks.

[0014] In a preferred embodiment of the shared capacitive fingerprint CSP chip packaging substrate provided by this utility model, the feature mark is cross-shaped.

[0015] This utility model has the following beneficial effects:

[0016] Since the shape of the silkscreen outline marking is set according to the minimum outer rectangle of the old CSP chip, the new CSP chip is packaged in a row-separated manner in this structure and cut in a row-separated manner according to the drawings. Although the substrate utilization rate is reduced, there is no need to re-open the substrate. After the initial trial production and confirmation that the appearance of the module will not change, the design and mold opening of the special substrate will be carried out, thereby saving the cost and time of re-opening the substrate, improving the efficiency of the initial trial production of the new CSP chip, and reducing the initial trial production cost. Attached Figure Description

[0017] To more clearly illustrate the solutions in this application, the accompanying drawings used in the description of the embodiments will be briefly introduced below. Obviously, the accompanying drawings described below are some embodiments of this application. For those skilled in the art, other drawings can be obtained from these drawings without creative effort.

[0018] Figure 1This is a schematic diagram of a conventional CSP chip packaging structure for a shared capacitive fingerprint CSP chip packaging substrate provided by this utility model.

[0019] Figure 2 for Figure 1 Enlarged view of point A in the middle.

[0020] Figure 3 A schematic diagram of a novel CSP chip packaging structure based on a shared capacitive fingerprint CSP chip packaging substrate provided by this utility model.

[0021] Figure 4 for Figure 3 Enlarged view of point B in the middle.

[0022] Explanation of icon numbers:

[0023] 1. Substrate body; 2. Silkscreen outline markings; 100 old CSP chip; 200 new CSP chip; 3. Positioning hole; 4. Feature markings. Detailed Implementation

[0024] To enable those skilled in the art to better understand the present invention, the technical solutions of the present invention will be clearly and completely described below with reference to the accompanying drawings of the embodiments. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort should fall within the protection scope of the present invention.

[0025] In the description of this utility model, it should be understood that the terms "center", "longitudinal", "transverse", "second plane dimension", "first plane dimension", "thickness", "upper", "lower", "front", "rear", "left", "right", "vertical", "horizontal", "top", "bottom", "inner", "outer", "clockwise", "counterclockwise", "axial", "radial", "circumferential", etc., indicating the orientation or positional relationship based on the orientation or positional relationship shown in the accompanying drawings, are only for the convenience of describing this utility model and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation, and therefore should not be construed as a limitation of this utility model.

[0026] Furthermore, the terms "first," "second," and "third" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of indicated technical features. Thus, a feature defined as "first," "second," or "third" may explicitly or implicitly include at least one of that feature. In the description of this utility model, "a plurality of" means at least two, such as two, three, etc., unless otherwise explicitly specified.

[0027] This utility model provides a shared capacitive fingerprint CSP chip packaging substrate, which is used to package a new CSP chip using a packaging substrate of an older CSP chip. It includes a substrate body and multiple silkscreen outline marks disposed on the substrate body. The multiple silkscreen outline marks are arranged in a multi-row, multi-column array. The shape of each silkscreen outline mark is the smallest circumscribed rectangle of the older CSP chip. The first planar dimension of the smallest circumscribed rectangle of the new CSP chip is between 1 and 2 times the first planar dimension of the smallest circumscribed rectangle of the older CSP chip. The second planar dimension of the smallest circumscribed rectangle of the new CSP chip is between 0 and 1 times the second planar dimension of the smallest circumscribed rectangle of the older CSP chip. The new CSP chips are arranged in alternating rows along the first planar dimension direction of the silkscreen outline marks, and sequentially along the second planar dimension direction of the silkscreen outline marks.

[0028] Since the shape of the silkscreen outline marking is set according to the minimum outer rectangle of the old CSP chip, the new CSP chip is packaged in a row-separated manner in this structure and cut in a row-separated manner according to the drawings. Although the substrate utilization rate is reduced, there is no need to re-open the substrate. After the initial trial production and confirmation that the appearance of the module will not change, the design and mold opening of the special substrate will be carried out, thereby saving the cost and time of re-opening the substrate, improving the efficiency of the initial trial production of the new CSP chip, and reducing the initial trial production cost.

[0029] To enable those skilled in the art to better understand the present application, the technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the accompanying drawings. The present invention will be described in detail below with reference to the accompanying drawings and embodiments, examples of which are shown in the drawings, wherein the same or similar reference numerals denote the same or similar elements or elements having the same or similar functions throughout. The embodiments described below with reference to the accompanying drawings are exemplary and intended to explain the present invention, and should not be construed as limiting the present invention.

[0030] Example 1, please refer to Figures 1 to 4This invention provides a shared capacitive fingerprint CSP chip packaging substrate, which is used to package a new CSP chip 200 using the packaging substrate of an old CSP chip 100. It includes a substrate body 1 and multiple silkscreen outline marks 2 disposed on the substrate body 1. The multiple silkscreen outline marks 2 are arranged in a multi-row, multi-column array. The shape of the silkscreen outline marks 2 is the smallest circumscribed rectangle of the old CSP chip 100. The first planar dimension of the smallest circumscribed rectangle of the new CSP chip 200 is between 1 and 2 times (excluding the first planar dimension) of the smallest circumscribed rectangle of the old CSP chip 100. The second planar dimension of the smallest circumscribed rectangle of the new CSP chip 200 is between 0 and 1 times (excluding the second planar dimension) of the smallest circumscribed rectangle of the old CSP chip 100. The new CSP chips 200 are arranged in alternating rows along the first planar dimension direction and sequentially along the second planar dimension direction of the silkscreen outline marks 2. Since the shape of the silkscreen outline mark 2 is set according to the minimum outer rectangle of the old CSP chip 100, the new CSP chip 200 is encapsulated in a row-separated manner in this structure, and the row-separated cutting is carried out according to the drawings. Although the substrate utilization rate is reduced, there is no need to re-open the substrate. After the initial trial production and confirmation that the appearance of the module will not change, the design and mold opening of the special substrate will be carried out to achieve the purpose of sharing the capacitive fingerprint CSP chip packaging substrate. It can be used to encapsulate the new CSP chip 200 or the old CSP chip 100, thereby saving the cost and time of re-opening the substrate, improving the initial trial production efficiency of the new CSP chip 200, and reducing the initial trial production cost.

[0031] The new CSP chip 200 has an arc shape. The rectangular component inside the new CSP chip 200 is a semiconductor die. A semiconductor die is an unpackaged single bare semiconductor chip cut from a wafer. The part between the semiconductor die and the new CSP chip 200 consists of jumpers and pads. The packaging is to connect the functional pins of the semiconductor to the pads by means of jumpers and traces, and then encapsulate and protect the semiconductor die and jumpers.

[0032] Further, the first planar dimension is the width, and the second planar dimension is the length. In this embodiment, the second planar dimension of the silkscreen outline mark 2, i.e., the length, is 11.72 mm, and the first planar dimension of the silkscreen outline mark 2, i.e., the width, is 8.92 mm. In other embodiments, the first planar dimension may also be the length, and the second planar dimension may be the width.

[0033] Furthermore, the minimum cutting gap or cutting path between two adjacent silkscreen outline marks 2 is 0.30mm.

[0034] Example 2, please refer to Figures 1 to 4As a further optimization of Embodiment 1, in this embodiment, positioning holes 3 are provided on the edge of the upper surface of the substrate body 1. There are four positioning holes 3, which are respectively located at the four vertices of the substrate body 1. The positioning holes 3 are circular in shape, so as to facilitate the positioning of the packaging substrate by using the positioning holes 3, thereby improving the positioning efficiency and reducing the positioning cost.

[0035] Furthermore, the silkscreen outline mark 2 has 7 rows and 19 columns. In this embodiment, the new CSP chip 200 has 4 rows and 19 columns after the spacing is set.

[0036] Furthermore, the substrate body 1 is provided with a plurality of feature marks 4, the feature marks 4 being cross-shaped. More preferably, the silkscreen outline mark 2 is also provided with cross-shaped feature marks 4 to facilitate machine recognition and positioning.

[0037] In this utility model, unless otherwise explicitly specified and limited, the terms "installation," "connection," "joining," and "fixing," etc., should be interpreted broadly. For example, they can refer to a fixed connection, a detachable connection, or an integral part; they can refer to a mechanical connection, an electrical connection, or a connection that allows communication between them; they can refer to a direct connection or an indirect connection through an intermediate medium; they can refer to the internal communication of two components or the interaction between two components, unless otherwise explicitly limited. Those skilled in the art can understand the specific meaning of the above terms in this utility model according to the specific circumstances.

[0038] Obviously, the embodiments described above are only some embodiments of this application, not all embodiments. The accompanying drawings show preferred embodiments of this application, but do not limit the patent scope of this application. This application can be implemented in many different forms; rather, the purpose of providing these embodiments is to provide a more thorough and comprehensive understanding of the disclosure of this application. Although this application has been described in detail with reference to the foregoing embodiments, those skilled in the art can still modify the technical solutions described in the foregoing specific embodiments, or make equivalent substitutions for some of the technical features. Any equivalent structures made using the content of this application's specification and drawings, directly or indirectly applied to other related technical fields, are similarly within the scope of patent protection of this application.

Claims

1. A shared capacitive fingerprint CSP chip packaging substrate, characterized in that, It is used to package a new CSP chip using a packaging substrate of an older CSP chip. It includes a substrate body and multiple silkscreen outline marks disposed on the substrate body. The multiple silkscreen outline marks are arranged in multiple rows and columns in an array. The shape of the silkscreen outline marks is the smallest circumscribed rectangle of the older CSP chip. The first planar dimension of the smallest circumscribed rectangle of the new CSP chip is between 1 and 2 times the first planar dimension of the smallest circumscribed rectangle of the older CSP chip. The second planar dimension of the smallest circumscribed rectangle of the new CSP chip is between 0 and 1 times the second planar dimension of the smallest circumscribed rectangle of the older CSP chip. The new CSP chips are arranged in alternating rows in the first planar dimension direction of the silkscreen outline marks, and the new CSP chips are arranged sequentially in the second planar dimension direction of the silkscreen outline marks.

2. The shared capacitive fingerprint CSP chip packaging substrate according to claim 1, characterized in that, The first plane dimension is the width, and the second plane dimension is the length.

3. The shared capacitive fingerprint CSP chip packaging substrate according to claim 2, characterized in that, The second plane dimension of the silkscreen outline mark is 11.72 mm, and the first plane dimension of the silkscreen outline mark is 8.92 mm.

4. The shared capacitive fingerprint CSP chip packaging substrate according to claim 1, characterized in that, The spacing between two adjacent silkscreen outline marks is 0.30mm.

5. The shared capacitive fingerprint CSP chip packaging substrate according to claim 1, characterized in that, The upper surface of the substrate body is provided with positioning holes.

6. The shared capacitive fingerprint CSP chip packaging substrate according to claim 5, characterized in that, There are four positioning holes, which are respectively located at the four vertices of the substrate body.

7. The shared capacitive fingerprint CSP chip packaging substrate according to claim 5, characterized in that, The positioning hole is circular in shape.

8. The shared capacitive fingerprint CSP chip packaging substrate according to claim 1, characterized in that, The silkscreen outline markings have 7 rows and 19 columns.

9. The shared capacitive fingerprint CSP chip packaging substrate according to claim 1, characterized in that, The substrate body has multiple feature marks.

10. The shared capacitive fingerprint CSP chip packaging substrate according to claim 9, characterized in that, The feature mark is cross-shaped.

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