A package substrate of a circular arc CSP chip

Abstract

This utility model discloses a packaging substrate for an arc-shaped CSP chip, comprising a substrate body and multiple arc-shaped dicing contour lines disposed on the substrate body. The arc-shaped dicing contour lines are formed by offsetting the outer contour of the arc-shaped CSP chip by a certain distance. The multiple arc-shaped dicing contour lines are arranged in multiple rows and columns. Multiple arc-shaped dicing contour lines in the same row are arranged sequentially. The arc-shaped dicing contour lines in even-numbered rows are staggered with those in odd-numbered rows. The gap between two adjacent arc-shaped dicing contour lines is 0mm-0.02mm. There are 22 arc-shaped dicing contour lines in odd-numbered rows and 21 arc-shaped dicing contour lines in even-numbered rows, with 7 rows in total. By staggering the arc-shaped dicing contour lines between adjacent rows, the utilization rate of the arc-shaped CSP chip is improved by changing its arrangement, thereby reducing packaging costs and enhancing product competitiveness.

Description

Technical Field

[0001] This utility model relates to the field of chip packaging technology, and more specifically, to a packaging substrate for an arc-shaped CSP chip. Background Technology

[0002] As an external component of the entire device, the essential manufacturing process for capacitive fingerprint chips is packaging. Often, the price of a capacitive fingerprint chip package is equal to or even higher than the price of the fingerprint chip itself. The design of the substrate is related to the overall layout of the capacitive fingerprint chip package, so the higher the utilization rate of the substrate, the more beneficial it is for cost control of the packaging. The traditional layout of capacitive fingerprint chips is usually an array arrangement. This structure has a high utilization rate for square chips, but a low utilization rate for arc-shaped CSP chips. The utilization rate of arc-shaped CSP chips is usually 61.90%, which makes the packaging cost higher and reduces the competitiveness of the product. Utility Model Content

[0003] The technical problem to be solved by this invention is how to change the arrangement of the arc-shaped CSP chip to improve utilization, thereby reducing packaging costs and enhancing product competitiveness.

[0004] The technical problem to be solved by this utility model is achieved through the following technical solution:

[0005] To solve the above-mentioned technical problems, this utility model provides a packaging substrate for an arc-shaped CSP chip, which includes a substrate body and multiple arc-shaped dicing contour lines disposed on the substrate body. The arc-shaped dicing contour lines are formed by offsetting the outer contour of the arc-shaped CSP chip by a certain distance. The multiple arc-shaped dicing contour lines are arranged in multiple rows and columns. The multiple arc-shaped dicing contour lines in the same row are arranged sequentially. The arc-shaped dicing contour lines in even-numbered rows are staggered with those in odd-numbered rows. The gap between two adjacent arc-shaped dicing contour lines is 0mm-0.02mm. There are 22 arc-shaped dicing contour lines in odd-numbered rows and 21 arc-shaped dicing contour lines in even-numbered rows. There are 7 rows of arc-shaped dicing contour lines.

[0006] In a preferred embodiment of the packaging substrate of the arc-shaped CSP chip provided by this utility model, the outline of the arc-shaped cutting channel is a silkscreen line.

[0007] In a preferred embodiment of the packaging substrate for the arc-shaped CSP chip provided by this utility model, the outline of the arc-shaped cutting channel is white.

[0008] In a preferred embodiment of the packaging substrate for the arc-shaped CSP chip provided by this utility model, a working surface is provided on the substrate body, the length of the working surface is 235.59 mm, and the width of the working surface is 71.09 mm.

[0009] In a preferred embodiment of the packaging substrate of the arc-shaped CSP chip provided by this utility model, the arc-shaped cutting contour line is formed by offsetting the outer contour of the arc-shaped CSP chip outward by 0.2mm.

[0010] In a preferred embodiment of the packaging substrate of the arc-shaped CSP chip provided by this utility model, the arc-shaped cutting contour lines in the same row abut against each other, and the gap between two arc-shaped cutting contour lines in adjacent rows is 0.02mm.

[0011] In a preferred embodiment of the packaging substrate for the arc-shaped CSP chip provided by this utility model, positioning holes are provided on the edge of the upper surface of the substrate body.

[0012] In a preferred embodiment of the packaging substrate for the arc-shaped CSP chip provided by this utility model, there are four positioning holes, which are respectively disposed at the four vertices of the substrate body.

[0013] In a preferred embodiment of the packaging substrate for the arc-shaped CSP chip provided by this utility model, the positioning hole is circular in shape.

[0014] In a preferred embodiment of the packaging substrate of the arc-shaped CSP chip provided by this utility model, the substrate body is provided with a plurality of cross-shaped feature marks.

[0015] This utility model has the following beneficial effects:

[0016] Because the arc-shaped dicing contours of even-numbered rows are staggered with those of odd-numbered rows—that is, the arc-shaped dicing contours of even-numbered rows are located between two adjacent arc-shaped dicing contours of their adjacent odd-numbered rows, and the arc-shaped dicing contours of odd-numbered rows are located between two adjacent arc-shaped dicing contours of their adjacent even-numbered rows—the arc-shaped dicing contours of adjacent rows are arranged in a staggered manner. The final substrate utilization rate is 70.81%, which is nearly 10 percentage points higher than the utilization rate before optimization. This is extremely beneficial for cost control. By changing the arrangement of the arc-shaped CSP chips, the utilization rate is improved, thereby reducing packaging costs and enhancing product competitiveness. Attached Figure Description

[0017] To more clearly illustrate the solutions in this application, the accompanying drawings used in the description of the embodiments will be briefly introduced below. Obviously, the accompanying drawings described below are some embodiments of this application. For those skilled in the art, other drawings can be obtained from these drawings without creative effort.

[0018] Figure 1 This is a schematic diagram of the packaging substrate for a traditional arc-shaped CSP chip.

[0019] Figure 2 This is a schematic diagram of the packaging substrate for an arc-shaped CSP chip provided by this utility model.

[0020] Figure 3 for Figure 2 Enlarged view of point A in the middle.

[0021] Explanation of icon numbers:

[0022] 1. Substrate body; 2. Arc-shaped cutting track outline; 100. Arc-shaped CSP chip; 3. Working surface; 4. Positioning hole; 5. Feature mark. Detailed Implementation

[0023] To enable those skilled in the art to better understand the present invention, the technical solutions of the present invention will be clearly and completely described below with reference to the accompanying drawings of the embodiments. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort should fall within the protection scope of the present invention.

[0024] In the description of this utility model, it should be understood that the terms "center", "longitudinal", "transverse", "length", "width", "thickness", "upper", "lower", "front", "rear", "left", "right", "vertical", "horizontal", "top", "bottom", "inner", "outer", "clockwise", "counterclockwise", "axial", "radial", "circumferential", etc., indicating the orientation or positional relationship are based on the orientation or positional relationship shown in the accompanying drawings, and are only for the convenience of describing this utility model and simplifying the description, and are not intended to indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation, and therefore should not be construed as a limitation of this utility model.

[0025] Furthermore, the terms "first," "second," and "third" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of indicated technical features. Thus, a feature defined as "first," "second," or "third" may explicitly or implicitly include at least one of that feature. In the description of this utility model, "a plurality of" means at least two, such as two, three, etc., unless otherwise explicitly specified.

[0026] This utility model provides a packaging substrate for an arc-shaped CSP chip, which includes a substrate body and multiple arc-shaped dicing contour lines disposed on the substrate body. The arc-shaped dicing contour lines are formed by offsetting the outer contour of the arc-shaped CSP chip by a certain distance. The multiple arc-shaped dicing contour lines are arranged in multiple rows and columns. The multiple arc-shaped dicing contour lines in the same row are arranged sequentially. The arc-shaped dicing contour lines in even-numbered rows are staggered with those in odd-numbered rows. The gap between two adjacent arc-shaped dicing contour lines is 0mm-0.02mm. There are 22 arc-shaped dicing contour lines in odd-numbered rows and 21 arc-shaped dicing contour lines in even-numbered rows. There are 7 rows of arc-shaped dicing contour lines.

[0027] Because the arc-shaped dicing contours of even-numbered rows are staggered with those of odd-numbered rows—that is, the arc-shaped dicing contours of even-numbered rows are located between two adjacent arc-shaped dicing contours of their adjacent odd-numbered rows, and the arc-shaped dicing contours of odd-numbered rows are located between two adjacent arc-shaped dicing contours of their adjacent even-numbered rows—the arc-shaped dicing contours of adjacent rows are arranged in a staggered manner. The final substrate utilization rate is 70.81%, which is nearly 10 percentage points higher than the utilization rate before optimization. This is extremely beneficial for cost control. By changing the arrangement of the arc-shaped CSP chips, the utilization rate is improved, thereby reducing packaging costs and enhancing product competitiveness.

[0028] To enable those skilled in the art to better understand the present application, the technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the accompanying drawings. The present invention will be described in detail below with reference to the accompanying drawings and embodiments, examples of which are shown in the drawings, wherein the same or similar reference numerals denote the same or similar elements or elements having the same or similar functions throughout. The embodiments described below with reference to the accompanying drawings are exemplary and intended to explain the present invention, and should not be construed as limiting the present invention.

[0029] Example 1, please refer to Figures 1 to 3This invention provides a packaging substrate for an arc-shaped CSP chip, comprising a substrate body 1 and multiple arc-shaped cutting contour lines 2 disposed on the substrate body 1. The arc-shaped cutting contour lines 2 are formed by offsetting the outer contour of the arc-shaped CSP chip 100 outward by a certain distance. The multiple arc-shaped cutting contour lines 2 are arranged in multiple rows and columns. Multiple arc-shaped cutting contour lines 2 in the same row are arranged sequentially. The arc-shaped cutting contour lines 2 in even-numbered rows are staggered with those in odd-numbered rows. The gap between two adjacent arc-shaped cutting contour lines 2 is 0mm-0.02mm. There are 22 arc-shaped cutting contour lines 2 in odd-numbered rows and 21 arc-shaped cutting contour lines 2 in even-numbered rows. There are 7 rows of arc-shaped cutting contour lines 2. Because the even-numbered rows of arc-shaped cutting contour lines 2 are staggered with the odd-numbered rows of arc-shaped cutting contour lines 2, that is, the even-numbered rows of arc-shaped cutting contour lines 2 are located between two adjacent arc-shaped cutting contour lines 2 in their adjacent odd-numbered rows, and the odd-numbered rows of arc-shaped cutting contour lines 2 are located between two adjacent arc-shaped cutting contour lines 2 in their adjacent even-numbered rows, the arc-shaped cutting contour lines 2 between adjacent rows are staggered, and the final substrate utilization rate is 70.81%, which is nearly 10 percentage points higher than the utilization rate before optimization. This is extremely beneficial for cost control. In this way, by changing the arrangement of the arc-shaped CSP chip 100, the utilization rate is improved, thereby reducing packaging costs and improving the competitiveness of the product.

[0030] Each arc-shaped cutting contour line 2 contains an arc-shaped CSP chip 100, and each arc-shaped CSP chip 100 contains a semiconductor die.

[0031] Furthermore, the arc-shaped cutting contour line 2 is a silkscreen line, and the color of the arc-shaped cutting contour line 2 is white to facilitate machine recognition and positioning.

[0032] Furthermore, a working surface 3 is provided on the substrate body 1. The working surface 3 has a length of 235.59 mm and a width of 71.09 mm to facilitate machine identification, positioning, and operation.

[0033] Furthermore, the arc-shaped cutting track outline 2 is formed by offsetting the outer contour of the arc-shaped CSP chip 100 outward by 0.2mm. The distance between the arc-shaped cutting track outline 2 and the arc-shaped CSP chip 100 is the cutting track, that is, the width of the cutting track is 0.2mm, so as to avoid damage to the arc-shaped CSP chip 100 caused by cutting errors and ensure the product yield of the arc-shaped CSP chip 100.

[0034] Furthermore, the arc-shaped cutting contour lines 2 in the same row abut against each other, and the gap between two arc-shaped cutting contour lines 2 in adjacent rows is 0.02mm.

[0035] Example 2, please refer to Figure 3 As a further optimization of Embodiment 1, in this embodiment, the upper surface of the substrate body 1 is provided with positioning holes 4. There are four positioning holes 4, which are respectively located at the four vertices of the substrate body 1. The positioning holes 4 are circular in shape, so as to facilitate the positioning of the packaging substrate by using the positioning holes 4, thereby improving the positioning efficiency and reducing the positioning cost.

[0036] Furthermore, the substrate body 1 is provided with a plurality of feature marks 5, the feature marks 5 being cross-shaped to facilitate machine identification and positioning.

[0037] In this utility model, unless otherwise explicitly specified and limited, the terms "installation," "connection," "joining," and "fixing," etc., should be interpreted broadly. For example, they can refer to a fixed connection, a detachable connection, or an integral part; they can refer to a mechanical connection, an electrical connection, or a connection that allows communication between them; they can refer to a direct connection or an indirect connection through an intermediate medium; they can refer to the internal communication of two components or the interaction between two components, unless otherwise explicitly limited. Those skilled in the art can understand the specific meaning of the above terms in this utility model according to the specific circumstances.

[0038] Obviously, the embodiments described above are only some embodiments of this application, not all embodiments. The accompanying drawings show preferred embodiments of this application, but do not limit the patent scope of this application. This application can be implemented in many different forms; rather, the purpose of providing these embodiments is to provide a more thorough and comprehensive understanding of the disclosure of this application. Although this application has been described in detail with reference to the foregoing embodiments, those skilled in the art can still modify the technical solutions described in the foregoing specific embodiments, or make equivalent substitutions for some of the technical features. Any equivalent structures made using the content of this application's specification and drawings, directly or indirectly applied to other related technical fields, are similarly within the scope of patent protection of this application.

Claims

1. A packaging substrate for an arc-shaped CSP chip, characterized in that, It includes a substrate body and multiple arc-shaped dicing contour lines disposed on the substrate body. The arc-shaped dicing contour lines are formed by offsetting the outer contour of the arc-shaped CSP chip by a certain distance. The multiple arc-shaped dicing contour lines are arranged in multiple rows and columns. The multiple arc-shaped dicing contour lines in the same row are arranged sequentially. The arc-shaped dicing contour lines in even-numbered rows are staggered with the arc-shaped dicing contour lines in odd-numbered rows. The gap between two adjacent arc-shaped dicing contour lines is 0mm-0.02mm. There are 22 arc-shaped dicing contour lines in odd-numbered rows and 21 arc-shaped dicing contour lines in even-numbered rows. There are 7 rows of arc-shaped dicing contour lines.

2. The packaging substrate for the arc-shaped CSP chip according to claim 1, characterized in that, The outline of the arc-shaped cutting channel is a screen printing line.

3. The packaging substrate for the arc-shaped CSP chip according to claim 2, characterized in that, The outline of the arc-shaped cutting channel is white.

4. The packaging substrate for the arc-shaped CSP chip according to claim 1, characterized in that, The substrate body is provided with a working surface, the length of which is 235.59 mm and the width of which is 71.09 mm.

5. The packaging substrate for the arc-shaped CSP chip according to claim 1, characterized in that, The arc-shaped cutting contour line is formed by offsetting the outer contour of the arc-shaped CSP chip outward by 0.2mm.

6. The packaging substrate for the arc-shaped CSP chip according to claim 1, characterized in that, The arc-shaped cutting contour lines in the same row abut against each other, and the gap between two arc-shaped cutting contour lines in adjacent rows is 0.02mm.

7. The packaging substrate for the arc-shaped CSP chip according to claim 1, characterized in that, The upper surface of the substrate body is provided with positioning holes.

8. The packaging substrate for the arc-shaped CSP chip according to claim 7, characterized in that, There are four positioning holes, which are respectively located at the four vertices of the substrate body.

9. The packaging substrate for the arc-shaped CSP chip according to claim 8, characterized in that, The positioning hole is circular in shape.

10. The packaging substrate for the arc-shaped CSP chip according to claim 1, characterized in that, The substrate body has multiple cross-shaped feature marks.

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