Integrated circuit package

Abstract

An integrated circuit package. The integrated circuit package includes a first die including a first semiconductor substrate and a first interconnect structure on the first semiconductor substrate. The first interconnect structure includes a plurality of first dielectric layers, a plurality of first metallization patterns in the plurality of first dielectric layers, and a first seal ring in the plurality of first dielectric layers. In a top view, the first seal ring surrounds the plurality of first metallization patterns. The first die includes a first bonding layer on the first interconnect structure and a first die connector in the first bonding layer. In a top view, the first seal ring encircles the first die connector. The first die includes a second die connector in the first bonding layer. In a top view, the second die connector is outside the first seal ring.

Description

Technical Field

[0001] This utility model relates to an integrated circuit package, and more particularly to an integrated circuit package including a dummy die connector. Background Technology

[0002] The semiconductor industry has experienced rapid growth due to continuous improvements in the integration density of various electronic components, such as transistors, diodes, resistors, and capacitors. In most cases, this increased integration density is driven by the shrinking minimum feature size, allowing more components to be integrated into a given area. As the demand for miniaturized electronics grows, so too does the need for smaller, more innovative semiconductor die packaging technologies. Utility Model Content

[0003] The purpose of this invention is to provide an integrated circuit package to solve at least one of the above-mentioned problems.

[0004] This utility model provides an integrated circuit package including a first die, comprising: a first semiconductor substrate and a first interconnect structure located on the first semiconductor substrate. The first interconnect structure includes: a plurality of first dielectric layers, a plurality of first metallization patterns in the plurality of first dielectric layers, and a first sealing ring located in the plurality of first dielectric layers. In a top view, the first sealing ring surrounds the plurality of first metallization patterns. The first die includes a first bonding layer located on the first interconnect structure and a first die connector located in the first bonding layer. In a top view, the first sealing ring surrounds the first die connector. The first die includes a second die connector located in the first bonding layer. In a top view, the second die connector is located outside the first sealing ring.

[0005] According to one embodiment of the present invention, the first die connector is electrically coupled to an integrated circuit of the first die.

[0006] According to one embodiment of the present invention, the second die connector is electrically isolated from an integrated circuit of the first die.

[0007] According to one embodiment of the present invention, in the top view, the size of the second die connector is larger than the size of the first die connector.

[0008] According to one embodiment of the present invention, a second die is further included, wherein the second die includes a second internal interconnect structure having a second sealing ring, a second bonding layer located on the second internal interconnect structure and bonded to the first bonding layer, a third die connector located in the second bonding layer and bonded to the first die connector, and a fourth die connector located in the second bonding layer and bonded to the second die connector.

[0009] According to one embodiment of the present invention, in the top view, the second sealing ring surrounds the third die connector, and in the top view, the fourth die connector is located outside the second sealing ring.

[0010] This utility model provides an integrated circuit package including a first die, which includes a first semiconductor substrate and a first interconnect structure located on the first semiconductor substrate. The first interconnect structure includes a first sealing ring, a first bonding layer located on the first interconnect structure, a first die connector located in the first bonding layer, and a second die connector located in the first bonding layer. The first die connector is electrically coupled to the integrated circuit of the first die. The second die connector is electrically isolated from the integrated circuit of the first die. In a top view, the first sealing ring is disposed between the first die connector and the second die connector.

[0011] According to one embodiment of the present invention, in the top view, the first sealing ring surrounds the first die connector.

[0012] According to one embodiment of the present invention, the second die connector is located directly above an exclusion area of ​​the first interconnect structure. Attached Figure Description

[0013] The concept of embodiments of this utility model will be better understood by referring to the following detailed description and the accompanying drawings. It should be noted that, according to standard industry practice, the various features in the drawings are not necessarily drawn to scale. In fact, the dimensions of various features may be arbitrarily enlarged or reduced for clarity. Similar features are designated with similar reference numerals throughout the specification and drawings.

[0014] Figure 1A , Figure 1B , Figure 1C and Figure 1D Cross-sectional and bottom views of an integrated circuit die according to some embodiments of the present invention are shown.

[0015] Figure 2A , Figure 2B , Figure 2C , Figure 2D , Figure 3A , Figure 3B , Figure 3C , Figure 4 , Figure 5 , Figure 6 , Figure 7 , Figure 8 , Figure 9 , Figure 10A , Figure 10B and Figure 10CCross-sectional and top views are shown of intermediate process steps in manufacturing an integrated circuit package according to some embodiments of the present invention.

[0016] The attached figures are labeled as follows:

[0017] 100: On-chip integrated circuit die

[0018] 102: Semiconductor substrate

[0019] 103: Metallized Pattern

[0020] 104: Internal Wiring Structure

[0021] 105: Sealing ring

[0022] 106: Dielectric layer

[0023] 108: Bonding layer

[0024] 109: Area

[0025] 110: Active Die Connector

[0026] 110A: Barrier Sublayer

[0027] 110B: Conductor layer

[0028] 111: Dummy Die Connector

[0029] 111A: Barrier Sublayer

[0030] 111B: Conductor layer

[0031] 112: Carrier

[0032] 114: Adhesive

[0033] 200: Wafer Structure

[0034] 200': Lower integrated circuit die

[0035] 202: Semiconductor substrate

[0036] 203: Metallized Pattern

[0037] 204: Internal Wiring Structure

[0038] 205: Sealing ring

[0039] 206: Dielectric layer

[0040] 207: Conductive via

[0041] 208: Bonding layer

[0042] 209: Area

[0043] 210: Active Die Connector

[0044] 210A: Barrier Sublayer

[0045] 210B: Conductor layer

[0046] 211: Dummy Die Connector

[0047] 211A: Barrier Sublayer

[0048] 211B: Conductor Sublayer

[0049] 212: Carrier

[0050] 213, 214: Bonding layers

[0051] 216, 217: Dielectric layer

[0052] 218: Metallized Pattern

[0053] 219: Redistributed Structure

[0054] 220: Under-bump metal layer

[0055] 221: Electrical connector

[0056] 222: with

[0057] 224: Frame

[0058] 226: Cutting line

[0059] 227: Dielectric layer

[0060] 228: Semiconductor packaged components

[0061] 229: Base

[0062] 230: Conductivity characteristics

[0063] 231: Conductive via

[0064] 232: Electrical conductivity characteristics

[0065] 233: Electrical connector

[0066] 234: Bottom Filler

[0067] 236: Adhesive layer

[0068] 238: Bottom filling

[0069] 240: Electrical connector

[0070] 250: Wafer Structure

[0071] 250': Integrated circuit packaged component

[0072] 275: Active Zone

[0073] 280: Integrated circuit package components

[0074] 282: Reinforcing ring

[0075] 284, 286: Adhesives

[0076] 290: Cover

[0077] 300: Integrated Circuit Package

[0078] A-A', B-B': Reference sections

[0079] D1, D2, D4, D5: Diameter

[0080] T1, T2, T3, T4, T5, T6: Thickness Detailed Implementation

[0081] The following disclosure provides numerous different embodiments or examples to implement various features of the present invention. Reference numerals and / or letters may be repeated in the various examples described herein. These repetitions are for brevity and clarity and do not in themselves imply any relationship between the various disclosed embodiments and / or configurations. Furthermore, specific examples of components and configurations are described below to simplify the description of the embodiments of the present invention. Of course, these specific examples are merely illustrative and not intended to limit the embodiments of the present invention. For example, in the following description, reference to a first feature being formed on or above a second feature indicates that it may include embodiments where the first and second features are in direct contact, or embodiments where additional features are formed between the first and second features, so that the first and second features may not be in direct contact.

[0082] In addition, spatially related terms may be used herein. For example, terms such as “below,” “under,” “lower,” “above,” “higher,” and similar terms are used to describe the relationship between one element or feature shown in the accompanying drawings and another element(s). Besides the orientations shown in the accompanying drawings, these spatially related terms are intended to include different orientations of the device in use or operation. The device may be turned to different orientations (rotated 90 degrees or other orientations), and the spatially related terms used herein may be interpreted in the same way.

[0083] An integrated circuit package and a method of forming the same are provided. According to some embodiments, the integrated circuit package may include one or more upper integrated circuit dies bonded to a lower integrated circuit die. The upper integrated circuit die may include an interconnect structure with a sealing ring, a bonding layer on the interconnect structure, and a dummy die connector located in the bonding layer. In a bottom view, the dummy die connector may be disposed outside a reinforcing ring. The lower integrated circuit die may include an interconnect structure with a sealing ring, a bonding layer on the interconnect structure, and a dummy die connector located in the bonding layer. In a top view, the dummy die connector may be disposed outside a reinforcing ring. By bonding the dummy die connectors of the upper and lower integrated circuit dies, the bonding strength between the upper and lower integrated circuit dies can be enhanced, which can eliminate or reduce the risk of delamination of the upper integrated circuit die during the manufacture and operation of the integrated circuit package. This allows for more effective dissipation of heat generated by the lower integrated circuit die, thereby improving the performance and reliability of the integrated circuit package.

[0084] exist Figure 1A , Figure 1B and Figure 1C The image shows the integrated circuit die 100. Figure 1A The sectional view shown can be viewed along... Figure 1C The reference section A-A' in the bottom view shown is obtained, and Figure 1B The sectional view shown can be viewed along... Figure 1CThe reference section B-B' in the bottom view shown. The integrated circuit die 100 can be a logic die (e.g., a central processing unit (CPU), graphics processing unit (GPU), system-on-chip (SoC), application processor (AP), microcontroller, etc.), a memory die (e.g., a dynamic random access memory (DRAM) die, a static random access memory (SRAM) die, a power management die (e.g., a power management integrated circuit (PMIC) die), a radio frequency (RF) die, a sensor die, a micro-electro-mechanical-system (MEMS) die, a signal processing die (e.g., a digital signal processing (DSP) die), a front-end die (e.g., an analog front-end (AFE) die), or a combination thereof.

[0085] The integrated circuit die 100 may have a semiconductor substrate 102, such as an active layer of doped silicon, undoped silicon, or a semiconductor-on-insulator (SOI) substrate. The semiconductor substrate 102 may include other semiconductor materials, such as germanium, silicon carbide, gallium arsenide, gallium phosphide, indium phosphide, indium arsenide, indium antimonide, SiGe, GaAsP, AlInAs, AlGaAs, GaInAs, GaInP, and / or combinations thereof. Other substrates, such as multilayer substrates or gradient substrates, may also be used. The semiconductor substrate 102 may have an active surface (e.g., Figure 1A The surface facing downwards (which can be referred to as the front side), and the non-active surface (e.g.) Figure 1A The surface facing upwards (the middle side) can be referred to as the rear side. The rear side of the semiconductor substrate 102 can also be referred to as the rear side of the upper integrated circuit die 100, and the front side of the semiconductor substrate 102 can face the front side of the upper integrated circuit die 100.

[0086] Devices (not shown separately) may be disposed on the active surface of semiconductor substrate 102. These devices may be active devices (e.g., transistors, diodes, etc.). These devices may generate significant heat during operation. Interconnect structures 104 may be disposed on the active surface of semiconductor substrate 102. Interconnect structures 104 may interconnect devices to form an integrated circuit on integrated circuit die 100. Interconnect structures 104 may include metallization patterns 103 in dielectric layer 106. Dielectric layer 106 may be a low-k dielectric layer comprising suitable dielectric materials such as silicon dioxide, silicon nitride, silicon oxynitride, etc. Dielectric layer 106 may be formed by suitable deposition processes such as chemical vapor deposition (CVD), atomic layer deposition (ALD), etc. Metallization patterns 103 may include metal lines and vias, which may be formed in dielectric layer 106 by damascene processes such as single damascene processes, dual damascene processes, etc. The metallization pattern 103 can be formed of a suitable conductive material, such as copper, tungsten, aluminum, silver, gold, or combinations thereof. The metallization pattern 103 can be electrically coupled to the device.

[0087] The interconnect structure 104 may also include a sealing ring 105 in the dielectric layer 106. For illustrative purposes, the sealing ring 105 is located in... Figure 1C Shown as dashed lines. In some embodiments, the sealing ring 105 extends through the dielectric layer 106. The sealing ring 105 may surround the metallization pattern 103 in a bottom view, and the region between the sealing ring 105 and the sidewall of the interconnect structure 104 may be referred to as the keep-out zone (KOZ) of the interconnect structure 104. The keep-out zone may not have the metallization pattern 103 formed therein. The sealing ring 105 may be formed of the same or similar material and using the same or similar process as the metallization pattern 103. The sealing ring 105 may be electrically isolated from the integrated circuit of the upper integrated circuit die 100.

[0088] A bonding layer 108 may be disposed on the interconnect structure 104 on the front side of each integrated circuit die 100. The bonding layer 108 may be formed of oxides (e.g., silicon oxide, phosphosilicate glass (PSG), borosilicate glass (BSG), boron-doped phosphosilicate glass (BPSG), tetraethyl orthosilicate-based oxides (TEOS), etc.), nitrides (e.g., silicon nitride), or similar materials. The bonding layer 108 may be formed by processes such as CVD or ALD. One or more passivation layers (not shown separately) may be disposed between the bonding layer 108 and the interconnect structure 104.

[0089] Active die connector 110 and dummy die connector 111 may be disposed in bonding layer 108. Active die connector 110 and dummy die connector 111 may also be referred to as bonding pads and can be used to bond with another integrated circuit die in subsequent processes. Active die connector 110 may be electrically coupled to the metallization pattern 103 and the integrated circuit of the upper integrated circuit die 100. Dummy die connector 111 may be electrically isolated from the integrated circuit of the upper integrated circuit die 100. Figure 1C As shown in the bottom view, the sealing ring 105 may surround the active die connector 110, and in the bottom view, the dummy die connector 111 may be located outside the sealing ring 105 and at an adjacent corner of the upper integrated circuit die 100. The dummy die connector 111 may be located directly above and adjacent to the exclusion area of ​​the interconnect structure 104. The dummy die connector 111 may enhance the bonding strength between the upper integrated circuit die 100 and another integrated circuit die in the region adjacent to the exclusion area of ​​the upper integrated circuit die 100, as will be further explained below.

[0090] The active die connector 110 and the dummy die connector 111 can have circular, polygonal (e.g., rectangular) shapes in a bottom view. In the bottom view, the dummy die connector 111 can be larger than the active die connector 110. Figure 1A , Figure 1B and Figure 1CIn the illustrated embodiment, the active die connector 110 and the dummy die connector 111 have circular shapes. The active die connector 110 may have a diameter D1 ranging from about 5 μm to about 10 μm. The dummy die connector 111 may have a diameter D2 ranging from about 20 μm to about 60 μm, which allows for sufficient bonding strength between the upper integrated circuit die 100 and another integrated circuit die in a region adjacent to the exclusion area of ​​the upper integrated circuit die 100, as will be further explained below. In some embodiments, the diameter D2 is larger than the diameter D1. The active die connector 110 and the dummy die connector 111 may extend partially or completely through the bonding layer 108. Figure 1A , Figure 1B and Figure 1C In the illustrated embodiment, the active die connector 110 and the dummy die connector 111 extend completely through the bonding layer 108. The active die connector 110 may have a thickness T1 ranging from about 0.2 μm to about 1 μm. The dummy die connector 111 may have a thickness T2 ranging from about 0.2 μm to about 1 μm. In some embodiments, the thickness T1 is equal to the thickness T2.

[0091] The active die connector 110 and the dummy die connector 111 can be formed using one or more damascene processes, such as single damascene, dual damascene, etc. In some embodiments, the active die connector 110 and the dummy die connector 111 are formed from the same material, such as copper. In these embodiments, the active die connector 110 and the dummy die connector 111 can be formed using the same process. In some embodiments, the active die connector 110 and the dummy die connector 111 are formed from different materials. For example, the active die connector 110 can be formed from copper, while the dummy die connector 111 can be formed from aluminum, solder, etc. In these embodiments, the active die connector 110 and the dummy die connector 111 can be formed using different processes.

[0092] Figure 1D Showing according to some embodiments Figure 1BRegion 109 of the structure shown. The active die connector 110 may include a barrier sublayer 110A and a conductive sublayer 110B, while the dummy die connector 111 may include a barrier sublayer 111A and a conductive sublayer 111B. The conductive sublayers 110B and 111B may include the same materials as described above for the active die connector 110 and the dummy die connector 111, respectively. The barrier sublayers 110A and 111A prevent the material of the conductive sublayers 110B and 111B from diffusing into the interconnect structure 104. The barrier sublayers 110A and 111A may include tantalum, tantalum nitride, titanium, titanium nitride, etc., and may be formed prior to the conductive sublayers 110B and 111B by physical vapor deposition (PVD), electroplating, or other methods. The barrier sublayers 110A and 111A may have a thickness T3 ranging from about 0.05 μm to about 0.3 μm.

[0093] Figures 2A to 10C Intermediate process steps for forming an integrated circuit package according to some embodiments are shown. Figure 2A , Figure 2B and Figure 2C In the process, the wafer structure 200 is attached to the carrier 112 by an adhesive 114. Figure 2A The sectional view shown can be along Figure 2C The reference section A-A' in the top view shown is used to obtain the data, and Figure 2B The sectional view shown can be viewed along... Figure 2C The reference section B-B' in the top view shown is used to obtain the wafer structure 200. The wafer structure 200 can then be divided into one or more lower integrated circuit dies 200'. For illustrative purposes, in Figure 2A , Figure 2B and Figure 2C The sidewalls (e.g., boundaries) of the expected lower integrated circuit die 200' are shown in dashed lines. The carrier 112 can be a semiconductor carrier, a glass carrier, a ceramic carrier, etc. The carrier 112 can be a wafer. In some embodiments, the adhesive 114 is a heat-release layer, such as an epoxy resin-based light-to-heat-conversion (LTHC) release material that loses its adhesiveness upon heating. In some embodiments, the adhesive 114 is an ultraviolet (UV) adhesive that loses its adhesiveness upon exposure to ultraviolet light.

[0094] The designed lower integrated circuit die 200' can be a logic die (e.g., CPU, GPU, SoC, AP, microcontroller, etc.), a memory die (e.g., DRAM die, SRAM die, etc.), a power management die (e.g., PMIC die), an RF die, a sensor die, a MEMS die, a signal processing die (e.g., DSP die), a front-end die (e.g., AFE die), or a combination thereof. The materials and processes for the features in the intended lower integrated circuit die 200' can be obtained by referring to similar features in the upper integrated circuit die 100. The intended lower integrated circuit die 200' may include a semiconductor substrate 202, which may have an active surface that can be referred to as the front side (e.g., Figure 2A The surface facing upwards and the non-active surface that can be referred to as the rear side (e.g., the surface facing upwards) and the surface that can be referred to as the rear side (e.g., the surface facing upwards) Figure 2A (The surface facing downwards). The rear side of the semiconductor substrate 202 may also be referred to as the rear side of the intended lower integrated circuit die 200', and the front side of the semiconductor substrate 202 may face the front side of the intended lower integrated circuit die 200'.

[0095] Devices (not shown separately) may be disposed on the active surface of semiconductor substrate 202. The devices may be active devices (e.g., transistors, diodes, etc.). These devices may generate significant heat during operation. Interconnection structure 204 may be disposed on the active surface of semiconductor substrate 202. Interconnection structure 204 may interconnect devices to form the intended lower integrated circuit die 200'. Interconnection structure 204 may include a metallization pattern 203 in dielectric layer 206. The metallization pattern 203 may be electrically coupled to the devices. Interconnection structure 204 may also include a sealing ring 205 in dielectric layer 206. For illustrative purposes, the sealing ring 205 is located in… Figure 2C Shown in dashed lines. In some embodiments, a sealing ring 205 extends through the dielectric layer 206. The sealing ring 205 may surround the metallization pattern 203 in a top view, and the region between the sealing ring 205 and the sidewall of the interconnect structure 204 may be referred to as a keep-out zone (KOZ) of the interconnect structure 204. The keep-out zone may not have the metallization pattern 203 formed. The sealing ring 205 may be formed of the same or similar material and using the same or similar process as the metallization pattern 203. The sealing ring 205 may be electrically isolated from the integrated circuit of the intended lower integrated circuit die 200'. A conductive via 207 may be disposed in the semiconductor substrate 202. The conductive via 207 may be electrically coupled to the metallization pattern 203 of the interconnect structure 204. The semiconductor substrate 202 may be thinned in a subsequent process to expose the conductive via 207 on a non-active surface of the semiconductor substrate 202. After the thinning process, the conductive via 207 can be referred to as a through-substrate via (TSV).

[0096] A bonding layer 208 may be disposed on the interconnect structure 204 on the front side of the intended lower integrated circuit die 200'. The bonding layer 208 may be formed of the same or similar material as the bonding layer 108 and by the same or similar processes. One or more passivation layers (not shown separately) may be disposed between the bonding layer 208 and the interconnect structure 204. An active die connector 210 and a dummy die connector 211 may be disposed in the bonding layer 208. The active die connector 210 and the dummy die connector 211 may also be referred to as bonding pads and may be used for bonding with another integrated circuit die in subsequent processes. The active die connector 210 may be electrically coupled to the metallization pattern 203 and the integrated circuit of the intended lower integrated circuit die 200'. The dummy die connector 211 may be electrically isolated from the integrated circuit of the intended lower integrated circuit die 200'. Figure 2C As shown in the top view, the sealing ring 205 may surround the active die connector 210, and in the top view, the dummy die connector 211 may be located outside the sealing ring 205 and at the adjacent corner of the intended lower integrated circuit die 200'. The dummy die connector 211 may be located directly above and adjacent to the exclusion area of ​​the interconnect structure 204. The dummy die connector 211 may then engage with the corresponding dummy die connector 111 of the upper integrated circuit die 100, which enhances the bonding strength between the upper integrated circuit die 100 and the intended lower integrated circuit die 200' in the region adjacent to the exclusion areas of the upper integrated circuit die 100 and the intended lower integrated circuit die 200', as will be further explained below.

[0097] The active die connector 210 and the dummy die connector 211 can have circular, polygonal (e.g., rectangular) shapes in a top view. In the top view, the dummy die connector 211 can be larger than the active die connector 210. Figure 2A , Figure 2B and Figure 2C In the illustrated embodiment, the active die connector 210 and the dummy die connector 211 have circular shapes. The active die connector 210 may have a diameter D4 ranging from about 5 μm to about 10 μm. The dummy die connector 211 may have a diameter D5 ranging from about 20 μm to about 60 μm. In some embodiments, the diameter D5 is larger than the diameter D4. The active die connector 210 and the dummy die connector 211 may extend partially or completely through the bonding layer 208. Figure 2A , Figure 2B and Figure 2CIn the illustrated embodiment, the active die connector 210 and the dummy die connector 211 extend completely through the bonding layer 208. The active die connector 210 may have a thickness T4 ranging from about 0.2 μm to about 1 μm. The dummy die connector 211 may have a thickness T5 ranging from about 0.2 μm to about 1 μm. In some embodiments, the thickness T4 is equal to the thickness T5.

[0098] The active die connector 210 and the dummy die connector 211 can be formed using one or more damascene processes, such as single damascene, dual damascene, etc. In some embodiments, the active die connector 210 and the dummy die connector 211 are formed of the same material, such as copper. In these embodiments, the active die connector 210 and the dummy die connector 211 can be formed using the same process. In some embodiments, the active die connector 210 and the dummy die connector 211 are formed of different materials. For example, the active die connector 210 can be formed of copper, while the dummy die connector 211 can be formed of aluminum, solder, etc. In these embodiments, the active die connector 210 and the dummy die connector 211 can be formed using different processes. In some embodiments, the dummy die connector 111 and the dummy die connector 211 are formed of the same material. In some embodiments, the dummy die connector 111 and the dummy die connector 211 are formed of different materials. For example, dummy connector 111 may be formed of copper or aluminum, while dummy connector 211 may be formed of solder, or dummy connector 111 may be formed of solder and dummy connector 211 may be formed of copper or aluminum.

[0099] Figure 2D Showing according to some embodiments Figure 2B Region 209 of the structure shown. The active die connector 210 may include a barrier sublayer 210A and a conductive sublayer 210B, while the dummy die connector 211 may include a barrier sublayer 211A and a conductive sublayer 211B. Conductive sublayers 210B and 211B may each comprise the same or similar materials as described above for conductive sublayers 110B and 111B. Barrier sublayers 210A and 211A prevent the material of conductive sublayers 210B and 211B from diffusing into the interconnect structure 204. Barrier sublayers 210A and 211A may each comprise the same or similar materials as described above for barrier sublayers 110A and 111A and be formed using the same or similar processes. Barrier sublayers 210A and 211A may have a thickness T6 ranging from about 0.05 μm to about 0.3 μm.

[0100] exist Figure 3A , Figure 3B and Figure 3CIn the process, the integrated circuit die 100 is bonded to the wafer structure 200. Figure 3A The sectional view shown can be along Figure 3C The reference section A-A' in the top view shown is used to obtain the data, and Figure 3B The sectional view shown can be viewed along... Figure 3C The reference section B-B' in the top view shown is used to obtain the data. For illustrative purposes, the active die connector 110, the dummy die connector 111, and the sealing ring 105 are... Figure 3C The image is shown in dashed lines. The wafer structure 200 can then be divided into one or more lower integrated circuit dies 200'. For illustrative purposes, in... Figure 3A , Figure 3B and Figure 3C The expected sidewalls (e.g., boundaries) of the lower integrated circuit die 200' are shown in dashed lines. As an example, Figure 3A , Figure 3B and Figure 3C This shows the layout of the two upper integrated circuit dies 100 on the expected lower integrated circuit die 200'. Other numbers (e.g., three, four) of upper integrated circuit dies 100 and other layouts on the expected lower integrated circuit die 200' are conceivable.

[0101] By bonding the bonding layer 108 of the upper integrated circuit die 100 to the bonding layer 208 of the intended lower integrated circuit die 200', and bonding the die connectors (e.g., active die connector 110 and dummy die connector 111) of the upper integrated circuit die 100 to the die connectors (e.g., active die connector 210 and dummy die connector 211) of the intended lower integrated circuit die 200', the upper integrated circuit die 100 can be bonded to the intended lower integrated circuit die 200' in the wafer structure 200. The bonding between the bonding layer 108 and the bonding layer 208 can be a direct dielectric-to-dielectric bonding. The bonding between the active die connector 110 and the active die connector 210, and the bonding between the dummy die connector 111 and the dummy die connector 211, can be a direct metal-to-metal bonding.

[0102] The bonding process may include a surface treatment step, a lamination step, and an annealing step. During the surface treatment step, the surfaces of the bonding layer 108, active die connector 110, and dummy die connector 111 of the upper integrated circuit die 100, as well as the surfaces of the bonding layer 208, active die connector 210, and dummy die connector 211 of the wafer structure 200, may be cleaned and treated using plasma or the like. Next, the upper integrated circuit die 100 may be placed on the lower integrated circuit die 200' intended for inclusion in the wafer structure 200. During the lamination step, a small pressure is applied at a low temperature (e.g., room temperature) to press the upper integrated circuit die 100 against the wafer structure 200. After the lamination step, a dielectric-to-dielectric bond may be formed between the bonding layers 108 and 208.

[0103] The bonding strength between bonding layers 108 and 208 can be improved during a subsequent annealing step at a higher temperature. Furthermore, during the annealing step, the material of active die connector 110 can be mixed and bonded with the material of active die connector 210, and the material of dummy die connector 111 can be mixed and bonded with the material of dummy die connector 211 to form a metal-to-metal bond. The bonding between dummy die connector 111 and dummy die connector 211 can enhance the bonding strength between the upper integrated circuit die 100 and the expected lower integrated circuit die 200' in the region adjacent to the exclusion area of ​​the upper integrated circuit die 100 and the expected lower integrated circuit die 200'. This can eliminate or reduce the risk of delamination of the upper integrated circuit die 100 during the manufacture and operation of the integrated circuit package. In this way, the performance and reliability of the integrated circuit package can be improved.

[0104] exist Figure 3A , Figure 3B and Figure 3C In the illustrated embodiments, the size and shape of the active die connector 110 are the same as or similar to the size and shape of the corresponding active die connector 210, and the size and shape of the dummy die connector 111 are the same as or similar to the size and shape of the corresponding dummy die connector 211. In other embodiments, the size and shape of the active die connector 110 differs from the size and shape of the corresponding active die connector 210, and / or the size and shape of the dummy die connector 111 differs from the size and shape of the corresponding dummy die connector 211.

[0105] exist Figure 3A , Figure 3B and Figure 3CIn the illustrated embodiment, the active die connector 110 is fully aligned with the corresponding active die connector 210, and the dummy die connector 111 is fully aligned with the corresponding dummy die connector 211. In other embodiments, the active die connector 110 is aligned with the corresponding active die connector 210 with an error margin of less than 3 μm, and / or the dummy die connector 111 is aligned with the corresponding dummy die connector 211 with an error margin of less than 3 μm.

[0106] The above is about Figure 3A , Figure 3B and Figure 3C The description uses a front-to-front bonding configuration according to some embodiments, wherein the front side of the upper integrated circuit die 100 may face the front side of the intended lower integrated circuit die 200'. In other embodiments, other bonding configurations may be used, such as a front-to-back bonding configuration, wherein the front side of the upper integrated circuit die 100 may face the rear side of the intended lower integrated circuit die 200', or the rear side of the upper integrated circuit die 100 may face the front side of the intended lower integrated circuit die 200'.

[0107] exist Figure 4 In this configuration, a gap-filling layer 116 is formed around the upper integrated circuit die 100, and the carrier 212 is bonded to the semiconductor substrate 102 and the surface of the gap-filling layer 116. In a top view, the gap-filling layer 116 may surround the upper integrated circuit die 100. The gap-filling layer 116 may extend along the sidewalls of the upper integrated circuit die 100 (e.g., the semiconductor substrate 102, the interconnect structure 104, and the bonding layer 108). The gap-filling layer 116 may be an insulating layer and may be formed of a dielectric material, such as silicon oxide, PSG, BSG, BPSG, TEOS-based oxides, etc., which may be formed by appropriate deposition processes, such as CVD, ALD, etc. Initially, the gap-filling layer 116 may cover the surface of the semiconductor substrate 102. A thinning process may be performed to make the surface of the gap-filling layer 116 flush with the surface of the semiconductor substrate 102. The thinning process may be a chemical-mechanical polishing (CMP) process, a polishing process, an etch-back process, a combination of the foregoing, etc. After the thinning process, the surfaces of the semiconductor substrate 102 and the gap filling layer 116 can be substantially coplanar (within the process variation).

[0108] The carrier 212 can be a semiconductor carrier, a glass carrier, a ceramic carrier, etc. The carrier 212 can be a wafer having the same or similar dimensions as the carrier 112. In some embodiments, bonding layers 213 and 214 are used to bond the carrier 212 to the semiconductor substrate 102 and the interstitial filling layer 116. Bonding layer 213 can be formed on the semiconductor substrate 102 and the interstitial filling layer 116, and bonding layer 214 can be formed on the carrier 212. Bonding layers 213 and 214 may each comprise a dielectric material, such as silicon dioxide, and can be formed by suitable deposition processes such as CVD and ALD. The structure above the carrier 112 can be constructed using... Figure 3A , Figure 3B and Figure 3C The same or similar process used for joining bonding layers 108 and 208 is used to join bonding layers 213 and 214 to join the structure above the carrier 112 to the carrier 212.

[0109] exist Figure 5 In the thinning process, carrier 112 and adhesive 114 are removed, and the semiconductor substrate 202 of wafer structure 200 is thinned to expose conductive vias 207, and a dielectric layer 216 is formed on the non-active surface of the semiconductor substrate. The removal process of carrier 112 and adhesive 114 may include projecting a light beam (e.g., a laser beam or an ultraviolet beam) onto the adhesive 114, causing the adhesive 114 to decompose due to the irradiation of the beam. Subsequently, carrier 112 can be removed. The thinning process of semiconductor substrate 202 may be a CMP process, a polishing process, an etch-back process, or a combination thereof. After the thinning process, a portion of the conductive via 207 may protrude from the non-active surface of semiconductor substrate 202.

[0110] Next, a dielectric layer 216 can be deposited to cover the exposed sidewalls of the conductive via 207. In some embodiments, the dielectric layer 216 comprises polybenzoxazole (PBO), polyimide, a benzocyclobutene-based polymer (BCB), etc., and is formed by a suitable coating process (e.g., spin coating, lamination, etc.). In some embodiments, the dielectric layer 216 comprises silicon dioxide, silicon nitride, silicon oxynitride, etc., and is formed by a suitable deposition process such as CVD, ALD, etc. First, the dielectric layer 216 may cover the bottom surface of the conductive via 207. Another thinning process may be performed to make the dielectric layer 216 and the bottom surface of the conductive via 207 flush. The thinning process may be a CMP process, a polishing process, an etch-back process, a combination of the foregoing, etc. After the thinning process, the bottom surfaces of the dielectric layer 216 and the conductive via 207 may be substantially coplanar (within process variations).

[0111] exist Figure 6In this process, a redistribution structure 219 is formed on the bottom surface of the dielectric layer 216 and the conductive via 207, and an under-bump metallization layer is formed on the redistribution structure 219.

[0112] UBM)220 and electrical connector 221. Figure 6 The structure shown may be referred to as wafer structure 250. The redistribution structure 219 may include a dielectric layer 217 and a metallization pattern 218 located within the dielectric layer 217. The dielectric layer 217 may be a low-dielectric-constant dielectric layer, including suitable dielectric materials (e.g., PBO, polyimide, BCB-based polymers, silicon dioxide, silicon nitride, silicon oxynitride, etc.). The dielectric layer 217 may be formed by spin coating, lamination, CVD, ALD, etc. The metallization pattern 218 may include metal lines and vias, which may be formed in the dielectric layer 217 by a damascene process, such as a single damascene process, a dual damascene process, etc. The metallization pattern 218 may be formed from a suitable conductive material, such as copper, tungsten, aluminum, silver, gold, or combinations thereof. The metallization pattern 218 may be electrically coupled to the conductive via 207. The under-bump metal layer 220 may have a portion along the surface of the extending dielectric layer 217 and a portion extending through the dielectric layer 217 to be electrically coupled to the metallization pattern 218.

[0113] As an example of forming the under-bump metal layer 220, a portion of the dielectric layer 217 (specifically, at least the bottom layer of the dielectric layer 217) can be patterned to form openings that expose the metallization pattern 218. Patterning can be performed using an acceptable lithography process, such as forming a mask followed by anisotropic etching. The mask can be removed after patterning. A seed layer can be formed on the dielectric layer 217, in the openings through the dielectric layer 217, and on the exposed portions of the metallization pattern 218. The seed layer can be a metal layer, which can be a single layer or a composite layer comprising multiple sublayers formed of different materials. The seed layer can be formed using a suitable deposition process, such as PVD. A photoresist can then be formed on the seed layer and patterned. Patterning can form openings through the photoresist to expose the seed layer. The pattern of the photoresist can correspond to the shape, size, and location of the under-bump metal layer 220. A conductive material can be formed in the openings of the photoresist and on the exposed portions of the seed layer. The conductive material can be formed by plating, such as electroless plating, electroplating, etc. The conductive material may include metals or metal alloys, such as copper, titanium, tungsten, aluminum, or combinations thereof. Next, the photoresist and portions of the seed layer where no conductive material is formed can be removed. The remaining portions of the seed layer and conductive material can form an under-bump metal layer 220.

[0114] Electrical connector 221 can be formed on the under-bump metal layer 220. Bumps formed using electroless nickel-electroless palladium-immersion gold technique (ENEPIG) are an example. In some embodiments, electrical connector 221 includes conductive materials such as solder, copper, aluminum, gold, nickel, silver, palladium, tin, or combinations thereof. Electrical connector 221 can be formed by first forming a solder layer through vapor deposition, electroplating, printing, solder transfer, ball placement, etc. Once the solder layer has been formed on the structure, reflow can be performed to shape the solder into the desired bump shape. In some embodiments, electrical connector 221 includes metal pillars, such as copper pillars, formed by sputtering, printing, electroplating, electroless plating, CVD, etc., which are solderless and have generally vertical sidewalls. A metal capping layer can be formed on top of the metal pillars by an electroplating process.

[0115] exist Figure 7 In this process, wafer structure 250 is diced into individual integrated circuit package elements 250'. Simultaneously, wafer structure 200 is diced into individual lower integrated circuit dies 200'. The above-described process can be performed using wafer-level processes. The carrier 212 can be a wafer and can include components related to... Figure 7 Many structures similar to the one shown are also possible (not shown individually). The wafer structure 250 can be placed on a strip 222 supported by a frame 224. Next, the wafer structure 250 can be diced along a dicing line 226, separating the wafer structure 250 into individual integrated circuit package elements 250'. The dicing process can include sawing, laser cutting, etc. A cleaning or rinsing process can be performed after the dicing process.

[0116] exist Figure 8 In this configuration, integrated circuit package element 250' is bonded to integrated circuit package element 228, and underfill 234 is formed between integrated circuit package element 250' and integrated circuit package element 228. Furthermore, integrated circuit package element 280 is bonded to integrated circuit package element 228 located next to integrated circuit package element 250', and underfill 238 is formed between integrated circuit package element 280 and integrated circuit package element 228.

[0117] Semiconductor package element 228 may include a substrate 229, a dielectric layer 227 on a first side of the substrate 229, a conductive feature 230 in the dielectric layer 227, and a conductive feature 232 on a second side of the substrate 229. Conductive feature 230 may include conductive lines and conductive vias. Conductive feature 232 may include an under-bump metal layer. Conductive via 231 may extend through the substrate 229 and may electrically couple conductive feature 230 to conductive feature 232. Electrical connector 233 may be located on conductive feature 232 and used for bonding to external devices, such as a package substrate, a printed circuit board (PCB), etc. Semiconductor package element 228 may be referred to as an interposer.

[0118] During the bonding process between integrated circuit package element 250' and integrated circuit package element 228, electrical connector 221 can be reflowed to bond integrated circuit package element 250' to the exposed portion of conductive element 230. Electrical connector 221 can electrically couple integrated circuit package element 228 to integrated circuit package element 250'. Underfill 234 can surround electrical connector 221 and protect the joint created due to reflow of electrical connector 221. Underfill 234 can surround integrated circuit package element 250' in top view. It can be formed by capillary flow process after attaching integrated circuit package element 250', or by appropriate deposition method before attaching integrated circuit package element 250'. Underfill 234 can then be cured.

[0119] Integrated circuit package element 280 may include one or more integrated circuit dies in an active region 275 of integrated circuit package element 280. In some embodiments, the active region 275 includes a stack of interconnected memory dies, and integrated circuit package element 280 is referred to as a high bandwidth memory (HBM) device. Electrical connector 240 of integrated circuit package element 280 may electrically couple integrated circuit package element 228 to integrated circuit package element 280. Electrical connector 240 may be formed of the same or similar material as electrical connector 221 and by the same or similar process as electrical connector 221. Underfill 238 may surround electrical connector 240 and may surround integrated circuit package element 280 in top view. Underfill 238 may be formed of the same or similar material as underfill 234 and by the same or similar process as underfill 234.

[0120] exist Figure 9In this process, the carrier 212, bonding layer 213, and bonding layer 214 are removed from the integrated circuit package element 250', and an adhesive layer 236 is formed on the gap filling layer 116, the upper integrated circuit die 100 of the integrated circuit package element 250', and the active region 275 of the integrated circuit package element 280. The adhesive layer 236 may include a thermal interface material (TIM), which may be a material with high thermal conductivity, such as thermal paste, gel-based thermal adhesive, graphite, graphene film, or a combination thereof.

[0121] exist Figure 10A , Figure 10B and Figure 10C In this process, a reinforcing ring 282 is attached to an integrated circuit package element 228, and a cover 290 is attached to the reinforcing ring 282, as well as integrated circuit package elements 250' and 280. Figure 10A , Figure 10B and Figure 10C The structure shown can be referred to as integrated circuit package 300. Figure 10A The sectional view shown can be viewed along... Figure 10C The reference section A-A' in the top view shown is used to obtain the data. Figure 10B The sectional view shown can be viewed along... Figure 10C The reference section B-B' in the top view shown is used to obtain the data. For illustrative purposes, the upper integrated circuit die 100, some features of the upper integrated circuit die 100, the lower integrated circuit die 200', the integrated circuit package element 280, and the reinforcing ring 282 are described. Figure 10C The text is displayed in dashed lines.

[0122] The reinforcing ring 282 can be used to provide additional support to the integrated circuit package element 228 during subsequent manufacturing processes to reduce warpage or other types of deformation of the integrated circuit package element 228. The reinforcing ring 282 can be formed of a high-hardness material, such as metal, metal alloy, etc. The reinforcing ring 282 can be attached to the integrated circuit package element 228 by an adhesive 284 such as epoxy resin, glue, etc.

[0123] The cover 290 can be used to dissipate heat generated by the integrated circuit package elements 250' and 280 during the operation of the integrated circuit package 300. The cover 290 can be attached to the integrated circuit package elements 250' and 280 via an adhesive layer 236, and to the reinforcing ring 282 via an adhesive 286 such as epoxy resin, glue, etc. The cover 290 can be formed of metal or metal alloy, such as copper, stainless steel, etc. Due to the bonding between the dummy die connector 111 of the upper integrated circuit die 100 and the dummy die connector 211 of the lower integrated circuit die 200', the risk of delamination of the upper integrated circuit die 100 can be eliminated or reduced, which allows heat generated in the lower integrated circuit die 200' to be more effectively transferred to the cover 290 and dissipated. This improves the performance and reliability of the integrated circuit package 300.

[0124] The embodiments may have several advantageous features. By engaging dummy die connectors 111 and 211, the bonding strength between the upper integrated circuit die 100 and the lower integrated circuit die 200' can be enhanced in the exclusion region adjacent to the upper integrated circuit die 100 and the lower integrated circuit die 200'. This can eliminate or reduce the risk of delamination of the upper integrated circuit die 100 during the manufacture and operation of the integrated circuit package 300. In this way, heat generated in the lower integrated circuit die 200' can be dissipated more effectively, thereby improving the performance and reliability of the integrated circuit package 300.

[0125] In some embodiments, an integrated circuit package includes a first die, comprising: a first semiconductor substrate and a first interconnect structure on the first semiconductor substrate. The first interconnect structure includes: a plurality of first dielectric layers, a plurality of first metallization patterns in the plurality of first dielectric layers, and a first sealing ring located in the plurality of first dielectric layers. In a top view, the first sealing ring surrounds the plurality of first metallization patterns. The first die includes a first bonding layer on the first interconnect structure and a first die connector located in the first bonding layer. In a top view, the first sealing ring surrounds the first die connector. The first die includes a second die connector located in the first bonding layer. In a top view, the second die connector is located outside the first sealing ring.

[0126] In some embodiments, the first die connector is electrically coupled to the integrated circuit of the first die.

[0127] In some embodiments, the second die connector is electrically isolated from the integrated circuit of the first die.

[0128] In some embodiments, in a top view, the size of the second die connector is larger than the size of the first die connector.

[0129] In some embodiments, the first die connector and the second die connector comprise the same first material, wherein the first material is copper.

[0130] In some embodiments, the first die connector includes a first material and the second die connector includes a second material, wherein the first material is copper and the second material is solder.

[0131] In some embodiments, the integrated circuit package further includes a second die, wherein the second die includes a second interconnect structure having a second sealing ring, a second bonding layer on the second interconnect structure and bonded to a first bonding layer, and a third die connector located in the second interconnect structure and bonded to a first die connector.

[0132] In some embodiments, in a top view, the second sealing ring surrounds the third die connector, and in a top view, the fourth die connector is located outside the second sealing ring.

[0133] In some embodiments, an integrated circuit package includes a first die, which includes a first semiconductor substrate and a first interconnect structure on the first semiconductor substrate. The first interconnect structure includes a first sealing ring, a first bonding layer on the first interconnect structure, a first die connector in the first bonding layer, and a second die connector in the first bonding layer. The first die connector is electrically coupled to the integrated circuit of the first die. The second die connector is electrically isolated from the integrated circuit of the first die. In a top view, the first sealing ring is disposed between the first die connector and the second die connector.

[0134] In some embodiments, in a top view, a first sealing ring surrounds a first die connector.

[0135] In some embodiments, the second die connector is located directly above the exclusion zone (KOZ) of the first interconnect structure.

[0136] In some embodiments, in a top view, the diameter of the second die connector is larger than the diameter of the first die connector.

[0137] In some embodiments, the first die connector includes a first material, and the second die connector includes a second material different from the first material.

[0138] In some embodiments, the first material is copper, and the second material is aluminum or solder.

[0139] In some embodiments, a method of forming an integrated circuit package includes attaching a first die to a carrier. The first die includes a first semiconductor substrate, a first interconnect structure on the first semiconductor substrate, a first bonding layer on the first interconnect structure, and a first die connector and a second die connector located in the first bonding layer. The first interconnect structure includes a first sealing ring. In a top view, the first sealing ring surrounds the first die connector, and in another top view, the second die connector is located outside the first sealing ring. This method includes bonding the second die to the first bonding layer, the first die connector, and the second die connector.

[0140] In some embodiments, a first die connector is electrically coupled to an integrated circuit of a first die, and a second die connector is electrically isolated from the integrated circuit of the first die.

[0141] In some embodiments, the second die includes a second interconnect structure having a second sealing ring, a second bonding layer located on the second interconnect structure, and a third die connector and a fourth die connector located in the second bonding layer. The second bonding layer is bonded to the first bonding layer by dielectric-to-dielectric bonding, and the third die connector and the fourth die connector are bonded to the first die connector and the second die connector, respectively, by metal-to-metal bonding.

[0142] In some embodiments, in a bottom view, the second sealing ring surrounds the third die connector, and in a bottom view, the fourth die connector is located outside the second sealing ring.

[0143] In some embodiments, in a top view, the second die connector is adjacent to a corner of the first die, and in a bottom view, the fourth die connector is adjacent to a corner of the second die.

[0144] In some embodiments, the first and third die connectors are formed of a first material, the second and fourth die connectors are formed of a second material, and the first material is different from the second material.

[0145] The foregoing outlines the features of numerous embodiments to enable those skilled in the art to better understand the various embodiments of this utility model. Those skilled in the art should understand that other processes and structures can be easily designed or modified based on the embodiments of this utility model to achieve the same objectives and / or advantages as the embodiments described herein. Those skilled in the art should also understand that these equivalent structures do not depart from the spirit and scope of this utility model. Various changes, substitutions, and modifications can be made to the embodiments of this utility model without departing from the spirit and scope of the appended claims.

Claims

1. An integrated circuit package, characterized in that, include: A first grain, comprising: A first semiconductor substrate; A first interconnect structure is located on the first semiconductor substrate, the first interconnect structure comprising: Multiple first dielectric layers; Multiple first metallization patterns are located in multiple first dielectric layers; and A first sealing ring is located within a plurality of the first dielectric layers, wherein, in a top view, the first sealing ring surrounds a plurality of the first metallization patterns; A first bonding layer is located on the first interconnect structure; A first die connector, located in the first bonding layer, wherein, in the top view, the first sealing ring surrounds the first die connector; and A second die connector is located in the first bonding layer, wherein, in the top view, the second die connector is located outside the first sealing ring.

2. The integrated circuit package as described in claim 1, characterized in that, The first die connector is electrically coupled to an integrated circuit of the first die.

3. The integrated circuit package as described in claim 1, characterized in that, The second die connector is electrically isolated from an integrated circuit of the first die.

4. The integrated circuit package as described in claim 1, characterized in that, In this top view, the size of the second die connector is larger than the size of the first die connector.

5. The integrated circuit package as described in claim 1, characterized in that, It also includes a second die, wherein the second die includes a second internal interconnect structure having a second sealing ring, a second bonding layer located on the second internal interconnect structure and bonded to the first bonding layer, a third die connector located in the second bonding layer and bonded to the first die connector, and a fourth die connector located in the second bonding layer and bonded to the second die connector.

6. The integrated circuit package as described in claim 5, characterized in that, In this top view, the second sealing ring surrounds the third die connector, and in this top view, the fourth die connector is located outside the second sealing ring.

7. An integrated circuit package, characterized in that, include: A first grain includes; A first semiconductor substrate; A first interconnect structure is located on the first semiconductor substrate, the first interconnect structure including a first sealing ring; A first bonding layer is located on the first interconnect structure; A first die connector is located in the first bonding layer, wherein the first die connector is electrically coupled to an integrated circuit of the first die; and A second die connector is located in the first bonding layer, wherein the second die connector is electrically isolated from the integrated circuit of the first die, and In one top view, the first sealing ring is disposed on the first die connector and the second die connector.

8. The integrated circuit package as described in claim 7, characterized in that, In this top view, the first sealing ring surrounds the first die connector.

9. The integrated circuit package as described in claim 7, characterized in that, The second die connector is located directly above an exclusion area of ​​the first interconnect structure.

10. The integrated circuit package as claimed in claim 7, characterized in that, In this top view, the diameter of the second die connector is larger than the diameter of the first die connector.

Images