Packaging structure and electronic device

Abstract

The present disclosure relates to a packaging structure and an electronic device, the packaging structure comprising a packaging substrate, a chip, a uniform heating layer and a connecting layer, the uniform heating layer being arranged on a side of the chip away from the packaging substrate, the uniform heating layer being used for uniformly distributing heat generated by the chip, a ratio of a thickness of the uniform heating layer to a thickness of the chip being in a range of 1 to 15, the connecting layer being arranged between the chip and the uniform heating layer, the connecting layer being used for connecting the chip and the uniform heating layer, and a rigidity of the connecting layer being less than a rigidity of the chip. Arranging the uniform heating layer on the side of the chip away from the packaging substrate and controlling the ratio of the thickness of the uniform heating layer to the thickness of the chip in the range of 1 to 15 can avoid heat concentration on the chip and improve the heat distribution performance of the chip. Arranging the connecting layer with the rigidity less than the rigidity of the chip between the chip and the uniform heating layer can realize the connection between the chip and the uniform heating layer and make the chip have good stress performance, so that the chip can meet the requirements of the heat distribution performance and the stress performance at the same time, and the overall performance and product quality of the packaging structure are improved.

Description

Technical Field

[0001] This disclosure relates to the field of semiconductor packaging, specifically a packaging structure and an electronic device. Background Technology

[0002] In recent years, with the continuous iteration of electronic devices, various components in electronic devices have gradually developed towards multi-functionality and smaller size, leading to the widespread application of packaging technology for chip packaging. The stress performance and heat dissipation effect of the chip within the packaging structure are key factors in evaluating the overall performance of the packaging structure. The packaging structure needs to comprehensively consider the chip's stress performance and heat dissipation requirements to ensure product quality. Utility Model Content

[0003] To overcome the problems existing in related technologies, this disclosure provides a packaging structure and an electronic device.

[0004] According to a first aspect of the present disclosure, a packaging structure is provided, the packaging structure comprising:

[0005] Packaging substrate;

[0006] The chip is electrically connected to the packaging substrate;

[0007] A heat dissipation layer is disposed on the side of the chip away from the packaging substrate. The heat dissipation layer is used to uniformly dissipate the heat generated by the chip. The ratio of the thickness of the heat dissipation layer to the thickness of the chip is in the range of 1 to 15.

[0008] A connection layer is disposed between the chip and the heat spreader layer, the connection layer is used to connect the chip and the heat spreader layer, and the rigidity of the connection layer is less than that of the chip.

[0009] In this embodiment, a heat dissipation layer is provided on the side of the chip facing away from the packaging substrate, and the thickness ratio of the heat dissipation layer to the chip is controlled within the range of 1 to 15. This effectively prevents heat concentration on the chip, improves the chip's heat dissipation performance, and ensures the chip's operational reliability. A connection layer with less rigidity than the chip is provided between the chip and the heat dissipation layer. This allows the chip to achieve good stress performance while connecting the chip and the heat dissipation layer, thus enabling the chip to simultaneously meet the requirements of heat dissipation performance and stress performance, improving the overall performance of the packaging structure and product quality.

[0010] In some embodiments of this disclosure, the chip includes a flip chip, wherein the active surface of the flip chip is the surface of the flip chip adjacent to the packaging substrate.

[0011] In this embodiment, a flip chip with an active surface closer to the packaging substrate is used as the chip in the packaging structure. This allows the chip to be electrically connected to the packaging substrate through the active surface, facilitating the setting of the heat dissipation layer and the connection layer. This satisfies the chip's heat dissipation performance and stress performance. Furthermore, the flip chip has excellent electrical performance, good heat dissipation performance, and low packaging cost, further improving the overall performance of the packaging structure and the product quality.

[0012] In some embodiments of this disclosure, the heat spreader layer includes at least one of a wafer and a metal layer.

[0013] In this embodiment, at least one of the wafer and the metal layer is used as the heat dissipation layer of the packaging structure. The heat generated by the chip can be uniformly distributed by the wafer or the metal layer. The high thermal conductivity and high hardness of the wafer or the metal layer are utilized to improve the heat dissipation effect and reliability of the chip, further improving the overall performance and product quality of the packaging structure. The low manufacturing cost and simple process of the wafer or the metal layer are also used to effectively reduce the production cost of the packaging structure and improve the production efficiency of the packaging structure.

[0014] In some embodiments of this disclosure, the bonding layer includes a wafer bonding film or a silver paste layer.

[0015] In this embodiment, the wafer bonding film or silver paste layer is used as a connection layer between the chip and the heat spreader. The good bonding performance of the wafer bonding film or silver paste layer can achieve a stable connection between the chip and the heat spreader. Moreover, the rigidity of the wafer bonding film and silver paste layer is less than that of the chip, which allows the chip to achieve good stress performance while further improving the overall heat dissipation performance of the packaging structure, thereby improving the quality of the packaging structure product.

[0016] In some embodiments of this disclosure, the thermal conductivity of the connecting layer is greater than or equal to 1 W / m*k.

[0017] In this embodiment, by configuring a connection layer with a thermal conductivity greater than or equal to 1W / m*k, the connection layer can also have a good thermal conductivity effect, enabling the heat dissipation layer to uniformly dissipate the heat generated by the chip and conduct it through the heat dissipation layer. This provides a basis for improving the chip's heat dissipation performance, thereby enabling the chip to simultaneously meet the requirements of heat dissipation performance and stress performance, and improving the overall performance of the packaging structure and product quality.

[0018] In some embodiments of this disclosure, the thickness of the chip is 50–250 μm, and the thickness of the heat spreader is 50–750 μm.

[0019] In this embodiment, the thickness of the chip is controlled between 50 and 250 μm, and the thickness of the heat spreader is controlled between 50 and 750 μm. This ensures that the ratio of the thickness of the heat spreader to the thickness of the chip is within the range of 1 to 15, so that both the chip and the heat spreader have reasonable thicknesses. This guarantees the stress performance of the chip and the heat spreader's heat dissipation and protection effects on the chip, further improving the overall performance of the packaging structure and the product quality.

[0020] In some embodiments of this disclosure, the thickness of the chip is 150–200 μm, the thickness of the heat spreader is 600–700 μm, and the thickness of the interconnect layer is 10–30 μm.

[0021] In this embodiment, the thickness of the chip is further controlled to 150–200 μm, the thickness of the heat spreader is further controlled to 600–700 μm, and the thickness of the interconnect layer is controlled to 10–30 μm. This makes the chip, heat spreader, and interconnect layer all have more reasonable thicknesses, further improving the performance of the chip, heat spreader, and interconnect layer individually, as well as the combined performance of the three. This improves the overall performance of the packaging structure and the product quality, and the overall height of the three facilitates the implementation of system-level packaging.

[0022] In some embodiments of this disclosure, at least two of the chip, the heat spreader, and the interconnect layer have projections that overlap on the packaging substrate.

[0023] In this embodiment, at least two of the chip, heat spreader, and interconnect layer are configured such that their projections on the packaging substrate overlap, making the edges of at least two of the chip, heat spreader, and interconnect layer flush. This improves the heat spreader's heat dissipation and protection effect on the chip, as well as the connection strength between the heat spreader and the chip, ensuring the overall strength and stability of the three components. Furthermore, it simplifies the packaging process, enabling mass production of the chip, heat spreader, and interconnect layer components, thereby improving the production efficiency of the packaging structure.

[0024] In some embodiments of this disclosure, the packaging structure further includes:

[0025] A heat-dissipating adhesive layer is disposed on the surface of the heat-spreading layer opposite to the packaging substrate.

[0026] The package includes a first package portion, a second package portion, and a connecting portion. The first package portion is connected to the thermal adhesive layer, the second package portion is connected to the package substrate, and the connecting portion is used to connect the first package portion and the second package portion. The package and the package substrate enclose a receiving space, and the chip, the heat dissipation layer, and the connecting layer are located within the receiving space.

[0027] In this embodiment, a thermal adhesive layer and a package are provided. The thermal adhesive layer improves the heat dissipation effect of the package structure, and the package fixes and protects the chip, heat spreader, and connection layer as a whole, realizing the overall encapsulation of the chip, heat spreader, and connection layer. Together with the package substrate, chip, heat spreader, and connection layer, they form a complete package structure, enabling the chip to simultaneously meet the requirements of heat spreader performance and stress performance, thereby improving the overall performance of the package structure and product quality.

[0028] In some embodiments of this disclosure, the package includes a metal component.

[0029] In this embodiment, a metal component is used as the encapsulation component, which enables the encapsulation component to have a high connection strength with the thermal adhesive layer and the encapsulation substrate, and the good thermal conductivity of the metal component is used to further improve the heat dissipation effect of the encapsulation structure.

[0030] In some embodiments of this disclosure, the packaging structure further includes a molding compound used to encapsulate the chip, the heat spreader, and the interconnect layer.

[0031] In this embodiment, a molding compound is used to fix and protect the chip, heat spreader, and connector layer as a whole, thereby achieving overall encapsulation of the chip, heat spreader, and connector layer. Together with the packaging substrate, chip, heat spreader, and connector layer, it forms a complete packaging structure, enabling the chip to simultaneously meet the requirements of heat spreader performance and stress performance, thus improving the overall performance of the packaging structure and product quality.

[0032] In some embodiments of this disclosure, the packaging structure further includes a dynamic random access memory disposed on the packaging substrate, and the molding compound is also used to encapsulate the dynamic random access memory.

[0033] In this embodiment, in addition to encapsulating the chip, heat spreader, and interconnect layer, the molding compound can also wrap the dynamic random access memory to achieve overall encapsulation of the chip, heat spreader, interconnect layer, and dynamic random access memory, thereby realizing a system-level encapsulation method.

[0034] In some embodiments of this disclosure, the surface of the heat spreader layer facing away from the encapsulation substrate is exposed to the molding compound.

[0035] In this embodiment, the surface of the heat dissipation layer facing away from the packaging substrate is exposed to the molding compound. This further improves the heat dissipation effect of the packaging structure while ensuring the overall performance of the packaging structure. It also reduces the overall thickness of the packaging structure, saving the space occupied by the packaging structure in the thickness direction, which is beneficial to the layout and design of other structures outside the packaging structure.

[0036] According to a second aspect of the present disclosure, an electronic device is provided, the electronic device including the packaging structure described in the first aspect.

[0037] The technical solutions provided by the embodiments of this disclosure can include the following beneficial effects: a heat dissipation layer is provided on the side of the chip away from the packaging substrate, and the thickness ratio of the heat dissipation layer to the chip is controlled within the range of 1 to 15, which can effectively prevent heat concentration on the chip, improve the heat dissipation performance of the chip, and ensure the operational reliability of the chip. A connection layer with less rigidity than the chip is provided between the chip and the heat dissipation layer, which enables the chip to achieve good stress performance while realizing the connection between the chip and the heat dissipation layer, thereby enabling the chip to simultaneously meet the requirements of heat dissipation performance and stress performance, improving the overall performance of the packaging structure and product quality.

[0038] It should be understood that the above general description and the following detailed description are exemplary and explanatory only, and are not intended to limit this disclosure. Attached Figure Description

[0039] The accompanying drawings, which are incorporated in and form a part of this specification, illustrate embodiments consistent with this disclosure and, together with the description, serve to explain the principles of this disclosure.

[0040] Figure 1 This is a schematic diagram of the packaging structure according to an exemplary embodiment.

[0041] Figure 2 This is a schematic diagram of the packaging structure according to another exemplary embodiment.

[0042] Figure 3 This is a schematic diagram of the packaging structure according to another exemplary embodiment.

[0043] Figure 4 This is a schematic diagram of the packaging structure according to another exemplary embodiment.

[0044] Figure 5 This is a schematic diagram of the packaging structure according to another exemplary embodiment.

[0045] Figure 6 This is a schematic diagram of the packaging structure according to another exemplary embodiment.

[0046] In the picture:

[0047] 10-Packaging substrate; 20-Chip; 30-Heat vaporization layer; 40-Connecting layer; 50-Thermal adhesive layer; 60-Packaging component; 61-First packaging part; 62-Second packaging part; 63-Connecting part; 70-Molding material; 80-Dynamic random access memory; 90-Bottom filler. Detailed Implementation

[0048] Exemplary embodiments will now be described in detail, examples of which are illustrated in the accompanying drawings. When the following description relates to the drawings, unless otherwise indicated, the same numerals in different drawings denote the same or similar elements. The embodiments described in the following exemplary embodiments do not represent all embodiments consistent with this disclosure. Rather, they are merely examples of apparatuses and methods consistent with some aspects of this disclosure as detailed in the appended claims.

[0049] In recent years, with the continuous iteration of electronic devices such as mobile phones and tablets, the chips and other components in these devices have gradually become more multifunctional and smaller in size, leading to the widespread application of chip packaging technology. Within the packaging structure, the chip package interaction (CPI) stress performance determines the chip's reliability, while the chip's heat dissipation effect determines its operating performance and efficiency; both are key factors in evaluating the overall performance of the packaging structure.

[0050] In one exemplary embodiment, a packaging structure is provided that can be combined with a circuit board to form a circuit board assembly and be embedded in an electronic device such as a mobile phone, tablet computer, or smart bracelet.

[0051] In one embodiment, a thinner chip is selected in the packaging structure to give the chip better CPI stress performance and reduce the chip's CPI risk. However, this results in the heat generated by the chip being concentrated in a smaller space, leading to poor heat dissipation and poor heat uniformity. In another embodiment, a thicker chip is selected in the packaging structure to give the chip better heat uniformity, ensuring the chip's operating performance and lifespan. However, this results in poor CPI stress performance, increasing the risk of elasto-plastic instability fracture (ELK crack) and other reliability problems.

[0052] Using the above packaging structure, it is difficult to simultaneously consider the chip's stress performance and thermal performance by simply controlling the chip's thickness. This results in neither of them achieving optimal performance, limiting the overall performance of the packaging structure and the quality of the product.

[0053] In another embodiment, reference Figure 1As shown, the packaging structure includes a packaging substrate 10, a chip 20, a heat dissipation layer 30, and a connecting layer 40. The chip 20 is electrically connected to the packaging substrate 10. The heat dissipation layer 30 is disposed on the side of the chip 20 facing away from the packaging substrate 10. The heat dissipation layer 30 is used to uniformly distribute the heat generated by the chip 20. The ratio of the thickness of the heat dissipation layer 30 to the thickness of the chip 20 ranges from 1 to 15. The connecting layer 40 is disposed between the chip 20 and the heat dissipation layer 30. The connecting layer 40 is used to connect the chip 20 and the heat dissipation layer 30. The rigidity of the connecting layer 40 is less than that of the chip 20.

[0054] The package substrate 10 is used to carry the chip 20, providing electrical connection, protection, support, and heat dissipation for the chip 20. It enables multiple input / output, reduced package size, and modularization of the chip 20. The chip 20 in the package structure can have different functions, types, and manufacturing processes. The chip 20 is disposed on and electrically connected to the package substrate 10. The package substrate 10 and the chip 20 constitute the basic part of the package structure. The electrical connection between the chip 20 and the package substrate 10 can be achieved, for example, through a combination of flip chip (FC) and bump or ball grid array technology. Figures 1 to 6 As shown, solder balls are also provided on the other side of the packaging substrate 10. The packaging substrate 10 can be electrically connected to devices or circuits outside the packaging structure through the solder balls, so that the packaging structure can form a circuit board assembly with the circuit board.

[0055] A heat dissipation layer 30 is disposed on the side of the chip 20 facing away from the packaging substrate 10, i.e., the chip 20 is located between the heat dissipation layer 30 and the packaging substrate 10. The ratio of the thickness of the heat dissipation layer 30 to the thickness of the chip 20 ranges from 1 to 15. For example, the ratio can be 1, 5, 10, 15, etc., meaning the thickness of the heat dissipation layer 30 is greater than or equal to the thickness of the chip 20, and less than or equal to 15 times the thickness of the chip 20. Within this ratio range, the heat dissipation layer 30 can effectively increase the heat dissipation range of the chip 20 while ensuring process feasibility and structural stability, thereby uniformly distributing the heat generated by the chip 20 and preventing a large amount of heat from concentrating on the chip 20, thus improving the heat dissipation performance of the chip 20 and ensuring its heat dissipation effect. In addition, the heat dissipation layer 30 also forms a protective layer for the chip 20 on the side facing away from the packaging substrate 10, avoiding the risk of breakage due to impact and ensuring the reliability of the chip 20. For example, the heat dissipation layer 30 may include a wafer or a metal layer, and the ratio of the thickness of the heat dissipation layer 30 to the thickness of the chip 20 may be, for example, 3.

[0056] A connecting layer 40 is disposed between the chip 20 and the heat spreader 30. The connecting layer 40 is used to connect the chip 20 and the heat spreader 30 to fix them together. The rigidity of the connecting layer 40 is less than that of the chip 20, meaning that the connecting layer 40 is more easily deformed than the chip 20. This reduces stress transmission between the chip 20 and the heat spreader 30, so that the increase in the overall thickness of the package structure with the heat spreader 30 is not significantly affected by the stress performance of the chip 20 itself. The chip 20 can achieve good CPI stress performance with a relatively thin thickness.

[0057] In this embodiment, a heat dissipation layer is provided on the side of the chip facing away from the packaging substrate, and the thickness ratio of the heat dissipation layer to the chip is controlled within the range of 1 to 15. This effectively prevents heat concentration on the chip, improves the chip's heat dissipation performance, and ensures the chip's operational reliability. A connection layer with less rigidity than the chip is provided between the chip and the heat dissipation layer, enabling the chip to achieve good stress performance while connecting the chip and the heat dissipation layer. The heat dissipation performance of chip 20 corresponds to the overall thickness of chip 20 and heat dissipation layer 30, and the stress performance of chip 20 corresponds to the thickness of chip 20 itself. This allows the chip to simultaneously meet the requirements of heat dissipation performance and stress performance, improving the overall performance of the packaging structure and product quality.

[0058] In some embodiments, chip 20 includes a flip chip, the active surface of which is the surface of the flip chip closest to the packaging substrate 10.

[0059] The chip 20 in the package structure can be a flip chip (FC). The surface of the flip chip closest to the package substrate 10 is the active surface of the flip chip, that is, the side of the flip chip with the circuit pattern is close to the package substrate 10, and the other side is close to the interconnect layer 40 and the heat dissipation layer 30. Therefore, the flip chip can be electrically connected to the package substrate 10 through its active surface to ensure the function of the flip chip, and it is convenient to set the interconnect layer 40 and the heat dissipation layer 30 on the other side of the flip chip.

[0060] It should be noted that the term "flip chip" only describes the connection posture between the chip 20 and the packaging substrate 10, and does not limit the function and type of the chip 20. For example, various different chips 20, such as logic chips or system-on-a-chip, can be used as this flip chip.

[0061] In this embodiment, a flip chip with an active surface close to the packaging substrate 10 is used as the chip 20 of the packaging structure. This allows the chip 20 to be electrically connected to the packaging substrate 10 through the active surface, facilitating the setting of the heat dissipation layer 30 and the connection layer 40. This satisfies the heat dissipation performance and stress performance of the chip 20. Furthermore, the flip chip has excellent electrical performance, good heat dissipation performance, and low packaging cost, further improving the overall performance and product quality of the packaging structure.

[0062] In some embodiments, the heat spreader 30 includes a wafer.

[0063] The heat dissipation layer 30 for uniformly dissipating heat generated by chip 20 can be a wafer, which is a dicing unit formed after a wafer is cut. The wafer material can be, for example, a high-purity semiconductor material, and no circuits or devices are disposed inside the wafer. The wafer has high thermal conductivity and hardness, which can improve the heat dissipation performance of chip 20 while ensuring the heat dissipation effect of chip 20, and form protection for chip 20 on the side of chip 20 away from the packaging substrate 10 to ensure the reliability of chip 20. For example, a mirror die with reflective characteristics can be used as the heat dissipation layer 30 of the packaging structure, and the wafer material can include, for example, silicon.

[0064] In other embodiments, the heat spreader 30 includes a metal layer.

[0065] The heat dissipation layer 30 used to uniformly distribute the heat generated by the chip 20 can also be a metal layer, i.e., a thin sheet of metal material, without any circuitry or devices disposed inside the metal layer. The metal layer has high thermal conductivity and hardness, which can improve the heat dissipation performance of the chip 20 while enhancing its heat dissipation capabilities. It also forms a protective layer on the side of the chip 20 away from the packaging substrate 10, ensuring the reliability of the chip 20. For example, the material of the metal layer may include copper or aluminum.

[0066] Of course, it is understandable that the heat spreader 30 may also include a wafer and a metal layer. That is, the heat spreader 30 may be a composite layer formed by stacking wafers and metal layers, and the strength and heat spreader effect of the heat spreader 30 can be adjusted by adjusting the thickness ratio of the wafer and the metal layer.

[0067] In this embodiment, at least one of the wafer and the metal layer is used as the heat dissipation layer 30 of the packaging structure. The heat generated by the chip 20 can be uniformly distributed through the wafer or the metal layer. The high thermal conductivity and high hardness of the wafer or the metal layer are utilized to improve the heat dissipation effect and reliability of the chip 20, further improving the overall performance and product quality of the packaging structure. The low manufacturing cost and simple process of the wafer or the metal layer are also used to effectively reduce the production cost of the packaging structure and improve the production efficiency of the packaging structure.

[0068] In some embodiments, the bonding layer 40 includes a wafer bonding film.

[0069] The connection layer 40 disposed between the chip 20 and the heat spreader 30 can be a die attach film (DAF). A die attach film is a dried adhesive film of a specific thickness used to connect chips 20 to each other or to structures such as wafers and packaging substrates 10 during semiconductor packaging processes. For example, the die attach film can be made of a polymer with good adhesion and thermal conductivity, allowing it to be adhered to the surface of the chip 20 or the heat spreader 30 to achieve a stable connection between the chip 20 and the heat spreader 30, while ensuring that the rigidity of the connection layer 40 is less than that of the chip 20, thus avoiding any impact on the stress performance of the chip 20.

[0070] In other embodiments, the bonding layer 40 includes a silver paste layer.

[0071] The connecting layer 40 disposed between the chip 20 and the heat spreader 30 can also be a silver paste layer, that is, the chip 20 and the heat spreader 30 are connected by a silver (Ag) adhesive. The silver paste layer has good adhesion and thermal conductivity, and the rigidity of the silver paste layer is less than that of the chip 20, so as to avoid affecting the stress performance of the chip 20.

[0072] In this embodiment, a wafer bonding film or silver paste layer is used as a connection layer 40 between the chip 20 and the heat dissipation layer 30. The good bonding performance of the wafer bonding film or silver paste layer can achieve a stable connection between the chip 20 and the heat dissipation layer 30. Moreover, the rigidity of the wafer bonding film and silver paste layer is less than that of the chip 20, which enables the chip 20 to achieve good stress performance while further improving the overall heat dissipation performance of the packaging structure, thereby improving the product quality of the packaging structure.

[0073] In some embodiments, the thermal conductivity of the connecting layer 40 is greater than or equal to 1 W / m*k.

[0074] When selecting the bonding layer 40, it is necessary to ensure that the thermal conductivity of the bonding layer 40 is greater than or equal to 1W / m*k, so that the bonding layer 40 has good thermal conductivity in addition to good adhesion performance, and can conduct the heat generated by the chip 20 to the heat dissipation layer 30, so that the heat dissipation layer 30 can evenly distribute the heat generated by the chip 20.

[0075] When the bonding layer 40 includes a wafer bonding film, it is necessary to select a material with high thermal conductivity for the wafer bonding film so that the thermal conductivity of the wafer bonding film can reach 1.5W / m*k or 2W / m*k. When the bonding layer 40 includes a silver paste layer, the thermal conductivity of the silver paste layer can reach 100 to 400W / m*k.

[0076] In this embodiment, by configuring a connection layer 40 with a thermal conductivity greater than or equal to 1W / m*k, the connection layer 40 can also have a good thermal conductivity effect, so that the heat dissipation layer 30 can evenly distribute the heat generated by the chip 20 and conducted through the heat dissipation layer 30, providing a basis for improving the heat dissipation performance of the chip 20. Thus, the chip 20 can simultaneously meet the requirements of heat dissipation performance and stress performance, improving the overall performance of the packaging structure and product quality.

[0077] In some embodiments, the thickness of the chip 20 is 50–250 μm, and the thickness of the heat dissipation layer 30 is 50–750 μm.

[0078] When the ratio of the thickness of the heat dissipation layer 30 to the thickness of the chip 20 is controlled within the range of 1 to 15, the thickness of the chip 20 can be set to 50 to 250 μm, and the thickness of the heat dissipation layer 30 can be set to 50 to 750 μm. Controlling the thickness of the chip 20 to 50 to 250 μm ensures that the chip 20 has good stress performance at this thickness while maintaining its functionality. Controlling the thickness of the heat dissipation layer 30 to 50 to 750 μm ensures that the heat dissipation layer 30 effectively heats the chip 20, and keeps the thicknesses of both the chip 20 and the heat dissipation layer 30 within a reasonable range. This protects the side of the chip 20 away from the packaging substrate 10 and facilitates the overall packaging of the chip 20 and the heat dissipation layer 30.

[0079] For example, when the thickness of chip 20 is 50 μm, the thickness of heat dissipation layer 30 can be 50–750 μm, and the ratio of the thickness of heat dissipation layer 30 to the thickness of chip 20 is in the range of 1–15. When the thickness of chip 20 is 250 μm, the thickness of heat dissipation layer 30 can be 250–750 μm, and the ratio of the thickness of heat dissipation layer 30 to the thickness of chip 20 is in the range of 1–3.

[0080] In this embodiment, the thickness of chip 20 is controlled between 50 and 250 μm, and the thickness of heat dissipation layer 30 is controlled between 50 and 750 μm. This ensures that the ratio of the thickness of heat dissipation layer 30 to the thickness of chip 20 is within the range of 1 to 15, so that both chip 20 and heat dissipation layer 30 have reasonable thicknesses. This guarantees the stress performance of chip 20 and the heat dissipation and protection effect of heat dissipation layer 30 on chip 20, further improving the overall performance of the packaging structure and product quality.

[0081] In some embodiments, the thickness of the chip 20 is 150–200 μm, the thickness of the heat dissipation layer 30 is 600–700 μm, and the thickness of the connection layer 40 is 10–30 μm.

[0082] To further improve the individual performance of chip 20, heat dissipation layer 30, and connecting layer 40, as well as the combined performance of the three, the thicknesses of chip 20 and heat dissipation layer 30, and the thickness of connecting layer 40 are further controlled. The thickness of chip 20 is further controlled within 150–200 μm to achieve a balance between its strength and stress performance. The thickness of heat dissipation layer 30 is further controlled within 600–700 μm to ensure that the ratio of its thickness to that of chip 20 is within the range that best matches the heat dissipation effect, protection effect, and cost control. The thickness of connecting layer 40 is controlled within 10–30 μm to achieve a balance between connection strength and thermal conductivity.

[0083] It should be noted that when the thicknesses of the control chip 20, the heat dissipation layer 30, and the connection layer 40 are within the aforementioned thickness range, the overall thickness of the three is 760–930 μm. This facilitates packaging with other devices on the packaging substrate 10, such as dynamic random access memory (typically 620 μm in height), to achieve system-in-package (SIP) of the package structure.

[0084] In this embodiment, the thickness of chip 20 is further controlled to 150-200 μm, the thickness of heat dissipation layer 30 is further controlled to 600-700 μm, and the thickness of connection layer 40 is controlled to 10-30 μm. This makes chip 20, heat dissipation layer 30 and connection layer 40 have more reasonable thicknesses, which further improves the performance of chip 20, heat dissipation layer 30 and connection layer 40 individually as well as the performance of the three combined. This improves the overall performance of the packaging structure and product quality, and the overall height of the three facilitates the implementation of system-level packaging of the packaging structure.

[0085] In some embodiments, at least two of the chip 20, the heat dissipation layer 30, and the interconnection layer 40 have projections on the packaging substrate 10 that overlap with each other.

[0086] At least two of the chip 20, the heat dissipation layer 30, and the interconnect layer 40 are configured such that their projections on the packaging substrate 10 coincide, meaning that at least two of the chip 20, the heat dissipation layer 30, and the interconnect layer 40 have the same size, shape, and position in a direction parallel to the packaging substrate 10, such that the edges of at least two of the chip 20, the heat dissipation layer 30, and the interconnect layer 40 are flush. For example, the chip 20 and the heat dissipation layer 30 can be configured such that their projections on the packaging substrate 10 coincide, and the chip 20, the heat dissipation layer 30, and the interconnect layer 40 can also be configured such that their projections on the packaging substrate 10 coincide.

[0087] It is understandable that when the projections of chip 20 and heat spreader 30 coincide, it is beneficial to improve the heat spreader effect and protection of chip 20 by heat spreader 30, and to ensure the overall structural strength and stability of chip 20 and heat spreader 30, avoiding the generation of edge stress. When fabricating heat spreader 30, the size of chip 20 can be used as a basis, reducing the complexity of the manufacturing process. When the projections of chip 20, heat spreader 30, and connecting layer 40 coincide, it also improves the connection strength between chip 20 and heat spreader 30, and facilitates the obtaining of chip 20, heat spreader 30, and connecting layer 40 with flush edges through the cutting process. For example, a larger chip 20 motherboard and heat spreader 30 motherboard can be connected by a larger connecting layer 40 motherboard, and multiple chip 20, heat spreader 30, and connecting layer 40 that meet the size requirements and have flush edges can be obtained through the cutting process.

[0088] In this embodiment, at least two of the chip 20, the heat dissipation layer 30, and the connection layer 40 are configured such that their projections on the packaging substrate 10 overlap, making the edges of at least two of the chip 20, the heat dissipation layer 30, and the connection layer 40 flush. This is beneficial for improving the heat dissipation and protection effect of the heat dissipation layer 30 on the chip 20, as well as the connection strength between the heat dissipation layer 30 and the chip 20. It ensures the strength and stability of the overall structure of the three components and can further simplify the packaging structure process, enabling the mass production of the chip 20, the heat dissipation layer 30, and the connection layer 40 components, thereby improving the production efficiency of the packaging structure.

[0089] It is understandable that the chip 20, the heat dissipation layer 30, and the connection layer 40 can be packaged on the packaging substrate 10 using different packaging methods to obtain different forms of packaging structures.

[0090] In some embodiments, reference Figure 2 As shown, the packaging structure also includes a thermal adhesive layer 50 and a package 60. The thermal adhesive layer 50 is disposed on the surface of the heat spreader 30 facing away from the packaging substrate 10. The package 60 includes a first package portion 61, a second package portion 62, and a connecting portion 63. The first package portion 61 is connected to the thermal adhesive layer 50, the second package portion 62 is connected to the packaging substrate 10, and the connecting portion 63 is used to connect the first package portion 61 and the second package portion 62. The package 60 and the packaging substrate 10 enclose a receiving space, within which the chip 20, the heat spreader 30, and the connecting layer 40 are located.

[0091] like Figure 2As shown, the packaging structure also includes a thermal adhesive layer 50 and a package 60. The thermal adhesive layer 50 is disposed on the surface of the heat spreader 30 facing away from the substrate, and is used to dissipate the uniform heat of the heat spreader 30 to improve the heat dissipation effect of the packaging structure. The package 60 is used to package the chip 20, the heat spreader 30, and the connecting layer 40. The package 60 includes a first packaging part 61 connected to the thermal adhesive layer 50, a second packaging part 62 connected to the packaging substrate 10, and a connecting part 63 connecting the first packaging part 61 and the second packaging part 62, so that the package 60 and the packaging substrate 10 enclose a receiving space. The chip 20, the heat spreader 30, and the connecting layer 40 are all disposed in the receiving space, thereby fixing and protecting the chip 20, the heat spreader 30, and the connecting layer 40 through the package 60. The chip 20 and the packaging substrate 10 can be electrically connected by a ball grid array. An underfill 90 can also be provided between the chip 20 and the packaging substrate 10. The underfill 90 can provide stress buffering, protect the ball grid array, improve reliability and improve electrical performance.

[0092] In this embodiment, a thermal adhesive layer 50 and a package 60 are provided. The thermal adhesive layer 50 improves the heat dissipation effect of the package structure, and the package 60 fixes and protects the chip 20, the heat dissipation layer 30 and the connecting layer 40 as a whole, realizing the overall encapsulation of the chip 20, the heat dissipation layer 30 and the connecting layer 40. Together with the package substrate 10, the chip 20, the heat dissipation layer 30 and the connecting layer 40, they form a complete package structure, enabling the chip 20 to simultaneously meet the requirements of heat dissipation performance and stress performance, thereby improving the overall performance of the package structure and the product quality.

[0093] In some embodiments, the package 60 includes a metal component.

[0094] The package 60 may include a metal component, meaning the material of the package 60 can be a metal material. For example, the material of the package 60 can be copper. Using a metal component as the package 60 enables the package 60 to have a high connection strength with the thermal adhesive layer 50 and the package substrate 10, and the good thermal conductivity of the metal component further improves the heat dissipation effect of the package structure.

[0095] In some embodiments, reference Figure 3 As shown, the packaging structure also includes molding compound 70, which is used to package the chip 20, the heat dissipation layer 30, and the interconnect layer 40.

[0096] like Figure 3As shown, the encapsulation structure also includes a molding compound 70, which can encapsulate the chip 20, the heat dissipation layer 30, and the connection layer 40 to fix and protect the chip 20, the heat dissipation layer 30, and the connection layer 40, thereby achieving encapsulation of the chip 20, the heat dissipation layer 30, and the connection layer 40. The material of the molding compound 70 may include, for example, epoxy resin, polyimide, or other polymer or ceramic encapsulation materials.

[0097] In this embodiment, a molding compound 70 is provided to fix and protect the chip 20, the heat dissipation layer 30, and the connecting layer 40 as a whole, thereby achieving overall encapsulation of the chip 20, the heat dissipation layer 30, and the connecting layer 40. Together with the packaging substrate 10, the chip 20, the heat dissipation layer 30, and the connecting layer 40, they form a complete packaging structure, enabling the chip 20 to simultaneously meet the requirements of heat dissipation performance and stress performance, thereby improving the overall performance of the packaging structure and the product quality.

[0098] In some embodiments, reference Figure 4 As shown, the packaging structure also includes a dynamic random access memory 80 disposed on the packaging substrate 10, and the molding compound 70 is also used to encapsulate the dynamic random access memory 80.

[0099] The packaging structure also includes a Dynamic Random Access Memory (DRAM) 80 disposed on the packaging substrate 10. The DRAM 80 can be, for example, Low Power Double Data Rate SDRAM (LPDDR). In addition to packaging the chip 20, the heat spreader layer 30, and the interconnect layer 40, the molding compound 70 can also encapsulate the DRAM 80 to achieve a complete encapsulation of the chip 20, the heat spreader layer 30, the interconnect layer 40, and the DRAM 80, thereby realizing a system-in-package (SIP) packaging method.

[0100] It should be noted that the aforementioned dynamic random access memory 80 is only an example of a device that is system-in-packaged with chip 20, heat dissipation layer 30 and interconnect layer 40. Chip 20, heat dissipation layer 30 and interconnect layer 40, molding compound 70 and packaging substrate 10 can also form a packaging structure under system-in-package together with other chips or devices disposed on packaging substrate 10.

[0101] In some embodiments, such as Figure 3 or Figure 4 As shown, the surface of the heat dissipation layer 30 facing away from the packaging substrate 10 is covered by the molding compound 70, that is, the surface of the heat dissipation layer 30 facing away from the packaging substrate 10 is not exposed to the molding compound 70, so that the molding compound 70 can protect the surface of the heat dissipation layer 30 facing away from the packaging substrate 10.

[0102] In other embodiments, reference is made to... Figure 5 or Figure 6 As shown, the surface of the heat dissipation layer 30 facing away from the packaging substrate 10 is exposed to the molding compound 70.

[0103] The surface of the heat dissipation layer 30 facing away from the packaging substrate 10 can be exposed to the molding compound 70, allowing this surface to directly contact the external environment and preventing the molding compound 70 from affecting the heat dissipation of the packaging structure. For example, after the packaging process is complete, the molding compound 70 on the surface of the heat dissipation layer 30 facing away from the packaging substrate 10 can be polished to expose this surface. Since the important function of the heat dissipation layer 30 is to evenly distribute the heat generated by the chip 20 and protect the chip 20, even if the exposed surface of the heat dissipation layer 30 is damaged to some extent, it will not affect the overall performance of the packaging structure.

[0104] In this embodiment, the surface of the heat dissipation layer 30 facing away from the packaging substrate 10 is exposed to the molding compound 70. While ensuring the overall performance of the packaging structure, the heat dissipation effect of the packaging structure is further improved, and the overall thickness of the packaging structure can be reduced, saving the space occupied by the packaging structure in the thickness direction, which is beneficial to the layout and design of other structures outside the packaging structure.

[0105] In one exemplary embodiment, an electronic device is provided, the electronic device including the packaging structure described above.

[0106] The electronic device may be, for example, a mobile phone, a tablet computer, or a smart bracelet. For example, the packaging substrate 10 of the above-described packaging structure can be electrically connected to a printed circuit board (PCB) via bumps to form a circuit board assembly and be embedded in the electronic device.

[0107] In this embodiment, since the packaging structure included in the electronic device has the advantage of simultaneously taking into account the thermal performance and stress performance of the chip 20, the electronic device and its included packaging structure have the same advantages.

[0108] Other embodiments of this disclosure will readily occur to those skilled in the art upon consideration of the specification and practice of the disclosure herein. This application is intended to cover any variations, uses, or adaptations of this disclosure that follow the general principles of this disclosure and include common knowledge or customary techniques in the art not disclosed herein. The specification and examples are to be considered illustrative only, and the true scope and spirit of this disclosure are indicated by the following claims.

[0109] It should be understood that this disclosure is not limited to the precise structures described above and shown in the accompanying drawings, and various modifications and changes can be made without departing from its scope. The scope of this disclosure is limited only by the appended claims.

Claims

1. A packaging structure, characterized in that, The packaging structure includes: Packaging substrate; The chip is electrically connected to the packaging substrate; A heat dissipation layer is disposed on the side of the chip away from the packaging substrate. The heat dissipation layer is used to uniformly dissipate the heat generated by the chip. The ratio of the thickness of the heat dissipation layer to the thickness of the chip is in the range of 1 to 15. A connection layer is disposed between the chip and the heat spreader layer, the connection layer is used to connect the chip and the heat spreader layer, and the rigidity of the connection layer is less than that of the chip.

2. The packaging structure according to claim 1, characterized in that, The chip includes a flip chip, and the active surface of the flip chip is the surface of the flip chip closest to the packaging substrate.

3. The packaging structure according to claim 1, characterized in that, The heat spreader layer includes at least one of a wafer and a metal layer.

4. The packaging structure according to claim 1, characterized in that, The bonding layer includes a wafer bonding film or a silver paste layer.

5. The packaging structure according to claim 4, characterized in that, The thermal conductivity of the connecting layer is greater than or equal to 1 W / m*k.

6. The packaging structure according to any one of claims 1 to 5, characterized in that, The thickness of the chip is 50–250 μm, and the thickness of the heat spreader is 50–750 μm.

7. The packaging structure according to claim 6, characterized in that, The thickness of the chip is 150–200 μm, the thickness of the heat spreader is 600–700 μm, and the thickness of the bonding layer is 10–30 μm.

8. The packaging structure according to any one of claims 1 to 5, characterized in that, At least two of the chip, the heat spreader, and the interconnect layer have projections that overlap on the packaging substrate.

9. The packaging structure according to any one of claims 1 to 5, characterized in that, The packaging structure further includes: A heat-dissipating adhesive layer is disposed on the surface of the heat-spreading layer opposite to the packaging substrate. The package includes a first package portion, a second package portion, and a connecting portion. The first package portion is connected to the thermal adhesive layer, the second package portion is connected to the package substrate, and the connecting portion is used to connect the first package portion and the second package portion. The package and the package substrate enclose a receiving space, and the chip, the heat dissipation layer, and the connecting layer are located within the receiving space.

10. The packaging structure according to claim 9, characterized in that, The encapsulation component includes a metal component.

11. The packaging structure according to claim 1, characterized in that, The packaging structure also includes a molding compound used to encapsulate the chip, the heat spreader, and the interconnect layer.

12. The packaging structure according to claim 11, characterized in that, The packaging structure further includes a dynamic random access memory disposed on the packaging substrate, and the molding compound is also used to encapsulate the dynamic random access memory.

13. The packaging structure according to claim 11 or 12, characterized in that, The surface of the heat-spreading layer facing away from the packaging substrate is exposed in the molding compound.

14. An electronic device, characterized in that, The electronic device includes the packaging structure as described in any one of claims 1 to 13.

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