阵列基板与电子纸显示装置
By setting an insulating layer and opening vias between the source/drain layer and the semiconductor layer, the corrosion problem of the semiconductor layer on the source/drain layer in thin-film transistors is solved, thus improving the stability of thin-film transistors and electronic paper display devices.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Utility models(China)
- Current Assignee / Owner
- ZHEJIANG LAIBAO DISPLAY TECHNOLOGY CO LTD
- Filing Date
- 2025-08-25
- Publication Date
- 2026-07-17
AI Technical Summary
In the prior art, the semiconductor layer fabrication process of thin-film transistors can corrode the metal layers of the source and drain electrodes, resulting in damage to the integrity of the metal layer structure and affecting the operational stability of the thin-film transistor, array substrate, and electronic paper display device.
A first insulating layer is set between the source/drain layer and the semiconductor layer, and a via is formed in the insulating layer so that the semiconductor layer is electrically connected to the source and drain through the via, thereby reducing the contact area and reducing corrosion. A top gate structure is adopted to enhance stability.
This effectively reduces the corrosion effect of the semiconductor layer on the source and drain layers, improves the working stability of thin-film transistors, and thus enhances the working stability of array substrates and electronic paper display devices.
Smart Images
Figure CN224519095U_ABST
Abstract
Claims
1. An array substrate, characterized by, The array substrate comprises a substrate base provided at the bottom of the array substrate, a plurality of scanning lines and data lines are provided on the substrate base, the plurality of scanning lines and data lines cross and form a plurality of pixel units, the pixel unit comprises: a pixel electrode provided opposite to the substrate base; a thin film transistor provided between the substrate base and the pixel electrode, the thin film transistor comprises a top gate, a semiconductor layer, a first insulating layer, a source electrode and a drain electrode, the top gate is connected to the scanning line, the source electrode is connected to the data line, the drain electrode is electrically connected to the source electrode, in the thickness direction of the array substrate, the top gate is located on the side of the semiconductor layer away from the substrate base, the first insulating layer is located on the side of the semiconductor layer away from the pixel electrode, the source electrode and the drain electrode are located on the side of the first insulating layer away from the pixel electrode, a through hole is provided in the first insulating layer, and the semiconductor layer is electrically connected to the source electrode and the drain electrode through the through hole.
2. The array substrate of claim 1, wherein, The projection of the top gate on the substrate base covers at least the projection of the semiconductor layer on the substrate base.
3. The array substrate of claim 1, wherein, The projection shape of the through hole on the substrate base is a circle, and the diameter of the circle is 8 um. Alternatively, the projection shape of the through hole on the substrate base is a concentric circle, and the diameter of the inner circle of the concentric circle is 8 um.
4. The array substrate of claim 1, wherein, The thin film transistor further comprises a second insulating layer provided between the top gate and the semiconductor layer.
5. The array substrate of claim 1, wherein, The thin film transistor further comprises a bottom gate located on the side of the source electrode and the drain electrode away from the pixel electrode.
6. The array substrate of claim 5, wherein, The thin film transistor further comprises a third insulating layer located between the source electrode and the drain electrode and the bottom gate.
7. The array substrate of claim 1, wherein, The thin film transistor further comprises a protective layer located between the pixel electrode and the top gate.
8. The array substrate of claim 1, wherein, The pixel electrode is provided with a connecting hole, and the pixel electrode is electrically connected to the drain electrode through the connecting hole.
9. The array substrate of claim 1, wherein, The material of the pixel electrode is indium tin metal oxide, and / or the material of the semiconductor layer is amorphous silicon or indium gallium zinc oxide.
10. An electronic paper display device, characterized by comprising: The array substrate comprises a top base, an electrophoretic layer and the array substrate as claimed in any one of claims 1-9.