A timed cyclic power-off and restart system

Abstract

This utility model discloses a timed cyclic power-off restart system, including a timed cyclic unit, a power-off restart unit, and a switch control unit. The power-off restart unit is connected to the timed cyclic unit, and the switch control unit is connected to the power-off restart unit. The power-off restart unit is in a default on-state upon power-up. The switch control unit is used to output power. The timed cyclic unit starts timing. After the set timing time, the timed cyclic unit controls the power-off restart unit's level to change from high to low via level switching, thereby controlling the switch control unit to turn off the power output, shutting down the device. Simultaneously, the timed cyclic unit resets and restarts, restarting the timing. After receiving a certain set time, the power-off restart unit flips its level from low to high, controlling the switch control unit to output power, turning on the device. This achieves automatic power-off restart of the device, allowing it to dissipate heat and lower the temperature during power outages, helping to restore component performance and extend the device's lifespan.

Description

Technical Field

[0001] This utility model relates to the field of Internet of Things (IoT) device technology, and in particular to a timed cyclic power-off and restart system. Background Technology

[0002] In the field of IoT device technology, most IoT devices operate continuously for extended periods. This continuous operation generates heat, which can accelerate the aging of components due to prolonged operation and overheating, reducing the device's lifespan and performance. In severe cases, it can even cause the device to shut down or be damaged. Utility Model Content

[0003] To solve the above problems, the technical solution adopted by this utility model is as follows:

[0004] A timed cyclic power-off restart system includes a timed cyclic unit, a power-off restart unit, and a switch control unit. The power-off restart unit is connected to the timed cyclic unit, and the switch control unit is connected to the power-off restart unit.

[0005] Furthermore, the power-off restart unit includes a chip U1. Pin 3 of chip U1 has an OUT point, which is connected to a timing loop unit. Pin 8 of chip U1 is connected in series with a capacitor C2, and capacitor C2 is grounded. A resistor R7 is connected between pin 3 and pin 8 of chip U1. Pin 7 and pin 4 of chip U1 are connected through a resistor R3. A diode D2 and resistor R2 are located between resistor R3 and pin 7 of chip U1. Resistor R2 is connected to pins 2 and 6 of chip U1. Resistor R2 is sequentially connected to pins 2 and 6 of chip U1. The circuit consists of a resistor R4, a diode D1, and a transistor Q3. Pin 3 of transistor Q3 is connected to diode D1. Pin 2 of transistor Q3 is connected to resistor R1. Pin 1 of transistor Q3 is connected to resistor R13. Resistor R1 and resistor R3 are connected to pin 3 of transistor Q7. Pin 1 of transistor Q7 is connected to resistor R82 and has a Q14 point. Transistor Q7 is connected to the timing loop unit through Q14. Pin 2 of transistor Q7 is grounded, and resistor R85 is connected between pins 1 and 2 of transistor Q7. Pin 5 of chip U1 is connected in series with capacitor C1, and capacitor C1 is grounded.

[0006] Furthermore, the timed cycle restart unit includes a chip U2. Pin 3 of the chip U2 is connected to point Q14, pin 8 of the chip U2 is grounded, pins 9 and 11 of the chip U2 are connected through capacitor C3 and resistor R11, a resistor R10 is provided between capacitor C3 and resistor R11, resistor R10 is connected to pin 10 of the chip U2, pin 16 of the chip U2 is connected in series with capacitor C5 and capacitor C5 is grounded, pin 12 of the chip U2 is connected in series with resistor R12 and resistor R12 is grounded, a point RST is provided between resistor R12 and pin 12 of the chip U2, and a capacitor C6 is provided between pin 12 and pin 16 of the chip U2.

[0007] Furthermore, the RST point is connected to a transistor Q7, wherein pin 3 of the transistor Q7 is connected to the RST point, and pin 3 of the transistor Q7 is also connected to a resistor R14. Pin 2 of the transistor Q7 is grounded, and pin 1 of the transistor Q7 is connected in series with a resistor R15, which is connected to the OUT point.

[0008] Furthermore, the switch control unit includes a transistor Q1. A resistor R5 is connected in series to pin 1 of the transistor Q1, and the resistor R5 is connected to the OUT point. Pin 2 of the transistor Q1 is grounded. A resistor R9 and a transistor Q2 are connected in series to pin 3 of the transistor Q1. Pin 1 of the transistor Q2 is connected to the resistor R9, and a resistor R8 is connected to pin 2 of the transistor Q2. The resistor R8 is positioned between the resistor R9 and pin 1 of the transistor Q2.

[0009] The beneficial effects of this utility model are:

[0010] When the power-off restart unit is powered on, it is in the on state by default. The switch control unit is used to output power supply. At the same time, the timer cycle unit starts timing. After a certain set time, the timer cycle unit controls the power-off restart unit to switch from high to low through level toggling, thereby controlling the switch control unit to turn off the power supply output, thus shutting down the device. At the same time, the timer cycle unit resets and restarts to start timing again. After receiving a certain set time, the power-off restart unit switches from low to high, controlling the switch control unit to output power supply, thus turning on the device. This realizes automatic power-off restart of the device, allowing the device to dissipate heat and reduce temperature during power failure, helping to restore the performance of components and improve the service life of the device. Attached Figure Description

[0011] The accompanying drawings, which are incorporated in and form part of this specification, illustrate embodiments consistent with this application and, together with the description, serve to explain the principles of the invention.

[0012] To more clearly illustrate the technical solutions in the embodiments of this application or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, for those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0013] Figure 1 This is a connection block diagram of the present invention;

[0014] Figure 2 The circuit diagram is for the timing loop unit;

[0015] Figure 3 The circuit diagram for the power-off restart unit;

[0016] Figure 4 This is the circuit diagram of the switch control unit. Detailed Implementation

[0017] To make the objectives, technical solutions, and advantages of the embodiments of this disclosure clearer, the technical solutions of the embodiments of this disclosure will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some, not all, of the embodiments of this disclosure. All other embodiments obtained by those skilled in the art based on the described embodiments of this disclosure without creative effort are within the scope of protection of this disclosure.

[0018] Unless otherwise defined, the technical or scientific terms used in this disclosure shall have the ordinary meaning understood by one of ordinary skill in the art to which this disclosure pertains. The terms "first," "second," and similar terms used in this disclosure do not indicate any order, quantity, or importance, but are merely used to distinguish different components. Terms such as "comprising" or "including" mean that the element or object preceding the word encompasses the elements or objects listed following the word and their equivalents, without excluding other elements or objects. Terms such as "upper," "lower," "left," and "right" are used only to indicate relative positional relationships, and these relative positional relationships may change accordingly when the absolute position of the described object changes.

[0019] refer to Figures 1-4 As shown, one embodiment of this utility model is as follows:

[0020] A timed cyclic power-off restart system includes a timed cyclic unit, a power-off restart unit, and a switch control unit. The power-off restart unit is connected to the timed cyclic unit, and the switch control unit is connected to the power-off restart unit.

[0021] In this invention, the power-off restart unit is in the on state by default when powered on. The switch control unit is used to output power supply, and at the same time, the timer cycle unit starts timing. After timing for a certain set time, the timer cycle unit controls the power-off restart unit to switch from high to low by level flipping, thereby controlling the switch control unit to turn off the output power supply, realizing the shutdown of the device. At the same time, the timer cycle unit resets and restarts to start timing again. After receiving a certain set time, the power-off restart unit flips the level from low to high, controlling the switch control unit to output power supply, realizing the startup of the device. This realizes the automatic power-off restart of the device, allowing the device to dissipate heat and reduce temperature when power is off, helping to restore the performance of components and improve the service life of the device.

[0022] Specifically, the power-off restart unit includes a chip U1. Pin 3 of chip U1 has an OUT point, which is connected to a timing loop unit. Pin 8 of chip U1 is connected in series with a capacitor C2, and capacitor C2 is grounded. A resistor R7 is connected between pin 3 and pin 8 of chip U1. Pin 7 and pin 4 of chip U1 are connected through a resistor R3. A diode D2 and resistor R2 are located between resistor R3 and pin 7 of chip U1. Resistor R2 is connected to pins 2 and 6 of chip U1. Resistor R2 is sequentially connected to pins 2 and 6 of chip U1. The circuit consists of a resistor R4, a diode D1, and a transistor Q3. Pin 3 of transistor Q3 is connected to diode D1. Pin 2 of transistor Q3 is connected to resistor R1. Pin 1 of transistor Q3 is connected to resistor R13. Resistor R1 and resistor R3 are connected to pin 3 of transistor Q7. Pin 1 of transistor Q7 is connected to resistor R82 and has a Q14 point. Transistor Q7 is connected to the timing loop unit through Q14. Pin 2 of transistor Q7 is grounded, and resistor R85 is connected between pins 1 and 2 of transistor Q7. Pin 5 of chip U1 is connected in series with capacitor C1, and capacitor C1 is grounded.

[0023] The timed cycle restart unit includes a chip U2. Pin 3 of chip U2 is connected to point Q14. Pin 8 of chip U2 is grounded. Pins 9 and 11 of chip U2 are connected through capacitor C3 and resistor R11. Resistor R10 is provided between capacitor C3 and resistor R11. Resistor R10 is connected to pin 10 of chip U2. Pin 16 of chip U2 is connected in series with capacitor C5 and is grounded. Pin 12 of chip U2 is connected in series with resistor R12 and is grounded. Point RST is provided between resistor R12 and pin 12 of chip U2. Capacitor C6 is provided between pin 12 and pin 16 of chip U2.

[0024] The RST point is connected to a transistor Q7, with pin 3 of the transistor Q7 connected to the RST point and a resistor R14 connected to pin 3 of the transistor Q7. Pin 2 of the transistor Q7 is grounded, and pin 1 of the transistor Q7 is connected in series with a resistor R15, which is connected to the OUT point.

[0025] The switch control unit includes a transistor Q1. A resistor R5 is connected in series to pin 1 of transistor Q1, and the resistor R5 is connected to the OUT point. Pin 2 of transistor Q1 is grounded. A resistor R9 and a transistor Q2 are connected in series to pin 3 of transistor Q1. Pin 1 of transistor Q2 is connected to the resistor R9, and a resistor R8 is connected to pin 2 of transistor Q2. The resistor R8 is positioned between the resistor R9 and pin 1 of transistor Q2.

[0026] The working principle of this invention: Chip U1 uses an NE555 chip, and chip U2 is a CD4060BM, a 14-bit binary counter. The circuit includes an oscillator driver module and a 14-bit binary counter module. Resistor R11 and capacitor C3 form an RC oscillator to provide the timing time (T = 2.2RC). Upon power-up, Q14 outputs a low level, and the collector (pin 3) of transistor Q7 remains high, turning off transistor Q3, and capacitor C4 remains low. The voltage at pin 2 of chip U1 is lower than 1 / 3 of the power supply voltage (12V), causing pin 3 (OUT point) of chip U1 to output a high level (12V). At this time, chip U2 starts timing. When the set time is reached, the set time T = 2.2RC * 2. 13 (s), the specific time can be controlled by selecting different resistors R11 and capacitor C3 according to actual needs. When Q14 flips to a high level, the level of pin 3 (collector) of transistor Q7 remains low, making transistor Q3 turn on. Capacitor C4 charges to the level of pin 6 of chip U1, which is higher than 2 / 3 of the power supply voltage (12V), so that pin 3 of chip U1, i.e., OUT point, outputs a low level. When pin 3 of chip U1 outputs a low level, the level of pin 3 (collector) of transistor Q4 is turned on. The output high level is pulled high to pin 12 of chip U2 to reset chip U2, and chip U2 restarts the zero-time timing. When chip U2 restarts the zero-time timing, point Q14 flips to a low level, the collector (pin 3) of transistor Q7 remains high, making Q3 turn off. C4 discharges through resistor R2, diode D2, and pin 7 of chip U2 to a voltage that is lower than 1 / 3 of the power supply voltage (12V) at pin 2 of chip U1, causing pin 3 of chip U1 to flip from low to high level (12V), thus realizing the cycle.

[0027] In this invention, transistor Q2 in the switch control unit is a P-MOS switch. The switching state of transistor Q2 is controlled by the level of pin 3 (OUT point) of chip U1, which is fed into pin 3 of transistor Q1 to control the power output. When pin 3 of chip U1 outputs a high level, the level of pin 3 of transistor Q1 remains low, transistor Q2 is off, and 12V power is output to the device. When pin 3 of chip U1 outputs a low level, the level of pin 3 of transistor Q1 remains high, transistor Q2 is on, power is stopped to the device, and 12V-OUT is output.

[0028] The following points need to be explained:

[0029] (1) Unless otherwise defined, the same reference numerals in the embodiments and drawings of this disclosure have the same meaning.

[0030] (2) The accompanying drawings of the embodiments of this disclosure only involve the structures involved in the embodiments of this disclosure. Other structures can be referred to the general design.

[0031] (3) For clarity, components or areas are enlarged in the drawings used to describe embodiments of the present disclosure. It will be understood that when an element is referred to as being “above” or “below” another element, the element may be “directly” located “above” or “below” the other element, or there may be an intermediate element.

[0032] The above description is merely a specific embodiment of this disclosure, but the scope of protection of this disclosure is not limited thereto. Any variations or substitutions that can be easily conceived by those skilled in the art within the scope of the technology disclosed in this disclosure should be included within the scope of protection of this disclosure. Therefore, the scope of protection of this disclosure should be determined by the scope of the claims.

Claims

1. A timed cycle power cycle reboot system, characterized by: It includes a timed cycle unit, a power-off restart unit, and a switch control unit. The power-off restart unit is connected to the timed cycle unit, and the switch control unit is connected to the power-off restart unit.

2. A timed cycle power cycle reboot system as claimed in claim 1, wherein: The power-off restart unit includes a chip U1. Pin 3 of chip U1 has an OUT point, which is connected to a timing loop unit. Pin 8 of chip U1 is connected in series with a capacitor C2, and capacitor C2 is grounded. A resistor R7 is connected between pin 3 and pin 8 of chip U1. Pin 7 and pin 4 of chip U1 are connected through a resistor R3. A diode D2 and resistor R2 are located between resistor R3 and pin 7 of chip U1. Resistor R2 is connected to pins 2 and 6 of chip U1. A series of resistors are connected between resistor R2 and pins 2 and 6 of chip U1. The circuit consists of a resistor R4, a diode D1, and a transistor Q3. Pin 3 of transistor Q3 is connected to diode D1. Pin 2 of transistor Q3 is connected to resistor R1. Pin 1 of transistor Q3 is connected to resistor R13. Resistor R1 and resistor R3 are connected to pin 3 of transistor Q7. Pin 1 of transistor Q7 is connected to resistor R82 and has a Q14 point. Transistor Q7 is connected to the timing loop unit through Q14. Pin 2 of transistor Q7 is grounded, and resistor R85 is connected between pins 1 and 2 of transistor Q7. A capacitor C1 is connected in series with pin 5 of chip U1 and is grounded.

3. A timed cycle power cycle reboot system as claimed in claim 2, wherein: The timed cycle restart unit includes a chip U2. Pin 3 of chip U2 is connected to point Q14. Pin 8 of chip U2 is grounded. Pins 9 and 11 of chip U2 are connected through capacitor C3 and resistor R11. Resistor R10 is provided between capacitor C3 and resistor R11. Resistor R10 is connected to pin 10 of chip U2. Pin 16 of chip U2 is connected in series with capacitor C5 and is grounded. Pin 12 of chip U2 is connected in series with resistor R12 and is grounded. Point RST is provided between resistor R12 and pin 12 of chip U2. Capacitor C6 is provided between pin 12 and pin 16 of chip U2.

4. The timed cycle power cycle reboot system of claim 3, wherein: The RST point is connected to a transistor Q7, with pin 3 of the transistor Q7 connected to the RST point and a resistor R14 connected to pin 3 of the transistor Q7. Pin 2 of the transistor Q7 is grounded, and pin 1 of the transistor Q7 is connected in series with a resistor R15, which is connected to the OUT point.

5. A timed cycle power cycle reboot system as claimed in claim 4, wherein: The switch control unit includes a transistor Q1. A resistor R5 is connected in series to pin 1 of transistor Q1, and the resistor R5 is connected to the OUT point. Pin 2 of transistor Q1 is grounded. A resistor R9 and a transistor Q2 are connected in series to pin 3 of transistor Q1. Pin 1 of transistor Q2 is connected to the resistor R9, and a resistor R8 is connected to pin 2 of transistor Q2. The resistor R8 is positioned between the resistor R9 and pin 1 of transistor Q2.

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