一种基于硬件电路的短路输入及报警IO控制系统电路

Abstract

本实用新型属于行业门禁电子产品硬件技术领域，公开一种基于硬件电路的短路输入及报警IO控制系统电路，包括主控SOC模块、具有多位并行输入 / 串行输出的移位寄存器模块以及外部接口模块，所述移位寄存器模块的并行输入端与所述外部接口模块连接，用于接收外部接口模块的输入信号和传输报警IO控制信号；所述的移位寄存器模块的串行输出端与主控SOC模块的GPIO1接口连接，所述移位寄存器模块的时钟输入端与所述主控SOC模块的第二GPIO2接口连接；所述外部接口模块上设有具有防误插功能的信号调理电路。本实用新型具有电平转换、抗干扰、接口保护等功能，结构简单、成本低廉、可靠性高的优点。

Claims

1. A short-circuit input and alarm IO control system circuit based on a hardware circuit, comprising a master control SOC module (1), a shift register module (2) with multi-bit parallel input / serial output, and an external interface module (3), characterized in that: The parallel input terminal of the shift register module (2) is connected to the external interface module (3) for receiving input signals from the external interface module (3) and transmitting alarm IO control signals; the serial output terminal of the shift register module (2) is connected to the GPIO1 interface of the main control SOC module (1), and the clock input terminal of the shift register module (2) is connected to the second GPIO2 interface of the main control SOC module; The external interface module (3) is equipped with a signal conditioning circuit with anti-misinsertion function. The signal conditioning circuit includes resistors R1 and R2, capacitor C1 and bidirectional TVS diode T1. One end of resistor R1 is connected to one end of resistor R2 and one end of bidirectional TVS diode T1. One end of resistor R1 is also connected to an external access device. The other end of resistor R1 is connected to the parallel input terminal of shift register module (2) and to one end of capacitor C1. The other end of capacitor C1 and the other end of bidirectional TVS diode T1 are grounded. The other end of resistor R2 is connected to a loading voltage of 3.3V.

2. The shorted input and alarm IO control system circuit based on hardware circuitry of claim 1, wherein: The shift register module (2) supports asynchronous parallel loading and synchronous serial data shifting. When it is necessary to acquire external signals, the parallel data loading is controlled by the SH / LD pin, and the clock signal provided by the main control SOC module is received by the CP pin, so as to realize the conversion and transmission of parallel data to serial data.

3. The shorted input and alarm IO control system circuit based on hardware circuitry of claim 1, wherein: There are at least two shift register modules (2). The serial output terminal of the previous module is connected to the serial input terminal of the next module. The serial output pin and CP pin of the two modules are connected to the GPIO1 interface and GPIO2 interface of the main control SOC, respectively, so as to realize the cascading of multiple shift register modules (2).

4. The shorted input and alarm IO control system circuit based on hardware circuitry of claim 1, wherein: The shift register module (2) is a 74HC165D shift register, which has ESD protection and surge protection capabilities, and realizes electrical isolation between the main control SOC module and external devices.

5. The shorted input and alarm IO control system circuit based on hardware circuitry of claim 1, wherein: The external interface module (3) consists of multiple short-circuit input interfaces and alarm IO interfaces, and each short-circuit input interface and each alarm IO interface is equipped with a signal conditioning circuit.

6. The short-circuit input and alarm I / O control system circuit based on hardware circuitry according to claim 4, characterized in that: When the main control SOC module (1) needs to acquire external short-circuit signals, it outputs a low level through the GPIO1 interface to control the SH / LD pin to achieve parallel data loading. Then, it outputs a clock signal through the GPIO2 interface. The 74HC165D shift register module transmits the 8 parallel signals bit by bit serially to the GPIO2 interface. The main control SOC module (1) completes the acquisition of the 8 short-circuit signals through serial reception. When an alarm control signal needs to be output, the main control SOC module (1) sends control instructions through the GPIO1 and GPIO2 interfaces. After being converted into parallel signals by the 74HC165D shift register module, the signals are output through the alarm IO interface of the external interface module to realize alarm linkage control.

7. The short-circuit input and alarm I / O control system circuit based on hardware circuitry according to claim 4, characterized in that: The conversion response speed of the 74HC165D shift register module is typically 15nS, and the maximum clock frequency is 61MHz.

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