A fast-response LDO circuit suitable for UWBSOC

Abstract

This application provides a fast-response LDO circuit suitable for UWB SOC, comprising: a reference voltage Vref, a fast feedback loop, and a slow loop; the fast feedback loop includes: PMOS transistor M1, PMOS transistor M2, NMOS transistor M3, and PMOS transistor M4; the gate of PMOS transistor M1 is connected to the source of PMOS transistor M2, the source of PMOS transistor M1 is connected to the power supply terminal, the gate of PMOS transistor M2 is connected to the drain of NMOS transistor M3, the source of NMOS transistor M3 is connected to the drain of PMOS transistor M4, and the source of PMOS transistor M4 is connected to the output terminal; the slow loop includes: an error amplifier EA, PMOS transistor M5, and NMOS transistor M7; the LDO circuit further includes: PMOS transistor M11 and a bias circuit, the bias circuit including PMOS transistor M12 and PMOS transistor M13.

Description

Technical Field

[0001] This application relates to the field of ultra-wideband technology, and in particular to an LDO circuit suitable for fast response in UWB SOC. Background Technology

[0002] Ultra-wideband (UWB) is suitable for a wide range of wireless systems. UWB positioning technology uses pulse signals with extremely low power spectral density and extremely narrow pulse width to transmit data. It has the characteristics of high time resolution and strong spatial penetration, and can achieve centimeter-level ranging and positioning accuracy in line-of-sight environments.

[0003] A System-on-Chip (SoC) is a highly integrated application-specific chip that integrates hardware and software co-design on a single die. UWB (Ultra Wideband) communication is a relatively complex system, and currently, the mainstream approach is to design solutions using SoCs. A typical UWB communication SoC chip includes a normally-on timer module, a microprocessor core module, a digital baseband, a memory module, a power supply module, a system clock module, an RF carrier clock module, a transmitter, and a receiver.

[0004] The LDO (Low Dropout Regulator) provides a clean power supply voltage and transient response voltage for the modules mentioned above. Some modules require an LDO that can quickly recover its transient response to handle rapid high-current pull-out.

[0005] Therefore, there is a need to provide an LDO circuit with fast response in UWB SOC that can solve the above problems. Utility Model Content

[0006] The technical problem to be solved by this utility model is to provide a fast-response LDO circuit suitable for UWB SOC. By setting a bias circuit and core transistor related to the power supply voltage, the transistor can be ensured to operate below 0.9V, thereby improving the reliability of the circuit.

[0007] The technical solution adopted by this utility model to solve the above-mentioned technical problems is to provide an LDO circuit with fast response suitable for UWB SOC, including: reference voltage Vref, fast feedback loop, and slow loop; The fast feedback loop includes: PMOS transistor M1, PMOS transistor M2, NMOS transistor M3, and PMOS transistor M4; the gate of PMOS transistor M1 is connected to the source of PMOS transistor M2, the source of PMOS transistor M1 is connected to the power supply terminal, the gate of PMOS transistor M2 is connected to the drain of NMOS transistor M3, the source of NMOS transistor M3 is connected to the drain of PMOS transistor M4, and the source of PMOS transistor M4 is connected to the output terminal. The slow circuit includes: an error amplifier EA, a PMOS transistor M5, and an NMOS transistor M7; the drain of the PMOS transistor M5 is connected to the non-inverting input of the error amplifier EA, the gate of the PMOS transistor M5 is connected to the gate of the PMOS transistor M4, the gate of the NMOS transistor M7 is connected to the output of the error amplifier EA, the source of the NMOS transistor M7 is grounded, and the inverting input of the error amplifier EA is connected to the reference voltage Vref. The LDO circuit further includes: a PMOS transistor M11 and a bias circuit, the bias circuit including a PMOS transistor M12 and a PMOS transistor M13; the drain of the PMOS transistor M12 is connected to the source of the PMOS transistor M13, the source of the PMOS transistor M12 is connected to the power supply terminal, the drain of the PMOS transistor M13 is grounded after being connected in series with a resistor, the gate of the PMOS transistor M11 is connected to the drain of the PMOS transistor M13, the source of the PMOS transistor M11 is connected to the drain of the PMOS transistor M2, and the drain of the PMOS transistor M11 is grounded.

[0008] Preferably, the PMOS transistors M1, M2, and M4 are core transistors, and the NMOS transistor M3 is an I / O transistor; the PMOS transistors M11, M12, and M13 are I / O transistors.

[0009] Preferably, the LDO circuit further includes NMOS transistor M6, PMOS transistor M8, PMOS transistor M9, and PMOS transistor M10, wherein the NMOS transistor M6 is an NMOS current mirror, and the PMOS transistors M8, M9, and M10 are PMOS current mirrors.

[0010] Preferably, the gate of the PMOS transistor M4 is connected to the gate of the PMOS transistor M5, and the PMOS transistor M4 mirrors the current in the PMOS transistor M5.

[0011] This utility model offers the following advantages over existing technologies: It provides a fast-response LDO circuit suitable for UWBSOC, comprising: a reference voltage Vref, a fast feedback loop, and a slow feedback loop. The fast feedback loop includes: PMOS transistor M1, PMOS transistor M2, NMOS transistor M3, and PMOS transistor M4. The gate of PMOS transistor M1 is connected to the source of PMOS transistor M2, and the source of PMOS transistor M1 is connected to the power supply terminal. The gate of PMOS transistor M2 is connected to the drain of NMOS transistor M3, and the source of NMOS transistor M3 is connected to the drain of PMOS transistor M4. The source of PMOS transistor M4 is connected to the output terminal. The slow feedback loop includes: an error amplifier EA, a PMOS transistor M5, and an NMOS transistor M7. The drain of PMOS transistor M5 is connected to the non-inverting input terminal of the error amplifier EA, and the gate of PMOS transistor M5 is connected to the non-inverting input terminal of the error amplifier EA. The gate of transistor M4 is connected to the ground, the gate of NMOS transistor M7 is connected to the output of error amplifier EA, the source of NMOS transistor M7 is grounded, and the inverting input of error amplifier EA is connected to the reference voltage Vref. The LDO circuit also includes: PMOS transistor M11 and a bias circuit, the bias circuit including PMOS transistor M12 and PMOS transistor M13; the drain of PMOS transistor M12 is connected to the source of PMOS transistor M13, the source of PMOS transistor M12 is connected to the power supply terminal, the drain of PMOS transistor M13 is grounded after a series resistor, the gate of PMOS transistor M11 is connected to the drain of PMOS transistor M13, the source of PMOS transistor M11 is connected to the drain of PMOS transistor M2, and the drain of PMOS transistor M11 is grounded. By setting a bias circuit and core transistor related to the power supply voltage, the transistors are ensured to operate below 0.9V, thereby improving circuit reliability. Attached Figure Description

[0012] To more clearly illustrate the technical solutions in the embodiments of this application or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are some embodiments of this application, but not all embodiments. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort. In the accompanying drawings, the same reference numerals indicate the same parts.

[0013] Figure 1 This is a schematic diagram of the structure of an LDO circuit suitable for fast response in a UWB SOC, provided as an embodiment of this application. Detailed Implementation

[0014] To make the objectives, technical solutions, and advantages of the embodiments of this application clearer, the technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this application, not all embodiments. Based on the embodiments of this application, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this application.

[0015] The technical solutions of this application will be described in detail below with specific embodiments. These specific embodiments can be combined with each other, and the same or similar concepts or processes may not be described again in some embodiments.

[0016] Now see Figure 1 Based on the problems existing in the current UWB SOC, this application provides an LDO circuit with fast response suitable for UWB SOC, including: reference voltage Vref, fast feedback loop, and slow loop; The fast feedback loop includes: PMOS transistor M1, PMOS transistor M2, NMOS transistor M3, and PMOS transistor M4; the gate of PMOS transistor M1 is connected to the source of PMOS transistor M2, the source of PMOS transistor M1 is connected to the power supply terminal, the gate of PMOS transistor M2 is connected to the drain of NMOS transistor M3, the source of NMOS transistor M3 is connected to the drain of PMOS transistor M4, and the source of PMOS transistor M4 is connected to the output terminal. The slow circuit includes: an error amplifier EA, a PMOS transistor M5, and an NMOS transistor M7; the drain of the PMOS transistor M5 is connected to the non-inverting input of the error amplifier EA, the gate of the PMOS transistor M5 is connected to the gate of the PMOS transistor M4, the gate of the NMOS transistor M7 is connected to the output of the error amplifier EA, the source of the NMOS transistor M7 is grounded, and the inverting input of the error amplifier EA is connected to the reference voltage Vref. The LDO circuit further includes: a PMOS transistor M11 and a bias circuit, the bias circuit including a PMOS transistor M12 and a PMOS transistor M13; the drain of the PMOS transistor M12 is connected to the source of the PMOS transistor M13, the source of the PMOS transistor M12 is connected to the power supply terminal, the drain of the PMOS transistor M13 is grounded after being connected in series with a resistor, the gate of the PMOS transistor M11 is connected to the drain of the PMOS transistor M13, the source of the PMOS transistor M11 is connected to the drain of the PMOS transistor M2, and the drain of the PMOS transistor M11 is grounded.

[0017] Preferably, PMOS transistors M1, M2, and M4 are core transistors, and NMOS transistor M3 is an I / O transistor; PMOS transistors M11, M12, and M13 are I / O transistors. The core transistors need to operate at 0.9V, while the I / O transistors can operate up to 2.5V.

[0018] Preferably, the LDO circuit further includes NMOS transistor M6, PMOS transistor M8, PMOS transistor M9, and PMOS transistor M10, wherein the NMOS transistor M6 is an NMOS current mirror, and the PMOS transistors M8, M9, and M10 are PMOS current mirrors.

[0019] Specifically, the slow loop consisting of error amplifier EA, PMOS transistor M5, and NMOS transistor M7 is used to ensure that the source voltage of PMOS transistor M5 is proportional to the reference voltage Vref.

[0020] PMOS transistor M11 limits the drain voltage range of PMOS transistor M2. The source voltage of PMOS transistor M11 is determined by the bias circuit composed of PMOS transistors M12 and M13. The current of this bias circuit changes with the power supply voltage due to the diode connection of PMOS transistor M12. When the power supply voltage changes from 1.2-1.8V, the current changes from 0.26-3.74uA, and the output voltage Vp_bias1 changes from 0.05-0.45V. The source voltage of PMOS transistor M11 also changes from 0.45-0.8V, following the gate voltage. Therefore, the source-drain voltage range of PMOS transistor M2 is 0.4-0.65V, which meets the voltage requirements.

[0021] Preferably, the gates of PMOS transistor M4 and PMOS transistor M5 are connected, and PMOS transistor M4 mirrors the current in PMOS transistor M5. Since the output voltage Vout is not fed back to the error amplifier EA, its DC voltage accuracy is highly dependent on the DC gain of the fast loop.

[0022] This application provides an embodiment of a fast-response LDO circuit suitable for UWB SOC, comprising: a reference voltage Vref, a fast feedback loop, and a slow feedback loop; the fast feedback loop includes: PMOS transistor M1, PMOS transistor M2, NMOS transistor M3, and PMOS transistor M4; the gate of PMOS transistor M1 is connected to the source of PMOS transistor M2, the source of PMOS transistor M1 is connected to a power supply terminal, the gate of PMOS transistor M2 is connected to the drain of NMOS transistor M3, the source of NMOS transistor M3 is connected to the drain of PMOS transistor M4, and the source of PMOS transistor M4 is connected to an output terminal; the slow feedback loop includes: an error amplifier EA, PMOS transistor M5, and NMOS transistor M7; the drain of PMOS transistor M5 is connected to the non-inverting input terminal of error amplifier EA, the gate of PMOS transistor M5 is connected to the gate of PMOS transistor M4, and the NMOS transistor... The gate of transistor M7 is connected to the output of error amplifier EA. The source of NMOS transistor M7 is grounded. The inverting input of error amplifier EA is connected to the reference voltage Vref. The LDO circuit also includes a PMOS transistor M11 and a bias circuit, which includes PMOS transistors M12 and M13. The drain of PMOS transistor M12 is connected to the source of PMOS transistor M13. The source of PMOS transistor M12 is connected to the power supply terminal. The drain of PMOS transistor M13 is grounded after a series resistor. The gate of PMOS transistor M11 is connected to the drain of PMOS transistor M13. The source of PMOS transistor M11 is connected to the drain of PMOS transistor M2. The drain of PMOS transistor M11 is grounded. By setting a bias circuit and core transistor related to the power supply voltage, the transistors are ensured to operate below 0.9V, thereby improving circuit reliability.

[0023] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of this application, and are not intended to limit them. Although this application has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some or all of the technical features therein. Such modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of this application.

Claims

1. A LDO circuit suitable for fast response in a UWB SOC, characterized in that, include: Reference voltage Vref, fast feedback loop, slow feedback loop; The fast feedback loop includes: PMOS transistor M1, PMOS transistor M2, NMOS transistor M3, and PMOS transistor M4; the gate of PMOS transistor M1 is connected to the source of PMOS transistor M2, the source of PMOS transistor M1 is connected to the power supply terminal, the gate of PMOS transistor M2 is connected to the drain of NMOS transistor M3, the source of NMOS transistor M3 is connected to the drain of PMOS transistor M4, and the source of PMOS transistor M4 is connected to the output terminal. The slow circuit includes: an error amplifier EA, a PMOS transistor M5, and an NMOS transistor M7; the drain of the PMOS transistor M5 is connected to the non-inverting input of the error amplifier EA, the gate of the PMOS transistor M5 is connected to the gate of the PMOS transistor M4, the gate of the NMOS transistor M7 is connected to the output of the error amplifier EA, the source of the NMOS transistor M7 is grounded, and the inverting input of the error amplifier EA is connected to the reference voltage Vref. The LDO circuit further includes: a PMOS transistor M11 and a bias circuit, the bias circuit including a PMOS transistor M12 and a PMOS transistor M13; the drain of the PMOS transistor M12 is connected to the source of the PMOS transistor M13, the source of the PMOS transistor M12 is connected to the power supply terminal, the drain of the PMOS transistor M13 is grounded after being connected in series with a resistor, the gate of the PMOS transistor M11 is connected to the drain of the PMOS transistor M13, the source of the PMOS transistor M11 is connected to the drain of the PMOS transistor M2, and the drain of the PMOS transistor M11 is grounded.

2. The LDO circuit suitable for fast response in UWB SOC according to claim 1, characterized in that, The PMOS transistors M1, M2, and M4 are core transistors, and the NMOS transistor M3 is an I / O transistor; the PMOS transistors M11, M12, and M13 are I / O transistors.

3. The LDO circuit suitable for fast response in UWB SOC according to claim 1, characterized in that, The LDO circuit also includes NMOS transistor M6, PMOS transistor M8, PMOS transistor M9, and PMOS transistor M10. The NMOS transistor M6 is an NMOS current mirror, and the PMOS transistors M8, M9, and M10 are PMOS current mirrors.

4. The LDO circuit suitable for fast response in UWB SOC according to claim 2, characterized in that, The gate of the PMOS transistor M4 is connected to the gate of the PMOS transistor M5, and the PMOS transistor M4 mirrors the current in the PMOS transistor M5.

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