射频时钟电路以及时钟电路板

Abstract

本实用新型涉及时钟电路板技术领域，公开了一种射频时钟电路以及时钟电路板，电路包括：控制信号模块，控制信号模块用于接收编程信号，并输出编程信号的编程驱动信号；可编程时钟模块，可编程时钟模块和控制信号模块连接，用于接收预设时钟信号及编程驱动信号，并基于编程驱动信号针对预设时钟信号进行多次编程倍频处理，得到不同频率的编程时钟信号后输出。解决现有技术中固定时钟的应用场景受到限制的问题。

Claims

1. A radio frequency clock circuit, characterized by, The circuit includes: A control signal module, which receives programming signals and outputs programming drive signals for the programming signals; A programmable clock module, which is connected to the control signal module, is used to receive a preset clock signal and the programming drive signal, and to perform multiple programming frequency multiplication processes on the preset clock signal based on the programming drive signal to obtain programming clock signals of different frequencies and then output them. The programming drive signal includes a first programming drive signal and a second programming drive signal, and the programmable clock module includes a first frequency multiplication module and an extended second frequency multiplication module. The first frequency multiplication module is connected to the control signal module and is used to receive the preset clock signal and the first programming drive signal, and perform the first frequency multiplication process on the preset clock signal based on the first programming drive signal to obtain and output first clock signals of different frequencies. The extended secondary frequency multiplication module is connected to the control signal module and the primary frequency multiplication module respectively. It is used to receive the first clock signal and the second programming drive signal, and perform at least one frequency multiplication process on the first clock signal based on the second programming drive signal to obtain programming clock signals of different frequencies and then output them.

2. The circuit of claim 1, wherein, The first frequency multiplication module includes: The first main controller is connected to the control signal module and is used to receive the preset clock signal and the first programming drive signal, perform first-level frequency multiplication processing based on the first programming drive signal to obtain first-level clock signals of different frequencies and output them. A secondary processing unit is connected to the first main controller and the extended sub-frequency multiplier module, respectively, for receiving the primary clock signal, stabilizing the primary clock signal, obtaining first clock signals of different frequencies, and outputting them.

3. The circuit of claim 1, wherein, The extended sub-frequency multiplier module includes: At least one second frequency multiplier module is provided, which is used to receive the previous frequency multiplier clock signal, perform frequency multiplication processing, and then output the signal, wherein the previous frequency multiplier clock signal includes the first clock signal.

4. The circuit of claim 3, wherein, The second programming drive signal includes: a second analog-to-digital programming drive signal and a second digital-to-analog programming drive signal; the second frequency multiplier module includes: The second main controller is connected to the first frequency multiplication module and the control signal module respectively. It is used to receive the previous frequency multiplication clock signal and the second analog-to-digital programming drive signal, and after performing frequency multiplication processing on the previous frequency multiplication clock signal based on the second analog-to-digital programming drive signal, it sends the signal to the analog-to-digital converter of the FPGA. The third main controller is connected to the first frequency multiplication module and the control signal module respectively. It is used to receive the previous frequency multiplication clock signal and the second digital-to-analog programming drive signal, and after performing frequency multiplication processing on the previous frequency multiplication clock signal based on the second digital-to-analog programming drive signal, it sends the signal to the digital-to-analog converter of the FPGA.

5. The circuit of claim 1, wherein, The control signal module includes: The first communication port is used to receive programming signals of the first communication method; A conversion interface is connected to the first communication port and is used to receive the programming signal of the first communication mode, convert the programming signal of the first communication mode to obtain the programming drive signal of the second communication mode, and then output it. The second communication port is connected to both the conversion interface and the programmable clock module, and is used to transmit the programming drive signal of the second communication method to the programmable clock module.

6. The circuit of claim 1, wherein, Also includes: A power management module is connected to both the control signal module and the programmable clock module. It receives external power and adjusts it to supply power to the control signal module and the programmable clock module.

7. A clock circuit board, characterized by The clock circuit board includes the radio frequency clock circuit as described in any one of claims 1 to 6, wherein, The clock circuit board includes, from top to bottom, a top layer, a power layer, a high-speed signal layer, and a bottom layer; The top layer is used to house the control signal module and the programmable clock module; The power layer is used to house the power management module; The high-speed signal layer is used to set up clock signal lines; The underlying layer includes a connector for supplying power to the power management module and for transmitting clock signals and programming drive signals between the clock circuit board and the FPGA.

8. The clock circuit board of claim 7, wherein, The thickness of the wiring layer in the high-speed signal layer meets the preset thickness requirement, the line width of the wiring layer meets the preset line width requirement, and the interval between copper pouring and wiring is greater than the preset interval.

9. The clock circuit board of claim 8, wherein, The clock signal line of the high-speed signal layer adopts a star topology.

Images