A blade processor based on Phytium 5000C-16 6U VPX general-purpose GPGPU.

Abstract

This utility model relates to the field of computer hardware technology, specifically to a Phytium S5000C-16 6U VPX general-purpose GPGPU processing blade. It employs a Phytium S5000C-16 processor, a 100GPGPU daughter card, and integrates an N10G-X8I 40G Ethernet controller (two 40G signals) and a Netcom WX1860AL4 gigabit controller. The Phytium X100 bridge chip expands to include USB 3.0, VGA, SATA, and other interfaces. The GD32F407ZGT6BMC chip uses I2C / IPMB for temperature / voltage monitoring, power timing control, and slot identification. It works in conjunction with the EF2L45BG256B CPLD chip for overall board management. The clock unit uses a CETC Xingtuo TGEN6310HQFIGR buffer to provide multiple 100MHz differential clocks. The hot-swap unit uses an HZE5005 controller to suppress 12V power surges. This blade meets the requirements of domestic production, high-performance computing, and multi-scenario expansion, and is suitable for radar signal processing, data centers, and other scenarios.

Description

Technical Field

[0001] This utility model relates to the field of computer hardware technology, and more specifically, to a general-purpose GPGPU processing blade based on Phytium 5000C-16 6UVPX. Background Technology

[0002] In areas such as radar signal processing and high-density computing in data centers, existing general-purpose processing modules mainly rely on imported processors (such as Intel Xeon and AMD EPYC) and GPUs (such as NVIDIA Tesla) to accelerate computing through PCIe interfaces and transmit data with gigabit Ethernet or 10-gigabit Ethernet interfaces. These solutions typically adopt an "imported CPU + imported GPU" architecture, supplemented by third-party bridge chips to expand USB, display, and other interfaces. Health management relies on simple monitoring circuits integrated into the motherboard and lacks intelligent control from an independent BMC chip.

[0003] However, in existing technical solutions, the core chip supply chain is limited by foreign manufacturers, which poses information security risks, insufficient efficiency of heterogeneous computing power collaboration to cope with complex computing loads, and computing performance that is difficult to meet the needs of emerging scenarios, such as insufficient computing power density of traditional CPU+GPU combinations, limited interface scalability, and lack of fault warning and hot-swappable protection mechanisms.

[0004] In summary, there is a current need for a processing blade that integrates chip combination, high-performance GPGPU acceleration, multi-protocol high-speed interfaces, and intelligent health management architecture to achieve comprehensive hardware-to-system optimization and systematically solve the above problems. Utility Model Content

[0005] One objective of this invention is to provide a Phytium 5000C-16 6U VPX general-purpose GPGPU processing blade to solve the problems mentioned in the background art.

[0006] To achieve the above objectives, embodiments of this utility model provide a Phytium 5000C-16 6UVPX general-purpose GPGPU processing blade, comprising:

[0007] Phytium S5000C-16 processor, domestic GPGPU daughter card, Phytium X100 bridge chip, 40G Ethernet controller, Gigabit Ethernet controller, BMC chip, CPLD chip and VPX connector.

[0008] The Phytium S5000C-16 processor connects to the GPGPU daughter card via the PCIeX16 interface, and connects to the 40G Ethernet controller, Phytium X100 bridge chip and VPX connector via the C2C interface.

[0009] The Phytium X100 bridge chip connects to the Gigabit Ethernet controller via the PCIe channel and to the VPX connector and front panel display interface via the DP to VGA chip.

[0010] The BMC chip connects to the CPLD chip, temperature sensor, and power management module via the I2C interface, obtains the VPX slot number information via the GPIO interface, and communicates with the VPX connector via the IPMB bus.

[0011] In the above technical solution, the memory unit adopts a dual-channel DDR5 board-mounted memory design, and achieves a capacity of 32GB by using Hynix H5CG48MEBDX014N chips with both sides mounted. The maximum single channel supports 512GB of memory, and it is directly interconnected with the dual DDR5 channels of the Phytium S5000C-16 processor.

[0012] In the above technical solution, the GPGPU daughter card uses the Tianshu Zhixin Zhikai 100 chip, which is interconnected with the PCIe Gen4.0 x16 interface of the carrier board through the Gree C-242-4120P-B3R-01(QTH) connector, supporting 24TFLOPS single-precision computing power and 32GB HBM2E memory.

[0013] In the above technical solution, the 40G Ethernet controller uses the Muchuang N10G-X8I chip, which is connected through the processor's C2C1_PCIE_X8 interface and outputs two 40G signals to the VPX's P1 connector, supporting PCIeGen3.0x8 and 40G cryptographic acceleration functions.

[0014] In the above technical solution, the Gigabit Ethernet controller uses the Netcom WX1860AL4 chip, which is connected through the PCIeX2 channel of the Phytium X100 bridge chip. One 1000Base-T signal (multiplexed with the SK21101PHY chip with the fourth SERDES signal) is output to the front panel RJ45 interface, and four SERDES signals are output to the VPX connector.

[0015] In the above technical solution, the BMC chip adopts GD32F407ZGT6, which acquires the voltage / current data of the digital temperature sensor (-55~+125℃, ±2℃ accuracy) and ADC channel through the I2C interface, and reports the status information to the VPX baseboard through the IPMB bus. It works with the CPLD chip EF2L45BG256B to realize the power supply timing control of the whole board.

[0016] In the above technical solution, the clock unit adopts the TECHNOLOGY TGEN6310HQFIGR clock buffer, which takes in a 100MHz crystal oscillator signal and outputs multiple 100MHz differential clocks to peripherals such as the processor, GPGPU, and Ethernet controller, to ensure the synchronization of the same source clock for high-speed interfaces such as PCIe and C2C.

[0017] In the above technical solution, the hot-swappable unit uses an HZE5005 controller, which is connected in series to the 12V power input path. It communicates with the BMC via the SMBus protocol, receives power-on / off control commands and current threshold configuration information sent by the BMC, and realizes surge current suppression (maximum 25A) and overcurrent protection, supporting a wide voltage input of 4.5V-16V.

[0018] Compared with the prior art, the significant advantages of this utility model are:

[0019] 1. This utility model achieves significant improvements in computing performance, security and controllability, reliability and scenario adaptability through the selection of domestically produced chips, multi-dimensional hardware collaborative design and intelligent management architecture.

[0020] 2. It integrates a 16-core processor and a high-performance GPU, supporting multi-precision mixed computing, suitable for AI inference and signal processing, thereby achieving high-performance computing; it also provides interfaces such as 40G / Gigabit Ethernet, PCIe, RapidIO, VGA, and USB to adapt to multiple scenarios and make the interface richer.

[0021] 3. The BMC chip acquires 24 monitoring signals, including temperature, voltage, and current, in real time via the I2C interface. Combined with GPIO to obtain slot information, it dynamically reports the system status via the IPMB bus. Paired with the CPLD chip, it achieves precise control of power-on timing, linkage of reset logic, and rapid response to fault signals. Through a dual mechanism of LED indicators and remote alarms, the mean time between failures (MTBF) of the system is effectively improved, significantly enhancing the reliability of operation in complex scenarios, thereby achieving intelligent management of the blade hardware system. Attached Figure Description

[0022] The above and / or additional aspects and advantages of this utility model will become apparent and readily understood from the description of the embodiments taken in conjunction with the following drawings, in which:

[0023] Figure 1 This is a block diagram illustrating the principle of the blade of this utility model;

[0024] Figure 2 This is a block diagram of the processor interface of this utility model;

[0025] Figure 3 This is a layout diagram of the CPU and memory chips of this utility model;

[0026] Figure 4 This is an assembly diagram of the GPGPU daughter card and the 6U VPX carrier board of this utility model;

[0027] Figure 5 This is a block diagram of the extended functions of the X100 of this utility model;

[0028] Figure 6 This is a block diagram of the functional interface of the BMC unit of this utility model;

[0029] Figure 7 This is a functional block diagram of the N10G-X8I utility model;

[0030] Figure 8 This is a block diagram illustrating the principle of a gigabit network according to this utility model;

[0031] Figure 9 This is a block diagram of the internal GPU of the X100 chip of this utility model;

[0032] Figure 10 This is a block diagram of the X100 display design of this utility model;

[0033] Figure 11 This is a block diagram illustrating the principle of the USB interface of this utility model;

[0034] Figure 12 This is a block diagram illustrating the serial port connection principle of this utility model.

[0035] Figure 13 This is a block diagram illustrating the SATA connection principle of this utility model;

[0036] Figure 14 This is a block diagram of the CPLD principle of this utility model;

[0037] Figure 15 This is a block diagram illustrating the PCIE bus connection principle of this utility model;

[0038] Figure 16 This is a block diagram of the RTC circuit design of this utility model;

[0039] Figure 17 This is a block diagram of the WX1860 time synchronization design of this utility model;

[0040] Figure 18 This is a block diagram of the motherboard clock design for this utility model;

[0041] Figure 19 This is a system reset block diagram of this utility model;

[0042] Figure 20 This is a schematic diagram of the hot-swappable design principle of this utility model;

[0043] Figure 21 This is a layout diagram of the blade of this utility model. Detailed Implementation

[0044] To better understand the above-mentioned objectives, features, and advantages of this utility model, the present utility model will be further described in detail below with reference to the accompanying drawings and specific embodiments. It should be noted that, unless otherwise specified, the embodiments and features described in these embodiments can be combined with each other.

[0045] Many specific details are set forth in the following description in order to provide a full understanding of the present invention. However, the present invention may also be implemented in other ways different from those described herein. Therefore, the scope of protection of the present invention is not limited to the specific embodiments disclosed below.

[0046] The following reference Figures 1 to 21 This invention describes a general-purpose GPGPU processing blade based on the Phytium 5000C-166UVPX, according to some embodiments of the present invention. Its core components include:

[0047] The Phytium S5000C-16 processor (16-core FTC862 architecture, compatible with ARMv8.2 instruction set) is directly connected to the GPGPU daughter card via the PCIe X16 interface, and connected to the 40G Ethernet controller, Phytium X100 bridge chip and VPX connector via the C2C interface.

[0048] The Tianshu Zhixin Zhikai 100GPGPU daughter card is interconnected with the carrier board via a Gree C-242-4120P-B3R-01(QTH) connector;

[0049] The Phytium X100 bridge chip (integrating a low-power GPU, 3 DisplayPort 1.4 interfaces, 8 USB 3.1 Gen 1 interfaces, and 4 SATA 3.0 interfaces) is interconnected with the processor via a PCIe 3.0 x16 uplink;

[0050] The Muchuang N10G-X8I40G Ethernet controller and the Netcom WX1860AL4 Gigabit controller are connected to the system via the C2C interface and the PCIe channel of the X100 bridge chip, respectively.

[0051] The GD32F407ZGT6BMC chip and the EF2L45BG256BCPLD chip work together to manage power timing, status monitoring and IPMB communication via the I2C bus and GPIO interface.

[0052] In one embodiment, the processing blade further includes a memory unit, and the processor and memory unit include:

[0053] The Phytium S5000C-16 processor integrates a 16-core FTC862 architecture, two dual-channel DDR5-4000 controllers (maximum 512GB per channel), 16-lane PCIe 5.0 ports, and four C2C interfaces, supporting up to eight processors for direct connection expansion. Its PCIe x16 interface is used to connect a GPGPU, the C2C0 interface provides PCIe x8 / x4 signals, and the C2C1 interface connects to a 40G Ethernet controller and an x100 bridge chip.

[0054] The memory unit adopts a dual-channel DDR5 board design, using Hynix H5CG48MEBDX014N chips to achieve a capacity of 32GB and a theoretical bandwidth of 256GB / s.

[0055] In one embodiment, the processing blade also includes a GPGPU and a high-speed interconnect design:

[0056] The Zhikai 100GPGPU daughter card supports mixed computing of FP32 / FP16 / INT8, with a memory bandwidth of 800GB / s. It can be directly connected to the processor through the PCIeGen4.0x16 interface and is suitable for radar signal processing and AI inference scenarios.

[0057] PCIe Bus Expansion: The processor's C2C interface can be configured as a PCIe channel, where the PCIe x8[0:7] of C2C0 is connected to the VPXP3 connector, the PCIe x4[8:11] of C2C0 provides a RapidIOx4 interface through the PRB0400 chip, and the PCIe x8[0:7] of C2C1 is connected to the 40G Ethernet controller.

[0058] In one embodiment, the Phytium X100 bridge chip interconnects with the processor via a PCIe 3.0 x16 uplink and provides eight PCIe 3.0 lanes (including two x2 lanes and six x1 lanes) for expanding interfaces such as USB 3.0, VGA, and SATA. One DP interface is converted to a VGA signal via a CS5233AN chip and routed to the front panel and VPX connector.

[0059] Serial and SATA interfaces: The processor UART0 outputs RS232 signals through CPLD level conversion, and the X100 bridge chip MIO interface outputs RS422 signals through an RS422 transceiver; the X100 bridge chip provides 4 SATA 3.0 interfaces (1 connected to an mSATA hard drive, and 3 led to the VPX connector).

[0060] In one embodiment, the processing blade also includes health management and power control:

[0061] The BMC unit acquires voltage / current data (5V, 3.3V, 1.2V, etc.) from a digital temperature sensor (temperature range: -55~+125℃; accuracy: ±2℃) and ADC channels via an I2C interface, obtains the slot number via GPIO (backup pull-down is enabled), and reports status information via the IPMB bus. The GD32F407ZGT6 supports 1024KB Flash, 4 USART channels, and 24 ADC signals.

[0062] The CPLD unit (EF2L45BG256B) is responsible for power-on timing control, PCIe device reset and level conversion, and works with the BMC to realize the board-wide fault response;

[0063] Hot-swappable design: The HZE5005 controller is connected in series with the 12V power supply path, supporting surge current suppression (maximum 25A), overcurrent protection and I2C control for power on / off.

[0064] In one embodiment, the processing blade also includes a clock and reset system:

[0065] The clock unit uses the TECHNOLOGY TGEN6310HQFIGR buffer, which takes a 100MHz crystal oscillator signal as input and outputs 14 channels of 100MHz differential clocks (including CPU_C2C0_CLK, CPU_PCIEX16_CLK, etc.) to ensure that the PCIe, C2C and other interfaces are synchronized from the same source.

[0066] Reset logic: After receiving the BMC reset command, the CPLD first performs a 50ms power stabilization delay on the processor, then releases the reset signal, and subsequently triggers the peripheral reset to ensure that the timing is controllable.

[0067] In one embodiment, the processing blade also includes a time synchronization and expansion interface:

[0068] Second-level time synchronization: achieved through the AT8339RTC chip, supporting crystal oscillator stop monitoring and clock correction;

[0069] Sub-microsecond synchronization: Based on the IEEE1588V2 protocol supported by the WX1860AL4 controller, network time synchronization is achieved through hardware timestamps;

[0070] Reserved interfaces: Onboard LED indicators, test points and JTAG programming interface for easy debugging and maintenance.

[0071] In one embodiment, the blade adopts the 6UVPX standard size, with the front panel integrating an RJ45 network port, USB3.0, and VGA interface, and the rear panel leading out high-speed signals (40G / Gigabit Ethernet, PCIe, RapidIO, etc.) through a VPX connector. The overall layout conforms to the VITA46 specification.

[0072] Specifically, the blade uses the domestically produced S5000C-16 core processor as its core, with the MR100 serving as a high-speed computing acceleration and inference unit. It completes the front-end data processing and provides computing and inference resources to support the implementation of functions such as task management, system management, data fusion, comprehensive detection, and comprehensive identification.

[0073] In one embodiment, the processor can provide interfaces such as PCIe, DDR5, and debug serial port to the outside world.

[0074] like Figure 1 As shown, the S5000C / 16 processor has one PCIe x16 interface, four PCIe x1 interfaces, and four C2C x8 interfaces. The C2C interfaces can be configured as PCIe interfaces. Each PCIe x16 interface can be split into two PCIe x8 interfaces. In this design, the processor's PCIe x16 interface is used to connect to the GPU chip MR-100; the PCIe x8 [0:7] interfaces of C2C0 are brought out to connect to the P3 connector of the VPX; the PCIe x4 [8:11] interfaces of C2C0 are used to connect to one SRIO chip PRB0400, providing one RapidIO x4 interface to the VPX connector; the PCIe x8 [0:7] interfaces of C2C1 are used to connect to the 10 Gigabit Ethernet controller N10G-X8I, outputting two 40G Ethernet signals to the P1 connector of the VPX.

[0075] In one embodiment, PCIe x8 supports flipping.

[0076] The C2C1 PCIE x8 [8:15] is used to connect to the X100 chip, which is used to expand USB, VGA, SATA, PCIE, UART, and MIO interfaces. The X100 chip brings out two PCIE x2 ports. The first PCIE x2 port is connected to the Gigabit Ethernet controller WX1860AL4; it is converted to SERDES by four Shengke PHY chips SK21101 and connected to the VPX connector; the front-facing Gigabit network and the fourth SERDES port share a PHY chip to bring out a 1000Base-T to the front panel RJ45. The second PCIE x2 port is connected to a Jingxinwei RapidIO chip PRB0400, which brings out one RapidIO x4 port to the VPX P1 connector.

[0077] The GD32F407ZGT6 is used as the management controller (BMC). It monitors and collects signals such as board temperature, voltage, and current through sensors, identifies slot information, controls the power-on and power-off of the system and IPMB communication, and works with the CPLD chip EF2L45BG256B to complete the power timing management of the entire board.

[0078] The slot number signal on the blade is uniformly pulled up, and valid slot number information needs to be pulled down through the baseboard. The BMC obtains the slot number information through GPIO. The chassis number and rack number are sent to the Phytium S5000C-16 via serial port through the BMC chip.

[0079] The board has reserved LED indicators and test points for various power supplies or chips. For CPLD or FPGA chips, a JTAG programming interface is provided to facilitate later debugging and maintenance.

[0080] It is important to note that:

[0081] BMC (Baseboard Management Controller) is the baseboard management controller.

[0082] CPLD (Complex Programmable Logic Device) is a complex programmable logic device.

[0083] PCIE (Peripheral Component Interconnect Express) is a high-speed serial computer expansion bus standard.

[0084] IPMB (Intelligent Platform Management Bus) is an intelligent platform management bus.

[0085] In one embodiment, the processor selected is Phytium's latest Tengyun S5000C-16 processor, a high-performance, high-throughput 64-bit processor integrating 16 FTC862 processor cores, compatible with the ARMv8.2 instruction set specification; it supports KVM virtual machines; and integrates two dual-channel DDR5-4000 interfaces, 16-lane PCIe 5.0 interfaces, 4-lane PCIe 3.0 x1 interfaces, and 4-way x8-lane C2C interfaces, supporting up to 8-way processor direct connection expansion. The Tengyun S5000C-16 processor efficiently connects processor cores, storage, and I / O resources through an on-chip interconnect network supporting consistent memory, providing industry-leading computing performance, memory access bandwidth, and I / O expansion capabilities for large-scale business mainframes, high-performance server systems, and large-scale internet data centers.

[0086] Specifically, the S5000C-16 processor integrates two DDR5 memory channels, each with two ranks, and a maximum single-channel memory capacity of 512GB. The design utilizes surface-mount memory chips to complete the memory unit design of the board. Furthermore, to save space and improve layout utilization, two dual-channel configurations, each with 8GB chips mounted on both sides, are used to achieve the required 32GB memory capacity.

[0087] The theoretical bandwidth of memory can be calculated as follows: if the memory frequency is 4000MT / s, then the theoretical bandwidth of a single channel is 4000*64bit / 8=32GB / s, and the theoretical bandwidth of two dual channels is 32*8=256GB / s. However, the actual performance should be considered in relation to CPU performance, and the actual performance can be tested using STREAM software.

[0088] In the above design, the DDR5 memory chip H5CG48MEBDX014N is used as the DDR5 memory chip for the board. H5CG48MEBDX014N is a 16Gbit memory chip launched by Hynix. Since a dual-channel requires a total capacity of 8GB, each channel needs 10 memory chips (including 1 ECC chip).

[0089] In one embodiment, this invention employs the Tianshu Zhixin Zhikai 100 general-purpose GPU chip, mounted as a daughter card, with Greepu connectors of plug type C-242-4120P-B3R-01(QTH) and socket type C-232-4180S-B3R-01(QSH). The Zhikai 100 chip adopts a general-purpose GPU architecture, supporting multi-precision mixed computing such as FP32, FP16, and INT8. It features wide application coverage, high computing performance, low application cost, and strong implementation support, thus providing flexible programming capabilities, high performance, and cost-effectiveness.

[0090] Specifically, the Phytium X100 is a supporting chip for Phytium processors, which can be used with Phytium series processors to form a complete solution.

[0091] Specifically, the X100 integrates a low-power GPU, uses LPDDR4 for graphics display, and integrates three DisplayPort 1.4 display interfaces, two of which support a maximum resolution of 3840x2160@60Hz, and one of which supports a maximum resolution of 1920x1080@60Hz.

[0092] In one embodiment, the X100 has one DP channel, one of which is routed through a DP-to-VGA chip CS5233AN to VGA and extended to the front panel and VPX connector via a switching chip. The other DP channel is connected to the VPX connector. These two signals are reserved for future use; the system does not support the simultaneous use of two display chips.

[0093] like Figure 6As shown, in one embodiment, the health management system uses GigaDevice's GD32F407ZGT6 as the main chip, responsible for monitoring the overall board status and reporting information, as well as performing remote power on / off and reset operations. Temperature information can be obtained via the I2C interface, and voltage and current can be obtained using the ADC interface. The CPU's clock speed, model, number of cores, and other operating status can also be obtained through UART communication with the CPU. It supports IPMI custom command queries, can use GPIO to obtain slot information and identify the chassis number, and can report information via IPMB, providing status and fault alarm indications.

[0094] In one embodiment, a digital temperature sensor is incorporated into the system to monitor temperature, capable of monitoring a temperature range of -55 to +125°C with an accuracy of ±2°C. The CPU temperature is acquired and transmitted to the BMC unit via I2C. Simultaneously, to monitor the system's operating status, its built-in ADC channel monitors voltage and current levels at 5V, 3.3V, 2.5V, 1.2V, 1.1V, 1.0V, and 12V. The output data can be read via the I2C interface, and alarm and reset interrupt signals are generated if any abnormality occurs.

[0095] In one embodiment, the dual 40G interface design adopts the Muchuang N10-X8I solution.

[0096] In one embodiment, the Gigabit Ethernet interface design adopts the Netcom WX1860AL4 solution, which has four fully integrated Gigabit Ethernet Media Access Control (MAC) and Physical Layer (PHY) modules and four RGMII interfaces that can be connected to external PHYs.

[0097] like Figure 8 As shown, the Gigabit Ethernet outputs 4 SERDES ports, the WX1860 can output 4 RGMII interfaces, and the PHY chip SK21101 is used to bring out 4 SERDES ports to connect to the VPX connector and output 1 10000Base-T port (multiplexed with the 4th PHY chip).

[0098] In one embodiment, the VGA design uses the GPU integrated into the Phytium X100 chipset to implement the display function.

[0099] In one embodiment, the Phytium X100 chipset integrates a low-power GPU and extends one DisplayPort interface. The DP signal is converted to VGA via a Longxun LT8712 chip and connected to both the front panel and the VPX connector. One VGA interface is routed to the front panel, and another to the VPX connector.

[0100] like Figure 11As shown, in one embodiment, according to the requirements of blade technology, the front panel has 2 USB 3.0 ports and VPX 4 USB 2.0 ports, with the USB interfaces brought out from the IO expansion chip X100.

[0101] In one embodiment, this invention employs RS232 and RS422 serial port designs, implemented using the UART0 and X100 interface controllers of the S5000C-16, respectively. The S5000C-16 interface controller outputs one UART channel, which, after level conversion by the CPLD, outputs one RS232 signal via an RS232 transceiver to the VPX connector. The X100 transceiver outputs one MIO channel, which, via an RS422 transceiver, outputs one RS422 signal to the VPX connector.

[0102] In one embodiment, this blade uses an X100 controller to expand three SATA 3.0 interfaces, providing one SATA 3.0 interface to connect to an mSATA hard drive, and the three SATA 3.0 interfaces to a VPX connector.

[0103] In one embodiment, the CPLD is designed based on the Shanghai Anlu Information Technology EF2L45BG256B, embedding a block-type static random access memory, a digital signal processing module, and phase-locked loop resources. The EF2L45BG256B is used for power-on timing control of the various power supplies of the blade, and is responsible for monitoring system power-on and reset. It is also responsible for level conversion of CPU processor GPIO signals, UART signals, and LPC signals.

[0104] In one embodiment, the present invention adopts a rear-out PCIe interface design, using an S5000C-16 processor to directly output one PCIe 5.0 x16 interface, and the C2C0 interface to output one PCIe 5.0 x8 interface.

[0105] In one embodiment, this invention achieves time acquisition of more than a second using an RTC chip, specifically the AT8339 from Wuhan Xinjing Technology Co., Ltd.; and achieves time acquisition of less than a second using the IEEE 1588V2 protocol. IEEE 1588 is the Precision Time Protocol (PTP), used for synchronizing clocks in computer networks. Through this solution, the technical protocol requirements are met, enabling the blade to support time acquisition of both more and less than a second, thereby achieving timekeeping and time fault tolerance.

[0106] In one embodiment, considering that the IEEE 1588 V2 protocol requires hardware support, the 1588 protocol can be supported through the WX1860 network card chip.

[0107] In one embodiment, the clock chip selected is the TECHNOLOGY TGEN6310HQFIGR clock buffer (6310 chip).

[0108] In one embodiment, the TGEN6310HQFIGR has 10 LVPECL, CML, HCSL, LVDS and LVCMOS level clock outputs. It uses a crystal oscillator to input a 100MHz clock and designs two 6310 chips to output 100MHz differential clocks to peripherals such as the CPU, WX1860 and GPU.

[0109] Table 1 below lists the main clock sources required in this solution. The clock sources in the table can be mainly divided into two different types: the first type is the CORE clock and DDR clock, whose output clocks are mainly used for processor core logic operations and DDR operation; the second type is the clocks of high-speed interfaces such as PCIe and SGMII, whose output clocks are mainly used to provide low-frequency reference clocks for various high-speed interface modules.

[0110] Table 1 Main Clock Sources of the Module

[0111]

[0112]

[0113] It should be noted that most of the clocks required on the modules use differential clock inputs in order to obtain clock signals with stronger noise immunity and higher signal integrity.

[0114] In one embodiment, the S5000C / 16 mainly includes one 48MHz single-ended reference clock, two 100MHz differential PCIe clocks, and two 100MHz differential C2C clocks. The single-ended clock is implemented using a crystal oscillator. The PCIe channel-related clocks are implemented using clock buffers, ensuring the PCIe reference clocks are from the same source. A 100MHz differential clock source is input to the clock buffer, which uses a single CETC StarTop TBUF1510HQFIGR chip to generate the PCIe reference clock and distribute it to various PCIe devices. The CETC StarTop TBUF1510HQFIGR supports three clock inputs and ten clock outputs.

[0115] In one embodiment, the present invention also includes a reset design, as shown in Table 2 below, which lists the timing requirements of each device for the reset signal and the actual situation of the device.

[0116] Table 2 Time requirements for reset signals for each device

[0117]

[0118]

[0119] In one embodiment, system reset can be triggered in two ways: a system-wide reset signal or a CPLD logic soft reset. When the BMC receives a reset triggered by either method, it sends a reset signal to the CPLD. Upon receiving the signal, the CPLD sends a reset signal to the CPU. After the CPU completes its internal reset, it replies with a Reset# signal to the CPLD. Finally, the CPLD uses this signal to reset all peripheral devices. PCIe device reset is also performed by the CPLD acquiring the system reset data, and the reset duration and timing are controllable.

[0120] like Figure 20 As shown, in one embodiment, the hot-swap unit uses a domestically produced HZE5005 controller to suppress the inrush current when the blade is powered on. Fast turn-on reduces the load voltage drop during power switching. If the input power supply fails or is short-circuited, the fast turn-off function minimizes reverse current.

[0121] In one embodiment, a 4.5V to 16V power supply is used for power supply; when the voltage is low, an external power supply is required. Under undervoltage or overvoltage conditions, the power supply path is disabled.

[0122] In this utility model, the terms "installation," "connection," and "linking" should be interpreted broadly. For example, "connection" can be a fixed connection, a detachable connection, or an integral connection; "linking" can be a direct connection or an indirect connection through an intermediate medium. Those skilled in the art can understand the specific meaning of these terms in this utility model according to the specific circumstances.

[0123] In the description of this specification, the terms "one embodiment," "some embodiments," "specific embodiment," etc., refer to a specific feature, structure, material, or characteristic described in connection with that embodiment or example, which is included in at least one embodiment or example of the present invention. In this specification, the illustrative expressions of the above terms do not necessarily refer to the same embodiment or example. Furthermore, the specific features, structures, materials, or characteristics described may be combined in any suitable manner in one or more embodiments or examples.

[0124] The above are merely preferred embodiments of this utility model and are not intended to limit the scope of this utility model. Various modifications and variations can be made to this utility model by those skilled in the art. Any modifications, equivalent substitutions, or improvements made within the spirit and principles of this utility model should be included within the protection scope of this utility model.

Claims

1. A general GPGPU processing blade based on Feiteng 5000C-16 6U VPX, characterized in that, include: Phytium S5000C-16 processor, domestic GPGPU daughter card, Phytium X100 bridge chip, 40G Ethernet controller, Gigabit Ethernet controller, BMC chip, CPLD chip and VPX connector. The Phytium S5000C-16 processor is connected to the GPGPU daughter card via a PCIeX16 interface, and is connected to the 40G Ethernet controller, Phytium X100 bridge chip and VPX connector via a C2C interface. The Phytium X100 bridge chip is connected to the Gigabit Ethernet controller via the PCIe channel, and is connected to the VPX connector and the front panel display interface via the DP to VGA chip. The BMC chip is connected to the CPLD chip, temperature sensor and power management module through the I2C interface, obtains VPX slot number information through the GPIO interface, and communicates with the VPX connector through the IPMB bus.

2. The treatment blade of claim 1, wherein, The processing blade also includes a memory unit, which adopts a dual-channel DDR5 surface-mount memory design. It achieves a capacity of 32GB by using Hynix H5CG48MEBDX014N chips with both sides facing up and down, and is directly interconnected with the dual DDR5 channels of the Phytium S5000C-16 processor.

3. The treatment blade of claim 1, wherein: The GPGPU daughter card uses the Tianshu Zhixin Zhikai 100 chip and is interconnected with the PCIeGen4.0x16 interface of the carrier board via a connector.

4. The treatment blade of claim 1, wherein: The 40G Ethernet controller uses the Muchuang N10G-X8I chip, which is connected through the processor's C2C1_PCIE_X8 interface and outputs two 40G signals to the VPX's P1 connector.

5. The treatment blade of claim 1, wherein: The Gigabit Ethernet controller uses the Netcom WX1860AL4 chip, which is connected through the PCIeX2 channel of the Phytium X100 bridge chip. One 1000Base-T signal is output to the front panel RJ45 interface. The 1000Base-T signal and the fourth SERDES signal are multiplexed with the SK21101PHY chip. Four SERDES signals are output to the VPX connector.

6. The treatment blade of claim 1, wherein: The BMC chip uses GD32F407ZGT6, which collects voltage / current data from the digital temperature sensor and ADC channel via I2C interface, reports status information to the VPX baseboard via IPMB bus, and works with CPLD chip EF2L45BG256B to achieve power sequence control of the entire board.

7. The treatment blade of claim 1, wherein: The processing blade also includes a clock unit, which uses the CETC Startop TGEN6310HQFIGR clock buffer, inputs a 100MHz crystal oscillator signal, and outputs multiple 100MHz differential clocks to the processor, GPGPU, and Ethernet controller.

8. The treatment blade of claim 1, wherein: The processing blade also includes a hot-swap unit, which uses an HZE5005 controller connected in series with the 12V power input path and communicates with the BMC via the SMBus protocol to achieve surge current suppression and overcurrent protection.

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