基于寄存器的双端口存储器电路
By using a register-based dual-port memory circuit, the problem of low storage capacity that the on-chip memory provided by the manufacturer cannot meet at the selected process node is solved. It realizes that the read and write operations of port A and port B do not affect each other, and is suitable for cross-clock domain data exchange of complex integrated circuit chips.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Utility models(China)
- Current Assignee / Owner
- HEFEI XINCAN TECHNOLOGY CO LTD
- Filing Date
- 2025-08-05
- Publication Date
- 2026-07-17
AI Technical Summary
Existing on-chip memories offered by manufacturers cannot meet low storage capacity requirements at selected process nodes, or are too expensive to use.
A register-based dual-port memory circuit is adopted, including N basic memory units, a first address decoding unit and a second address decoding unit. By utilizing a first multi-bit register, a second multi-bit register, a third multi-bit register, a comparison unit and a synchronization unit, the read and write operations of port A and port B are made independent of each other, thus solving the metastability problem across clock domains.
This ensures that read and write operations on port A and port B under different clock domains do not interfere with each other, avoiding cross-clock domain issues, providing better portability and adaptability, and meeting the needs of low storage capacity application scenarios.
Smart Images
Figure CN224519303U_ABST
Abstract
Claims
1. A register-based dual-port memory circuit, characterized by, The register-based dual-port memory circuit includes: N basic memory units, a first address decoding unit, and a second address decoding unit, wherein each of the basic memory units is connected to the first address decoding unit and the second address decoding unit, respectively; The first address decoding unit is used to decode and output multiple write control signals to the corresponding memory basic unit according to the write address signal and write enable signal; Each of the memory basic units is used to write write data according to a write control signal and generate a corresponding read data signal to be output to the second address decoding unit; The second address decoding unit is used to select and output the corresponding read data signal based on the read address signal and the read enable signal.
2. The register-based dual-port memory circuit of claim 1, wherein, The basic memory unit includes: The system comprises a first multi-bit register, a second multi-bit register, a third multi-bit register, a comparison unit, and a synchronization unit. The second multi-bit register is connected to both the first and third multi-bit registers. The input of the comparison unit is connected to both the first and second multi-bit registers. The output of the comparison unit is connected to the synchronization unit. The output of the synchronization unit is connected to both the second and third multi-bit registers. The first multi-bit register is used to buffer the write data according to the write control signal; The comparison unit is used to compare the write data wdata_reg with the original wdata_lock of the second multi-bit register and output the corresponding indication signal dif to the synchronization unit; The synchronization unit is used to output a corresponding data path control signal according to the indication signal dif, so as to latch wdata_reg into the second multi-bit register or latch wdata_lock into the third multi-bit register.
3. The register-based dual-port memory circuit of claim 2, wherein, The first multi-bit register, the second multi-bit register, and the third multi-bit register are registers with an n-bit width.
4. The register-based dual-port memory circuit of claim 2, wherein, The synchronization unit includes a multiplexer, a first single-bit register, a second single-bit register, a first synchronizer, a second synchronizer, a first inverter, a second inverter, and an AND gate circuit. The first synchronizer is connected to both the first single-bit register and the second single-bit register. The output of the multiplexer is connected to the first single-bit register. The first input of the AND gate circuit is connected to the output of the second single-bit register. The second input of the AND gate circuit is connected to the output of the first synchronizer via the second inverter. The second synchronizer is connected to the second single-bit register, the first inverter, and the multiplexer.
5. The register-based dual-port memory circuit of claim 1, wherein, The basic memory unit is a pseudo-dual-port memory unit.
6. The register-based dual-port memory circuit of claim 1, wherein, The basic memory unit is a true dual-port memory unit.