An anti-interference smart door lock

Abstract

This utility model discloses an anti-interference smart door lock, including a main control module, a first interface module, a second interface module, and a display module. The main control module, the first interface module, the second interface module, and the display module are sequentially communicatively connected. The main control module transmits image data or control signals to the display module through the first interface module and the second interface module. By utilizing the shielding of the wiring harnesses of the first interface module and the second interface module, and by setting corresponding signal filtering units or voltage regulation units in the first interface module and the second interface module respectively, the integrity transmission of differential long signals is ensured, thereby improving the smart door lock's ability to suppress high-speed signal EMC radiation and anti-interference from the display module.

Description

Technical Field

[0001] This utility model relates to the field of anti-interference technology for smart door locks, and in particular to an anti-interference smart door lock. Background Technology

[0002] Currently, in the market, smart door locks with displays typically have their main control chip located on the front lock motherboard, while the LCD display is located on the rear lock. This usually requires the front lock's main control chip to be designed with MIPI high-speed signal routing to transmit the signal to the rear lock.

[0003] The MIPI CSI (Camera Serial Interface) is used to connect the processor and the display screen. Through the MIPI CSI interface, the differential data channel can transmit image data, the differential clock channel can synchronize data transmission, and there are also control signals such as reset, backlight control, and power enable to ensure the display works properly and shows corresponding information, such as unlock status and operation prompts.

[0004] When a smart lock has a camera module, MIPI CSI is typically used to connect the processor and the camera module. The image data captured by the camera is transmitted to the processor for processing via differential signals from the MIPI CSI interface. Functions such as facial recognition and surveillance video transmission rely on MIPI CSI to achieve efficient data transmission.

[0005] The advantage of MIPI CSI signals in smart locks lies in their high speed, which can meet the data transmission requirements of components such as displays and cameras in smart locks, thereby improving the overall performance of smart locks.

[0006] However, improper signal routing design in high-speed MIPI CSI can easily lead to excessive EMC electromagnetic radiation and interference, resulting in failure to meet safety certification requirements for EMC. Utility Model Content

[0007] Existing smart door locks use the MIPI CSI interface protocol to connect the processing chip and the display screen, which has problems such as unreasonable wiring and poor anti-interference ability.

[0008] To address the aforementioned issues, an anti-interference smart lock is proposed. By utilizing the shielding of the wiring harnesses of the first and second interface modules, and by setting corresponding signal filtering or voltage regulation units in the first and second interface modules respectively, the integrity transmission of differential long signals is ensured, thereby improving the smart lock's ability to suppress high-speed signal EMC radiation and resist interference.

[0009] An anti-interference smart door lock, comprising:

[0010] Main control module;

[0011] First interface module;

[0012] Second interface module;

[0013] Display module;

[0014] The main control module, the first interface module, the second interface module, and the display module are sequentially connected for communication.

[0015] The main control module transmits image data or control signals to the display module through the first interface module and the second interface module.

[0016] In the first possible implementation of the anti-interference smart door lock described in this utility model, the first interface module and the second interface module are TYPE_C USB interface modules.

[0017] In conjunction with the first possible embodiment of this utility model, in the second possible embodiment, the first interface module includes:

[0018] A first interface, a first group of signal transmission pins leading out from the first interface, a second group of signal transmission pins, and a third group of signal transmission pins;

[0019] The second interface module includes:

[0020] The second interface, the fourth group of signal transmission pins, the fifth group of signal transmission pins, and the sixth group of signal transmission pins leading out from the second interface;

[0021] The first group of signal transmission pins is communicatively connected to the fourth group of signal transmission pins;

[0022] The second group of signal transmission pins is communicatively connected to the fifth group of signal transmission pins;

[0023] The third group of signal transmission pins is communicatively connected to the sixth group of signal transmission pins.

[0024] In conjunction with the second possible implementation of this utility model, and in the third possible implementation, the first interface module includes:

[0025] First signal pin, second signal pin, third signal pin and fourth signal pin, first filter unit, second filter unit, third filter unit and fourth filter unit;

[0026] The first filtering unit, the second filtering unit, the third filtering unit, and the fourth filtering unit are electrically connected to the first signal pin, the second signal pin, the third signal pin, and the fourth signal pin, respectively, and are used to filter the signals transmitted by the first signal pin, the second signal pin, the third signal pin, and the fourth signal pin, respectively.

[0027] In conjunction with the third possible implementation of this utility model, in the fourth possible implementation, the first filtering unit, the second filtering unit, the third filtering unit, and the fourth filtering unit respectively include:

[0028] First capacitor, second capacitor, third capacitor, and fourth capacitor;

[0029] The first terminal of the first capacitor, the first terminal of the second capacitor, the first terminal of the third capacitor, and the first terminal of the fourth capacitor are respectively electrically connected to the lead-out lines of the first signal pin, the second signal pin, the third signal pin, and the fourth signal pin. The second terminals of the first capacitor, the second terminal of the second capacitor, the second terminal of the third capacitor, and the second terminal of the fourth capacitor are respectively grounded.

[0030] In conjunction with the second possible implementation of this utility model, and in the fifth possible implementation, the second interface module includes:

[0031] Fifth signal pin, sixth signal pin, seventh signal pin, eighth signal pin, ninth signal pin, fifth filter unit, sixth filter unit, seventh filter unit, eighth filter unit, ninth filter unit;

[0032] The fifth, sixth, seventh, eighth, and ninth filtering units are electrically connected to the fifth, sixth, seventh, eighth, and ninth signal pins, respectively, and are used to filter the signals transmitted through the fifth, sixth, seventh, eighth, and ninth signal pins, respectively.

[0033] In conjunction with the fifth and sixth possible embodiments of this utility model, the fifth, sixth, seventh, eighth, and ninth filtering units respectively include:

[0034] Fifth capacitor, sixth capacitor, seventh capacitor, eighth capacitor, ninth capacitor;

[0035] The first terminals of the fifth, sixth, seventh, eighth, and ninth capacitors are electrically connected to the leads of the fifth, sixth, seventh, eighth, and ninth signal pins, respectively. The second terminals of the fifth, sixth, seventh, eighth, and ninth capacitors are grounded.

[0036] In conjunction with the sixth and seventh possible embodiments of this utility model, the second interface module further includes:

[0037] First voltage regulator unit, second voltage regulator unit, third voltage regulator unit, fourth voltage regulator unit, fifth voltage regulator unit, sixth voltage regulator unit, tenth signal pin, eleventh signal pin, twelfth signal pin, thirteenth signal pin, fourteenth signal pin, fifteenth signal pin;

[0038] The first, second, third, fourth, fifth, and sixth voltage regulator units are electrically connected to the tenth, eleventh, twelfth, thirteenth, fourteenth, and fifteenth signal pins, respectively, and are used to regulate the voltage and prevent static electricity of the signals on the tenth, eleventh, twelfth, thirteenth, fourteenth, and fifteenth signal pins, respectively.

[0039] In conjunction with the seventh and eighth possible embodiments of this utility model, the first voltage regulator unit, the second voltage regulator unit, the third voltage regulator unit, the fourth voltage regulator unit, the fifth voltage regulator unit, and the sixth voltage regulator unit respectively include a first voltage regulator diode, a second voltage regulator diode, a third voltage regulator diode, a fourth voltage regulator diode, a fifth voltage regulator diode, and a sixth voltage regulator diode;

[0040] The first terminals of the first, second, third, fourth, fifth, and sixth Zener diodes are electrically connected to the tenth, eleventh, twelfth, thirteenth, fourteenth, and fifteenth signal pins, respectively. The second terminals of the first, second, third, fourth, fifth, and sixth Zener diodes are all connected together and then grounded.

[0041] The anti-interference smart lock described in this utility model utilizes the shielding of the wiring harnesses of the first interface module and the second interface module, and sets corresponding signal filtering units or voltage regulation units in the first interface module and the second interface module respectively, to ensure the integrity transmission of differential long signals, thereby improving the smart lock's ability to suppress EMC radiation and anti-interference of high-speed signals from the display module. Attached Figure Description

[0042] To more clearly illustrate the technical solutions in the embodiments of this utility model, the drawings used in the description of the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this utility model. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0043] Figure 1 This is a modular structure diagram of an anti-interference smart door lock according to the present invention;

[0044] Figure 2 This is a circuit diagram of the first interface module in an anti-interference smart door lock according to the present invention.

[0045] Figure 3 This is a circuit diagram of the second interface module in an anti-interference smart door lock according to the present invention.

[0046] Components and their serial numbers:

[0047] 100 – Main control module, 200 – First interface module, 300 – Second interface module, 400 – Display module. Detailed Implementation

[0048] The technical solutions of this utility model will now be clearly and completely described with reference to the accompanying drawings. Obviously, the described embodiments are only a part of the embodiments of this utility model, and not all of them. Based on the embodiments of this utility model, other embodiments obtained by those skilled in the art without creative effort are all within the scope of protection of this utility model.

[0049] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this invention pertains. The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the invention. The term "and / or" as used herein includes any and all combinations of one or more of the associated listed items.

[0050] It should be noted that when a component is referred to as being "fixed to" or "set on" another component, it can be directly on or indirectly on that other component. When a component is referred to as being "connected to" another component, it can be directly connected to or indirectly connected to that other component.

[0051] It should be understood that the terms "length", "width", "upper", "lower", "front", "rear", "left", "right", "vertical", "horizontal", "top", "bottom", "inner", "outer", etc., indicate the orientation or positional relationship based on the orientation or positional relationship shown in the accompanying drawings. They are only for the convenience of describing this application and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation. Therefore, they should not be construed as limitations on this application.

[0052] Furthermore, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of technical features indicated. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more of that feature. In the description of this application, "multiple" means two or more, unless otherwise explicitly specified.

[0053] Existing smart door locks use the MIPI CSI interface protocol to connect the processing chip and the display screen, which has problems such as unreasonable wiring and poor anti-interference ability.

[0054] To address the aforementioned issues, an anti-interference smart lock is proposed.

[0055] An anti-interference smart door lock, such as Figure 1 , Figure 1 This is a modular structure diagram of an anti-interference smart door lock according to the present invention, including a main control module 100, a first interface module 200, a second interface module 300, and a display module 400. The main control module 100, the first interface module 200, the second interface module 300, and the display module 400 are sequentially connected for communication. The main control module 100 transmits image data or control signals to the display module 400 through the first interface module 200 and the second interface module 300. By utilizing the shielding of the wiring harnesses of the first interface module 200 and the second interface module 300, and by setting corresponding signal filtering units or voltage regulation units in the first interface module 200 and the second interface module 300 respectively, the integrity transmission of differential long signals is ensured, thereby improving the smart door lock's ability to suppress EMC radiation and anti-interference from the high-speed signals of the display module 400.

[0056] Preferably, the first interface module 200 and the second interface module 300 are TYPE-C USB interface modules. In this embodiment, to prevent excessive EMC electromagnetic radiation and interference issues in the high-speed MIPI signal traces from the front lock to the rear lock, a TYPE-C interface combined with a TYPE-C USB cable is used to suppress EMC. The rear lock LCD display MIPI signal to TYPE-C interface circuit is included. The high-speed signal from the front lock is connected to the TYPE-C interface, and then connected to the TYPE-C interface of the rear lock motherboard LCD screen via a TYPE-C USB cable harness. Through the shielding of the TYPE-C interface and the TYPE-C cable harness, and the transmission of differential signals with equal lengths to ensure signal integrity, the purpose of suppressing EMC radiation is effectively achieved, improving anti-interference capability.

[0057] In this embodiment, the display module 400 may include a display interface and a display screen LCD. Those skilled in the art will know the connection structure between the main control chip of the main control module 100 and the first interface module 200, and between the second interface module 300 and the display module 400. This application uses two TYPE-C interfaces to suppress EMC and improve anti-interference capability.

[0058] Specifically, such as Figure 2 , Figure 2 This is a circuit diagram of the first interface module 200 in an anti-interference smart door lock according to the present invention. The first interface module 200 includes a first interface CON1, a first set of signal transmission pins (MIPI_TX_CLK_N, MIPI_TX_CLK_P) led out from the first interface CON1, a second set of signal transmission pins (MIPI_TX_D1_N, MIPI_TX_D1_P), and a third set of signal transmission pins (MIPI_TX_D0_N, MIPI_TX_D0_P).

[0059] like Figure 3 , Figure 3 This is a circuit diagram of the second interface module 300 in an anti-interference smart door lock according to the present invention. The second interface module 300 includes a second interface CON2, a fourth group of signal transmission pins (MIPI_TX_CLK_N, MIPI_TX_CLK_P), a fifth group of signal transmission pins (MIPI_TX_D1_N, MIPI_TX_D1_P), a sixth group of signal transmission pins (MIPI_TX_D0_N, MIPI_TX_D0_P) led out from the second interface CON2; and a first group of signal transmission pins. The signal transmission pins (MIPI_TX_CLK_N, MIPI_TX_CLK_P), the second group of signal transmission pins (MIPI_TX_D1_N, MIPI_TX_D1_P), the third group of signal transmission pins (MIPI_TX_D0_N, MIPI_TX_D0_P), the fourth group of signal transmission pins (MIPI_TX_CLK_N, MIPI_TX_CLK_P), and the fifth group of signal transmission pins (MIPI_TX_D1_N, MIPI_TX_D1_P) are connected for communication.

[0060] Further, the first interface module 200 includes: a first signal pin (LCD_RST), a second signal pin (LCD_DISPLAY_2.5V), a third signal pin (3D_TOF_CAM_1V8), and a fourth signal pin (LCD_EDA), a first filtering unit, a second filtering unit, a third filtering unit, and a fourth filtering unit; the first filtering unit, the second filtering unit, the third filtering unit, and the fourth filtering unit are electrically connected to the first signal pin (LCD_RST), the second signal pin (LCD_DISPLAY_2.5V), the third signal pin (3D_TOF_CAM_1V8), and the fourth signal pin (LCD_EDA), respectively, for filtering the signals transmitted by the first signal pin (LCD_RST), the second signal pin (LCD_DISPLAY_2.5V), the third signal pin (3D_TOF_CAM_1V8), and the fourth signal pin (LCD_EDA), respectively.

[0061] Furthermore, the first filter unit, the second filter unit, the third filter unit, and the fourth filter unit each include a first capacitor C1, a second capacitor C2, a third capacitor C3, and a fourth capacitor C4. The first terminal of the first capacitor C1, the first terminal of the second capacitor C2, the first terminal of the third capacitor C3, and the first terminal of the fourth capacitor C4 are respectively electrically connected to the lead-out lines of the first signal pin (LCD_RST), the second signal pin (LCD_DISPLAY_2.5V), the third signal pin (3D_TOF_CAM_1V8), and the fourth signal pin (LCD_EDA). The second terminals of the first capacitor C1, the second terminal of the second capacitor C2, the second terminal of the third capacitor C3, and the second terminal of the fourth capacitor C4 are respectively grounded.

[0062] Furthermore, the second interface module 300 includes a fifth signal pin (LCD_EDK), a sixth signal pin (LCD_ID0), a seventh signal pin (LCD_ID1), an eighth signal pin (VCC_1V8_LCD), a ninth signal pin (VCC_2V88_LCD), a fifth filtering unit, a sixth filtering unit, a seventh filtering unit, an eighth filtering unit, and a ninth filtering unit. The fifth filtering unit, the sixth filtering unit, the seventh filtering unit, the eighth filtering unit, and the ninth filtering unit are electrically connected to the fifth signal pin (LCD_EDK), the sixth signal pin (LCD_ID0), the seventh signal pin (LCD_ID1), the eighth signal pin (VCC_1V8_LCD), and the ninth signal pin (VCC_2V88_LCD), respectively, for filtering the signals transmitted by the fifth signal pin (LCD_EDK), the sixth signal pin (LCD_ID0), the seventh signal pin (LCD_ID1), the eighth signal pin (VCC_1V8_LCD), and the ninth signal pin (VCC_2V88_LCD), respectively.

[0063] Furthermore, the fifth, sixth, seventh, eighth, and ninth filter units each include a fifth capacitor C5, a sixth capacitor C6, a seventh capacitor C7, an eighth capacitor C8, and a ninth capacitor C9, respectively. The first terminals of the fifth capacitor C5, the sixth capacitor C6, the seventh capacitor C7, the eighth capacitor C8, and the ninth capacitor C9 are electrically connected to the leads of the fifth signal pin (LCD_EDK), the sixth signal pin (LCD_ID0), the seventh signal pin (LCD_ID1), the eighth signal pin VCC_1V8_LCD, and the ninth signal pin VCC_2V88_LCD, respectively. The second terminals of the fifth capacitor C5, the sixth capacitor C6, the seventh capacitor C7, the eighth capacitor C8, and the ninth capacitor C9 are grounded, respectively.

[0064] Furthermore, the second interface module 300 also includes a first voltage regulator unit, a second voltage regulator unit, a third voltage regulator unit, a fourth voltage regulator unit, a fifth voltage regulator unit, a sixth voltage regulator unit, a tenth signal pin MIPI_TX_D0_N, an eleventh signal pin MIPI_TX_D0_P, a twelfth signal pin MIPI_TX_D1_N, a thirteenth signal pin MIPI_TX_D1_P, a fourteenth signal pin MIPI_TX_CLK_N, and a fifteenth signal pin MIPI_TX_CLK_P; the first voltage regulator unit, the second voltage regulator unit, the third voltage regulator unit, the fourth voltage regulator unit, the fifth voltage regulator unit, and the sixth voltage regulator unit are respectively connected to the tenth signal pin MIPI_TX_D0_N, The eleventh signal pin MIPI_TX_D0_P, the twelfth signal pin MIPI_TX_D1_N, the thirteenth signal pin MIPI_TX_D1_P, the fourteenth signal pin MIPI_TX_CLK_N, and the fifteenth signal pin MIPI_TX_CLK_P are electrically connected to perform voltage regulation and electrostatic discharge protection on the signals of the tenth signal pin MIPI_TX_D0_N, the eleventh signal pin MIPI_TX_D0_P, the twelfth signal pin MIPI_TX_D1_N, the thirteenth signal pin MIPI_TX_D1_P, the fourteenth signal pin MIPI_TX_CLK_N, and the fifteenth signal pin MIPI_TX_CLK_P, respectively.

[0065] Furthermore, the first, second, third, fourth, fifth, and sixth voltage regulator units respectively include a first Zener diode ED5, a second Zener diode ED6, a third Zener diode ED7, a fourth Zener diode ED8, a fifth Zener diode ED9, and a sixth Zener diode ED10; the first terminals of the first Zener diode ED5, the second Zener diode ED6, the third Zener diode ED7, the fourth Zener diode ED8, the fifth Zener diode ED9, and the sixth Zener diode ED10 are respectively connected to the tenth signal pin. The 11th signal pin MIPI_TX_D0_N, the 12th signal pin MIPI_TX_D0_P, the 13th signal pin MIPI_TX_D1_P, the 14th signal pin MIPI_TX_CLK_N, and the 15th signal pin MIPI_TX_CLK_P are electrically connected. The second terminals of the first Zener diode ED5, the second Zener diode ED6, the third Zener diode ED7, the fourth Zener diode ED8, the fifth Zener diode ED9, and the sixth Zener diode ED10 are connected together and then grounded.

[0066] The anti-interference smart lock of this utility model utilizes the shielding of the wiring harnesses of the first interface module and the second interface module, and sets corresponding signal filtering units or voltage regulation units in the first interface module 200 and the second interface module 300 respectively, to ensure the integrity transmission of differential long signals, thereby improving the smart lock's ability to suppress EMC radiation and anti-interference of high-speed signals from the display module.

[0067] The above are merely preferred embodiments of the present utility model and are not intended to limit the present utility model. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of the present utility model shall be included within the protection scope of the present utility model.

Claims

1. An anti-interference smart door lock, characterized in that it comprises: Main control module; First interface module; Second interface module; Display module; The main control module, the first interface module, the second interface module, and the display module are sequentially connected for communication. The main control module transmits image data or control signals to the display module through the first interface module and the second interface module; The first interface module and the second interface module are connected by a wire harness to suppress EMC radiation.

2. The tamper-resistant smart door lock of claim 1, wherein, The first interface module and the second interface module are TYPE_C USB interface modules.

3. The tamper-resistant smart door lock of claim 2, wherein, The first interface module includes: A first interface, a first group of signal transmission pins leading out from the first interface, a second group of signal transmission pins, and a third group of signal transmission pins; The second interface module includes: The second interface, the fourth group of signal transmission pins, the fifth group of signal transmission pins, and the sixth group of signal transmission pins leading out from the second interface; The first group of signal transmission pins is communicatively connected to the fourth group of signal transmission pins; The second group of signal transmission pins is communicatively connected to the fifth group of signal transmission pins; The third group of signal transmission pins is communicatively connected to the sixth group of signal transmission pins.

4. The tamper-resistant smart door lock of claim 3, wherein, The first interface module also includes: First signal pin, second signal pin, third signal pin and fourth signal pin, first filter unit, second filter unit, third filter unit and fourth filter unit; The first filtering unit, the second filtering unit, the third filtering unit, and the fourth filtering unit are electrically connected to the first signal pin, the second signal pin, the third signal pin, and the fourth signal pin, respectively, and are used to filter the signals transmitted by the first signal pin, the second signal pin, the third signal pin, and the fourth signal pin, respectively.

5. The tamper-resistant smart door lock of claim 4, wherein, The first filtering unit, the second filtering unit, the third filtering unit, and the fourth filtering unit each include: First capacitor, second capacitor, third capacitor, and fourth capacitor; The first terminal of the first capacitor, the first terminal of the second capacitor, the first terminal of the third capacitor, and the first terminal of the fourth capacitor are respectively electrically connected to the lead-out lines of the first signal pin, the second signal pin, the third signal pin, and the fourth signal pin. The second terminals of the first capacitor, the second terminal of the second capacitor, the second terminal of the third capacitor, and the second terminal of the fourth capacitor are respectively grounded.

6. The anti-interference smart door lock according to claim 3, characterized in that, The second interface module also includes: Fifth signal pin, sixth signal pin, seventh signal pin, eighth signal pin, ninth signal pin, fifth filter unit, sixth filter unit, seventh filter unit, eighth filter unit, ninth filter unit; The fifth, sixth, seventh, eighth, and ninth filtering units are electrically connected to the fifth, sixth, seventh, eighth, and ninth signal pins, respectively, and are used to filter the signals transmitted through the fifth, sixth, seventh, eighth, and ninth signal pins, respectively.

7. The tamper-resistant smart door lock of claim 6, wherein, The fifth, sixth, seventh, eighth, and ninth filtering units respectively include: Fifth capacitor, sixth capacitor, seventh capacitor, eighth capacitor, ninth capacitor; The first terminals of the fifth, sixth, seventh, eighth, and ninth capacitors are electrically connected to the leads of the fifth, sixth, seventh, eighth, and ninth signal pins, respectively. The second terminals of the fifth, sixth, seventh, eighth, and ninth capacitors are grounded.

8. The tamper-resistant smart door lock of claim 7, wherein, The second interface module also includes: First voltage regulator unit, second voltage regulator unit, third voltage regulator unit, fourth voltage regulator unit, fifth voltage regulator unit, sixth voltage regulator unit, tenth signal pin, eleventh signal pin, twelfth signal pin, thirteenth signal pin, fourteenth signal pin, fifteenth signal pin; The first, second, third, fourth, fifth, and sixth voltage regulator units are electrically connected to the tenth, eleventh, twelfth, thirteenth, fourteenth, and fifteenth signal pins, respectively, and are used to regulate the voltage and prevent static electricity of the signals on the tenth, eleventh, twelfth, thirteenth, fourteenth, and fifteenth signal pins, respectively.

9. The tamper-resistant smart door lock of claim 8, wherein, The first voltage regulator unit, the second voltage regulator unit, the third voltage regulator unit, the fourth voltage regulator unit, the fifth voltage regulator unit, and the sixth voltage regulator unit each include a first voltage regulator diode, a second voltage regulator diode, a third voltage regulator diode, a fourth voltage regulator diode, a fifth voltage regulator diode, and a sixth voltage regulator diode, respectively. The first terminals of the first, second, third, fourth, fifth, and sixth Zener diodes are electrically connected to the tenth, eleventh, twelfth, thirteenth, fourteenth, and fifteenth signal pins, respectively. The second terminals of the first, second, third, fourth, fifth, and sixth Zener diodes are all connected together and then grounded.

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