一种数模混合芯片的充电控制电路及包括其的充电芯片、充电器

Abstract

本申请提供一种数模混合芯片的充电控制电路，包括数字电路、模拟电路；所述模拟电路中设置有基准源模块、选择模块和充电模块；所述基准源模块包括基准源1和基准源2；所述选择模块包括选择开关和基准切换控制电路。使用本实用新型提供的充电控制电路，可适应数字电路的不同供电方式，如当数字电路采用电池供电，电池过放时，使用本实用新型提供的充电控制电路，可实现充电电流不受电池过放的影响，稳定不跳变。

Claims

1. A charge control circuit of a digital-analog hybrid chip, characterized by comprising: The application relates to a reference voltage source module for a digital circuit and an analog circuit, wherein the analog circuit is provided with a reference source module, a selection module and a charging module; the reference source module comprises reference source 1 and reference source 2; the selection module comprises a selection switch and a reference switch control circuit.

2. The charge control circuit according to claim 1, characterized by, The reference source 1 is electrically connected with the digital circuit and is controlled by a register of the digital circuit; An input end of the selection switch is connected with the reference source 1 or the reference source 2, and an output end of the selection switch is connected with the charging module; The reference switch control circuit is connected with the selection switch and is used for controlling the selection switch to select the reference source 1 or the reference source 2 as the reference voltage of the charging module.

3. The charge control circuit according to claim 2, characterized by The reference switch control circuit comprises a P-type MOS tube and a current source; a source of the P-type MOS tube is connected with a power supply of the digital circuit; a gate of the P-type MOS tube is grounded; a drain of the P-type MOS tube is connected with the current source and an input end of the selection switch; and an opposite end of the current source connected with the P-type MOS tube is grounded.

4. The charge control circuit according to claim 2, characterized by The reference source 2 comprises a first N-type MOS tube, a second N-type MOS tube, a first P-type MOS tube, a second P-type MOS tube, a third P-type MOS tube, a first resistor, a second resistor and a first triode.

5. The charge control circuit according to claim 4, characterized by The source of the first P-type MOS tube, the source of the second P-type MOS tube and the source of the third P-type MOS tube are connected in parallel with a power supply; the gate of the first P-type MOS tube and the gate of the second P-type MOS tube are connected in parallel with the drain of the second P-type MOS tube; and the gate of the third P-type MOS tube is connected with the drain of the second P-type MOS tube. The drain of the first P-type MOS tube is connected with the drain of the first N-type MOS tube; and the source of the first N-type MOS tube is grounded. The gate of the first N-type MOS tube and the gate of the second N-type MOS tube are connected in parallel with the drain of the first N-type MOS tube. The drain of the second P-type MOS tube is connected with the drain of the second N-type MOS tube; the source of the second N-type MOS tube is connected with the first resistor; and an opposite end of the first resistor connected with the source of the second N-type MOS tube is grounded. The drain of the third P-type MOS tube is connected with the second resistor and an output end of the reference source 2 respectively; an opposite end of the second resistor connected with the drain of the third P-type MOS tube is connected with the emitter of the first triode. The base of the first triode is connected with the collector of the first triode; and the collector of the first triode is grounded.

6. The charge control circuit according to claim 4, characterized by The first triode in the reference source 2 can be replaced by a third N-type MOS tube.

7. The charge control circuit according to claim 6, characterized by The source of the first P-type MOS tube, the source of the second P-type MOS tube and the source of the third P-type MOS tube are connected in parallel with a power supply; the gate of the first P-type MOS tube and the gate of the second P-type MOS tube are connected in parallel with the drain of the second P-type MOS tube; and the gate of the third P-type MOS tube is connected with the drain of the second P-type MOS tube. The drain of the first P-type MOS is connected with the drain of the first N-type MOS; the source of the first N-type MOS is grounded; The gate of the first N-type MOS is connected in parallel with the gate of the second N-type MOS at the drain of the first N-type MOS; The drain of the second P-type MOS is connected with the drain of the second N-type MOS; the source of the second N-type MOS is connected with the first resistor, and the opposite end of the first resistor connected with the source of the second N-type MOS is grounded; The drain of the third P-type MOS is connected with the second resistor and the output end of the reference source 2 respectively; the opposite end of the second resistor connected with the drain of the third P-type MOS is connected with the drain of the third N-type MOS; The gate of the third N-type MOS is connected between the second resistor and the drain of the third N-type MOS; the source of the third N-type MOS is grounded.

8. A charging chip, characterized by, The charging control circuit comprises any one of claims 1-7.

9. A charger characterized by comprising: The charging chip comprises claim 8.

Images