A power-on reset circuit, chip, motherboard and electronic device

Abstract

This invention provides a power-on reset circuit, a chip, a motherboard, and an electronic device. The power-on reset circuit includes a clamping circuit, a delay circuit, and a shaping circuit. The clamping circuit, delay circuit, and shaping circuit are all electrically connected between a power supply and a common ground. The output terminal of the clamping circuit is electrically connected to the input terminal of the delay circuit, and the output terminal of the delay circuit is electrically connected to the input terminal of the shaping circuit. The clamping voltage output by the clamping circuit is used to control the delay circuit to output a delay control signal. The delay circuit, through the delay control signal, controls the shaping circuit to output a reset end signal. The power-on reset circuit of this embodiment helps to make the voltage at the end of the reset more stable, and it does not change with the length of the power-on time.

Description

Technical Field

[0001] This utility model relates to the field of integrated circuit technology, and in particular to a power-on reset circuit, a chip, a motherboard, and an electronic device. Background Technology

[0002] The process of the chip's power supply voltage slowly rising from 0 to 1 is called the power-on process. During the power-on process, a power-on reset circuit is often required to ensure the normal operation of the chip's internal signals. That is, before or just before the power supply voltage completes the power-on process, the power-on reset circuit always outputs a reset signal at zero potential. This reset signal is used to initialize the chip's internal digital circuits, thereby enabling the chip's internal digital circuits to operate normally and reliably after the chip system is powered on normally.

[0003] In some earlier technologies, power-on reset circuits generally use capacitors and resistors to form an RC delay circuit as the key to achieve the function. When this RC delay circuit uses the current generated by the power supply to control the delay, it is easy to cause poor voltage stability and consistency at the end of the reset when the delay time is different, and it will change with the delay time. Utility Model Content

[0004] This invention provides a power-on reset circuit, chip, motherboard, and electronic device to solve the problem that the voltage stability of existing power-on reset circuits is poor at the end of the reset process and changes with the duration of the delay.

[0005] This utility model embodiment provides a power-on reset circuit, which includes a clamping circuit, a delay circuit, and a shaping circuit;

[0006] The clamping circuit, the delay circuit, and the shaping circuit are all electrically connected between the power supply and the common ground. The output terminal of the clamping circuit is electrically connected to the input terminal of the delay circuit, and the output terminal of the delay circuit is electrically connected to the input terminal of the shaping circuit.

[0007] The clamping voltage output by the clamping circuit is used to control the delay circuit to output a delay control signal, and the delay circuit controls the shaping circuit to output a reset end signal through the delay control signal.

[0008] Optionally, the clamping circuit includes a first transistor and a second transistor, both of which are diode-type devices;

[0009] The pin of the first transistor, which is equivalent to the anode of a diode, and the pin of the second transistor, which is equivalent to the anode of a diode, are electrically connected, and the node where the two are connected forms the output terminal of the clamping circuit.

[0010] In the first transistor and the second transistor, one transistor is equivalent to the cathode of a diode and its pin is electrically connected to the power supply, while the other transistor is equivalent to the cathode of a diode and its pin is electrically connected to the common ground.

[0011] Optionally, the first transistor is a PMOS, the second transistor is an NMOS, and the clamping circuit further includes a first resistor;

[0012] The source of the first transistor is electrically connected to the power supply, and the first resistor is connected in series between the source and the gate of the first transistor.

[0013] The drain of the first transistor is electrically connected to the drain of the second transistor, the drain of the second transistor is electrically connected to the gate of the second transistor, and the source of the second transistor is electrically connected to common ground.

[0014] Optionally, the delay circuit includes a third transistor and a capacitor, wherein the third transistor has a control electrode, an input electrode, and an output electrode;

[0015] The output terminal of the clamping circuit is electrically connected to the control electrode, the input electrode is electrically connected to the power supply, the output electrode is electrically connected to one end of the capacitor, and the node where the two are connected forms the output terminal of the delay circuit. The other end of the capacitor is electrically connected to the common ground.

[0016] Optionally, the third transistor is a PMOS, the gate of the third transistor is the control electrode, the source of the third transistor is the input electrode, and the drain of the third transistor is the output electrode.

[0017] Optionally, the power-on reset circuit further includes a discharge circuit;

[0018] The discharge circuit is electrically connected between the power supply and the input terminal of the shaping circuit, and the discharge circuit is used to release the charge of the capacitor.

[0019] Optionally, the discharge circuit includes a fourth transistor, which is a device equivalent to a diode.

[0020] Optionally, the fourth transistor is a PMOS, and the discharge circuit further includes a second resistor;

[0021] The source of the fourth transistor is electrically connected to the power supply, and the drain of the fourth transistor is electrically connected to the input terminal of the reset circuit.

[0022] The second resistor is connected in series between the source and the gate of the fourth transistor.

[0023] Optionally, the shaping circuit includes a buffer consisting of a plurality of transistors.

[0024] This utility model embodiment also provides a chip, which includes any of the aforementioned power-on reset circuits.

[0025] This utility model embodiment also provides a motherboard, which includes the aforementioned chip.

[0026] This utility model embodiment also provides an electronic device, which includes the aforementioned motherboard.

[0027] Compared with the prior art, the present invention has the following advantages:

[0028] The power-on reset circuit of this embodiment utilizes a clamping circuit to generate a stable and constant voltage signal. This voltage signal is used as a control quantity to control the delay circuit to output a delay control signal, which in turn triggers the shaping circuit to output a reset end signal. Compared with traditional power-on reset circuits, it no longer employs a simple RC delay circuit structure based on current magnitude for delay control. This helps to ensure that the voltage at the end of the reset is more stable and consistent, and does not change with the length of the power-on time. Attached Figure Description

[0029] To more clearly illustrate the technical solutions of the embodiments of this utility model, the drawings used in the description of the embodiments of this utility model will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this utility model. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0030] Figure 1 This is a schematic diagram of the basic circuit structure of a power-on reset circuit according to an embodiment of this utility model;

[0031] Figure 2 This is a schematic diagram of the first clamping circuit according to an embodiment of the present utility model;

[0032] Figure 3 This is a schematic diagram of the second clamping circuit according to an embodiment of the present utility model;

[0033] Figure 4 This is a schematic diagram of the third clamping circuit according to an embodiment of the present invention;

[0034] Figure 5 This is a circuit diagram of a power-on reset circuit according to an embodiment of the present utility model;

[0035] Figure 6 This is a schematic diagram of the basic circuit structure of another power-on reset circuit according to an embodiment of the present invention;

[0036] Figure 7This is a circuit diagram of another power-on reset circuit according to an embodiment of the present invention. Detailed Implementation

[0037] To make the above-mentioned objectives, features and advantages of this utility model more apparent and understandable, the utility model will be further described in detail below with reference to the accompanying drawings and specific embodiments.

[0038] like Figure 1 The diagram shown is a schematic representation of the basic circuit modules of a power-on reset circuit according to an embodiment of the present invention. The power-on reset circuit includes a clamping circuit 10, a delay circuit 20, and a shaping circuit 30.

[0039] The clamping circuit 10, the delay circuit 20, and the shaping circuit 30 are all electrically connected between the power supply VCC and the common ground GND, and, combined with Figure 1 As illustrated, the output terminal OUT1 of the clamping circuit 10 is electrically connected to the input terminal IN1 of the delay circuit 20. The clamping circuit 10 outputs a stable clamping voltage signal to the delay circuit 20. The output terminal OUT2 of the delay circuit 20 is electrically connected to the input terminal IN2 of the shaping circuit 30. Under the action of the clamping voltage signal, the delay circuit 20 outputs a delay control signal to the shaping circuit 30 after a preset delay time. Then, triggered by the aforementioned delay control signal, the level signal at the output terminal of the shaping circuit 30 is flipped and switched, outputting a reset end signal to indicate that other hardware connected to the power-on reset circuit can power on and operate according to the set timing.

[0040] Therefore, in the power-on reset circuit of this embodiment, during the power-on process of the circuit powered on by the power supply VCC, the clamping circuit 10 can output a stable and constant clamping voltage signal as a control quantity to control the delay circuit 20 to output a delay control signal, and then trigger the shaping circuit 30 to output a signal indicating that the reset process can end. Compared with the traditional power-on reset circuit, it no longer uses a simple RC delay circuit structure based on the current magnitude to achieve delay control, which helps to make the voltage at the end of the reset more stable and not change with the length of the power-on time.

[0041] Optionally, such as Figures 2 to 4 The diagram illustrates a clamping circuit 10 formed by connecting different types of transistors in an embodiment of this invention. These clamping circuits 10 all share the common feature of using two transistors equivalent to diodes for connection. During connection, the same pins of the two transistors (corresponding to the anodes of the equivalent diodes) are connected, resulting in a head-to-head connection between the two equivalent diodes. Thus, the node where the two equivalent diodes are connected forms the output terminal OUT1 of the clamping circuit 10, and the voltage at this node is clamped and fixed by the two equivalent diodes.

[0042] Specifically, such as Figure 2 As illustrated, in one embodiment, two transistors equivalent to diodes include a first transistor 101 and a second transistor 102, which can be directly used as diodes. The cathode of one diode is electrically connected to the power supply VCC, and the cathode of the other diode is electrically connected to the common ground GND. The node where the anodes of the two diodes are connected serves as the output terminal OUT1 of the clamping circuit 10.

[0043] like Figure 3 In one embodiment, two transistors equivalent to diodes include a first transistor 101 and a second transistor 102, which can specifically be bipolar junction transistors (BJTs). The first transistor 101 can be a PNP transistor, and the second transistor 102 can be an NPN transistor. The base (b) and emitter (e) of the first transistor 101 are connected, making it equivalent to a diode. The emitter (e) of the first transistor 101 is equivalent to the cathode of the diode, and the collector (c) of the first transistor 101 is equivalent to the anode of the diode. The base (b) and collector (c) of the second transistor 102 are connected, making it equivalent to a diode. The emitter (e) of the second transistor 102 is equivalent to the cathode of the diode, and the collector (c) of the second transistor 102 is equivalent to the anode of the diode. The emitter (e) of the first transistor 101 is electrically connected to the power supply VCC, and the emitter (e) of the second transistor 102 is electrically connected to the common ground GND. The collectors (c) of the first transistor 101 and the second transistor 102 are connected together to form a diode. Figure 2 In a similar head-to-head connection, the node where the two collectors c are connected serves as the output terminal OUT1 of the clamping circuit 10.

[0044] like Figure 4 In one embodiment, two transistors equivalent to diodes include a first transistor 101 and a second transistor 102, which can be MOSFETs. The first transistor 101 can be a PMOS, and the second transistor 102 can be an NMOS. The gate G and source S of the first transistor 101 are connected, making it equivalent to a diode. The source S of the first transistor 101 is equivalent to the cathode of the diode, and the drain D of the first transistor 101 is equivalent to the anode of the diode. The gate G and drain D of the second transistor 102 are connected, making it equivalent to a diode. The source S of the second transistor 102 is equivalent to the cathode of the diode, and the drain D of the second transistor 102 is equivalent to the anode of the diode. The source S of the first transistor 101 is electrically connected to the power supply VCC, and the source S of the second transistor 102 is electrically connected to the common ground GND. The drain D of the first transistor 101 and the drain D of the second transistor 102 are connected together to form a diode. Figure 2 In a similar head-to-head connection, the two drains D are connected as the output terminal OUT1 of the clamping circuit 10.

[0045] It should be noted that, regardless of the method used Figures 2 to 4 In which type of clamping circuit 10, because the first transistor 101 and the second transistor 102, which are equivalent diodes, are connected head-to-head, the second transistor 102 remains in a conducting state during power-on, and the voltage output by the clamping circuit 10 is always clamped and maintained as the voltage across the second transistor 102. Figure 4 Taking the schematic clamping circuit 10 as an example, when the second transistor 102 is turned on, the voltage output by the clamping circuit 10 is V. out1 The voltage V across the second transistor 102 GS Equal to the threshold voltage V at which the second transistor 102 is turned on thn Therefore V out1 =V thn V out1 Clamping held as V thn .

[0046] Optionally, such as Figure 4 As illustrated, when the first transistor 101 is a PMOS and the second transistor 102 is an NMOS, the PMOS is connected in a diode configuration. While connecting its gate G and source S to conduct, a first resistor 103 is connected in series between its gate G and source S. Thus, the first resistor 103 can protect the gate G of the PMOS and prevent it from being broken down by the power supply VCC.

[0047] Optionally, such as Figure 5 As shown, the delay circuit 20 of this embodiment includes a third transistor 201 and a capacitor 202. The third transistor 201 has three electrodes, including a control electrode 201a, an input electrode 201b, and an output electrode 201c. The control electrode 201a is used to control the on / off state between the input electrode 201b and the output electrode 201c. Specifically, when the third transistor 201 is a MOS transistor, the gate is the control electrode 201a, one of the source and drain is the input electrode 201b, and the other is the output electrode 201c. When the third transistor 201 is a bipolar transistor, the base is the control electrode 201a, one of the emitter and collector is the input electrode 201b, and the other is the output electrode 201c.

[0048] The output terminal OUT1 of the clamping circuit 10 is electrically connected to the control electrode 201a, the input electrode 201b is electrically connected to the power supply VCC, the output electrode 201c is electrically connected to one end of the capacitor 202, and the node where the two are connected forms the output terminal OUT2 of the delay circuit 20. The other end of the capacitor 202 is electrically connected to the common ground GND.

[0049] Combination Figure 5As illustrated, when the clamping voltage signal transmitted at the output terminal OUT1 causes the input electrode 201b and the output electrode 201c to conduct, the power supply VCC begins to charge the capacitor 202. The time taken for the capacitor 202 to slowly charge forms the delay duration of the power-on reset process. In this embodiment of the invention, the delay circuit 20 uses a transistor with a control electrode to control the capacitor's power-on process. Compared to an RC delay circuit, it can control VCC... out1 The clamp is maintained at a higher V. thn This allows the capacitor to charge at a slower rate, resulting in a longer delay time without the need for a larger capacitor as in RC delay circuits, thus significantly saving circuit area.

[0050] Optionally, such as Figure 5 As shown, the third transistor 201 is a PMOS, the gate of the third transistor 201 is the control electrode 201a, the source of the third transistor 201 is the input electrode 201b, and the drain of the third transistor 201 is the output electrode 201c.

[0051] Optionally, in the foregoing Figure 5 Based on the illustrated power-on reset circuit, during power-on, the power supply VCC charges capacitor 202. To ensure the capacitor can be recharged upon the next power-on, capacitor 202 needs to be discharged after the power-on reset process. Therefore, as shown... Figure 6 As shown, the power-on reset circuit of this utility model embodiment also includes a discharge circuit 40, which is electrically connected between the power supply VCC and the input terminal IN2 of the shaping circuit 30. The discharge circuit 40 is used to release the charge of the capacitor 202.

[0052] Optionally, such as Figure 6 As shown, the discharge circuit 40 includes a fourth transistor 401, which is a device equivalent to a diode. It should be noted that the fourth transistor 401 can be a diode, or a transistor or MOSFET connected in a diode configuration. The following section will discuss this further. Figure 7 Taking a MOSFET as an example, the equivalent structure of a transistor using a diode connection can be found in the aforementioned embodiments. Figure 3 Examples and explanations are omitted here.

[0053] When the fourth transistor 401 is a PMOS, its gate G and source S are connected to form the cathode of an equivalent diode, and its drain D serves as the anode. The source S of the fourth transistor 401 is electrically connected to the power supply VCC, and the drain D of the fourth transistor 401 is electrically connected to the input terminal IN2 of the shaping circuit 30. Referring to the diagram, it can be seen that the drain D of the fourth transistor 401 is also electrically connected to the capacitor 202. Therefore, since the equivalent diode formed by the fourth transistor 401 is reverse-connected in the circuit, it does not function during power-on, only releasing a weak leakage current. After power-on, as the capacitor 202 is fully charged, the voltage of OUT2 is also high. At this time, the power supply VCC and the drain D connected to the source S and gate G of the fourth transistor 401 are both high, and the source S and drain D of the fourth transistor 401 are not conducting. Therefore, the discharge circuit 40 is temporarily inactive. After the power supply VCC is turned off, the source S and gate G of the fourth transistor 401 become low level, and the source S and drain D of the fourth transistor 401 are turned on. The charge on the capacitor 202 can be released through the fourth transistor 401 to clear the charge and prepare for the next power-on reset.

[0054] Optionally, such as Figure 7 As shown, when the fourth transistor 401 is a PMOS, the discharge circuit 40 further includes a second resistor 402. The source G of the fourth transistor 401 is electrically connected to the power supply VCC, and the drain D of the fourth transistor 401 is electrically connected to the input terminal IN2 of the shaping circuit 30. The second resistor 402 is connected in series between the source S and the gate G of the fourth transistor 401. The second resistor 402 can protect the gate G of the PMOS from breakdown from the power supply VCC.

[0055] Optionally, the shaping circuit 30 in the power-on reset circuit of this embodiment can be a buffer composed of multiple transistors. For example... Figure 7 As shown, this buffer may include PMOS 301, NMOS 302, PMOS 303, and NMOS 304. The source S of PMOS 301 is electrically connected to the power supply VCC, the drain D of PMOS 301 is electrically connected to the drain D of NMOS 302, the gate G of PMOS 301 is electrically connected to the gate G of NMOS 302 to form the input terminal IN2 of the reset circuit 30, and the source S of NMOS 302 is electrically connected to the common ground GND.

[0056] The source (S) of PMOS 303 is electrically connected to the power supply VCC. The drain (D) of PMOS 303 is electrically connected to the drain (D) of NMOS 304, forming the output terminal of the shaping circuit 30, used to output the POR signal. The gate (G) of PMOS 303 is electrically connected to the gate (G) of NMOS 304, and is also electrically connected to the drain (D) of PMOS 301 and the drain (D) of NMOS 302. The source (S) of NMOS 304 is electrically connected to the common ground (GND).

[0057] In this embodiment of the invention, a buffer is used as the structure of the shaping circuit 30, which can perform pulse shaping on the signal transmitted from the previous stage, and can shape the slowly changing input signal into a rectangular pulse with steep edges.

[0058] Let's combine them again below. Figure 7 The diagram illustrates the working process of the power-on reset circuit provided in this embodiment of the present invention in a more detailed way.

[0059] The power supply voltage VCC of the chip is powered on in three stages. In the first stage, the power supply VCC voltage rises slowly, until it is below V... thn +V thp Previously (V) thp (This refers to the turn-on threshold voltage of the PMOS corresponding to the third transistor 201). When the PMOS corresponding to the third transistor 201 is in the off state, the voltage V at the output terminal OUT2 of the delay circuit 20 is... out2 =0, correspondingly, the voltage Vpor at the output of the shaping circuit 30 is 0, that is, Vpor provides a low-level signal to keep other hardware connected to the power-on reset circuit in a reset state. In the second stage, when the voltage of the power supply VCC is greater than V... thn +V thp Then, the PMOS corresponding to the third transistor 201 is turned on, charging capacitor 202. Since the gate voltage of the third transistor 201 is clamped at V... thn Therefore, the charging current of capacitor 202 is relatively small, and the voltage V is relatively low. out2 The rise rate is much slower than the voltage used to charge the capacitor in a traditional RC delay circuit. In the third stage, when the voltage V... out2 Greater than V thn Then, NMOS 302 turns on, Vpor = 1, which becomes a high level, ending the reset function.

[0060] This invention also provides a chip in which the power-on reset circuit disclosed in any of the foregoing embodiments can be integrated. By integrating the power-on reset circuit into the chip, at least the power supply voltage can remain consistent when the chip finishes power-on reset under different delay durations. Furthermore, it can also reduce chip area overhead and power consumption.

[0061] In addition, this utility model embodiment also discloses a motherboard, which uses a printed circuit board or flexible circuit board as a carrier and solders the aforementioned chips on it, which can improve the working reliability of the motherboard and reduce the development cost and power consumption of the motherboard.

[0062] Finally, this utility model embodiment also discloses an electronic device, which may include the motherboard of the aforementioned embodiments. This electronic device is not limited to hardware devices such as mobile phones, computers, smartwatches, and smart bracelets that have a System-on-Chip (SoC) chip. Electronic devices using the aforementioned chip have a more stable and reliable power-on reset process, and both device cost and power consumption can be reduced.

[0063] The above description is merely a specific embodiment of this utility model, but the protection scope of this utility model is not limited thereto. Any variations or substitutions that can be easily conceived by those skilled in the art within the technical scope disclosed in this utility model should be included within the protection scope of this utility model. Therefore, the protection scope of this utility model should be determined by the scope of the claims.

[0064] It should be noted that, for those skilled in the art, several improvements and modifications can be made without departing from the principles described in this utility model, and these improvements and modifications should also be considered within the scope of protection of this utility model.

[0065] Finally, it should be noted that in this document, relational terms such as "first" and "second" are used only to distinguish one entity or operation from another, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Furthermore, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or terminal device that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or terminal device. Without further limitations, an element defined by the phrase "comprising one..." does not exclude the presence of other identical elements in the process, method, article, or terminal device that includes said element.

[0066] The power-on reset circuit, chip, motherboard, and electronic device provided by this utility model have been described in detail above. Specific examples have been used to illustrate the principle and implementation of this utility model. The description of the above embodiments is only for the purpose of helping to understand the structure and core idea of ​​this utility model. At the same time, for those skilled in the art, there will be changes in the specific implementation and application scope based on the idea of ​​this utility model. Therefore, the content of this specification should not be construed as a limitation of this utility model.

Claims

1. A power-on reset circuit, characterized by comprising: The power-on reset circuit includes a clamping circuit (10), a delay circuit (20), and a shaping circuit (30). The clamping circuit (10), the delay circuit (20), and the shaping circuit (30) are all electrically connected between the power supply VCC and the common ground GND. The output terminal OUT1 of the clamping circuit (10) is electrically connected to the input terminal IN1 of the delay circuit (20), and the output terminal OUT2 of the delay circuit (20) is electrically connected to the input terminal IN2 of the shaping circuit (30). The clamping voltage output by the clamping circuit (10) is used to control the delay circuit (20) to output a delay control signal. The delay circuit (20) controls the shaping circuit (30) to output a reset end signal through the delay control signal.

2. The power-on reset circuit of claim 1, wherein, The clamping circuit (10) includes a first transistor (101) and a second transistor (102), both of which are equivalent to diodes. The first transistor (101) is equivalent to the pin of the diode anode and the second transistor (102) is equivalent to the pin of the diode anode. The connection point of the two transistors forms the output terminal OUT1 of the clamping circuit (10). In the first transistor (101) and the second transistor (102), one of the transistors is equivalent to the cathode of a diode and its pin is electrically connected to the power supply VCC, and the other transistor is equivalent to the cathode of a diode and its pin is electrically connected to the common ground GND.

3. The power-on reset circuit of claim 2, wherein, The first transistor (101) is a PMOS, the second transistor (102) is an NMOS, and the clamping circuit (10) further includes a first resistor (103). The source of the first transistor (101) is electrically connected to the power supply VCC, and the first resistor (103) is connected in series between the source and the gate of the first transistor (101). The drain of the first transistor (101) is electrically connected to the drain of the second transistor (102), the drain of the second transistor (102) is electrically connected to the gate of the second transistor (102), and the source of the second transistor (102) is electrically connected to the common ground GND.

4. The power-on reset circuit of claim 1, wherein, The delay circuit (20) includes a third transistor (201) and a capacitor (202). The third transistor (201) includes a control electrode (201a), an input electrode (201b), and an output electrode (201c). The output terminal OUT1 of the clamping circuit (10) is electrically connected to the control electrode (201a), the input electrode (201b) is electrically connected to the power supply VCC, the output electrode (201c) is electrically connected to one end of the capacitor (202), and the node where the two are connected forms the output terminal OUT2 of the delay circuit (20), and the other end of the capacitor (202) is electrically connected to the common ground GND.

5. The power-on reset circuit of claim 4, wherein, The third transistor (201) is a PMOS, and the gate of the third transistor (201) is the control electrode (201a). The source of the third transistor (201) is the input electrode (201b), and the drain of the third transistor (201) is the output electrode (201c).

6. The power-on reset circuit according to claim 4 or 5, wherein The power-on reset circuit also includes a discharge circuit (40). The discharge circuit (40) is electrically connected between the power supply VCC and the input terminal IN2 of the shaping circuit (30), and the discharge circuit (40) is used to release the charge of the capacitor (202).

7. The power-on reset circuit of claim 6, wherein, The discharge circuit (40) includes a fourth transistor (401), which is a device equivalent to a diode.

8. The power-on reset circuit of claim 7, wherein, The fourth transistor (401) is a PMOS, and the discharge circuit (40) also includes a second resistor (402). The source of the fourth transistor (401) is electrically connected to the power supply VCC, the drain of the fourth transistor (401) is electrically connected to the input terminal IN2 of the shaping circuit (30), and the second resistor (402) is connected in series between the source of the fourth transistor (401) and the gate of the fourth transistor (401).

9. The power-on reset circuit of claim 1, wherein, The shaping circuit (30) includes a buffer consisting of multiple transistors.

10. A chip, characterized by The chip includes the power-on reset circuit as described in any one of claims 1 to 9.

11. A main board, characterized by, The motherboard includes the chip as described in claim 10.

12. An electronic device, comprising: The electronic device includes the motherboard as described in claim 11.

Images