一种交错重叠采样的长时间连续采样保持电路

Abstract

本实用新型涉及采样保持电路技术领域，公开了一种交错重叠采样的长时间连续采样保持电路，包括采样信号生成模块、第一采样开关和第二采样开关，采样信号生成模块接收原有采样信号和高频时钟信号，并输出第一采样信号和第二采样信号，第一采样信号输入到第一采样开关中，第二采样信号输入到第二采样开关中，第一采样开关和第二采样开关对输入的VIN信号进行交替重叠采样，并输出采样结果VOUT；该电路结构简单，成本低，可实现长时间连续采样，采样时间可达几十秒甚至几百秒，且采样过程中开关管的栅源电压差和导通电阻保持稳定，采样保持电路的采样精度高，可以满足当前多数逐次逼近型模拟数字转换器的精度需求。

Claims

1. An interleaved, long-time continuous sample-and-hold circuit, characterized by, The system includes a sampling signal generation module, a first sampling switch, and a second sampling switch. The sampling signal generation module receives the original sampling signal and a high-frequency clock signal, and outputs a first sampling signal and a second sampling signal. The first sampling signal is input to the first sampling switch, and the second sampling signal is input to the second sampling switch. The first sampling switch and the second sampling switch perform alternating overlapping sampling of the input VIN signal and output the sampling result VOUT.

2. The long continuous sample-and-hold circuit with interleaved overlap sampling of claim 1, wherein, The first sampling switch and the second sampling switch have the same structure.

3. The long-term continuous sample-and-hold circuit with interleaved overlapping sampling according to claim 2, characterized in that, The first sampling switch includes MOSFETs P1, N1, and N2. The gates of MOSFETs P1 and N1 are both connected to the CLK signal. The source of MOSFET P1 is connected to the VDD power supply, and the drain of MOSFET P1 is connected to the drain of MOSFET N1. The source of MOSFET N1 is connected to the drain of MOSFET N2, the source of MOSFET N2 is connected to the VSS power supply, and the gate of MOSFET N2 is connected to the CLKB signal.

4. The staggered interleaved long continuous sample-and-hold circuit of claim 3, wherein, The first sampling switch also includes MOSFETs P2, P3, and N3. The source of MOSFET P2 is connected to the VDD power supply, and a capacitor C is connected in series with the drain of MOSFET P2. B The MOSFET P2 is then connected to the drain of MOSFET N2, and MOSFET P2 is connected to capacitor C. B The source of MOSFET P3 is connected in series, the drain of MOSFET P3 is connected to the gate of MOSFET N3, the source of MOSFET N3 is connected to the drain of MOSFET N2, and the drain of MOSFET N3 is connected to the gate of MOSFET P3. At the same time, the circuit between the drain of MOSFET N3 and the gate of MOSFET P3 is also connected to the connection circuit between the drain of MOSFET P1 and the drain of MOSFET N1.

5. The long continuous sample-and-hold circuit with interleaved overlap sampling of claim 4, wherein, The first sampling switch also includes MOSFETs N4, N5, N6, and M. S The gate of MOSFET N4 is connected to the VDD power supply, the drain of MOSFET N4 is connected to the gate of MOSFET P2, the source of MOSFET N4 is connected to the drain of MOSFET N5, the gate of MOSFET N5 is connected to the CLKB signal, the source of MOSFET N5 is connected to the VSS signal, and the drain of MOSFET N4 is also connected to the gate of MOSFET N3, MOSFET N6, and MOSFET M. S The gate of MOSFET N6 and MOSFET M S After the source is connected, the VIN signal is output. The drain of MOSFET N6 is connected to the drain of MOSFET N2. MOSFET M S The drain outputs the VOUT signal.

6. The long continuous sample-and-hold circuit with interleaved overlap sampling of claim 1, wherein, The sampling signal generation module includes a quaternary counter, a frequency divider circuit, and a signal generation circuit. The output of the quaternary counter is connected to the frequency divider circuit, and the output of the frequency divider circuit is connected to the signal generation circuit.

7. The staggered interleaved long continuous sample-and-hold circuit of claim 6, wherein, The input of the quaternary counter is the counter timing signal CLK_CNT, and the output is Q<2:1>.

8. The staggered interleaved long continuous sample-and-hold circuit of claim 6, wherein, The quaternary counter includes two sets of D flip-flops, which are connected by an XOR gate.

9. The staggered interleaved long continuous sample-and-hold circuit of claim 6, wherein, The frequency divider circuit includes two NAND gates.

10. The staggered interleaved long continuous sample-and-hold circuit of claim 6, wherein, The signal generation circuit includes two AND gates.

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