一种阵列式屏蔽栅场效应晶体管与电子设备
By combining an array-type shielded gate structure with a dielectric filling layer in the shielded gate field-effect transistor, the problems of poor electric field modulation effect and uneven potential distribution in the shielded gate MOS structure are solved, resulting in lower switching losses and stronger avalanche capability, thus preventing device failure.
CN224521483UActive Publication Date: 2026-07-17捷捷微电(南通)科技有限公司
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Utility models(China)
- Current Assignee / Owner
- 捷捷微电(南通)科技有限公司
- Filing Date
- 2025-09-09
- Publication Date
- 2026-07-17
AI Technical Summary
Technical Problem
Existing shielded gate MOS structures suffer from poor electric field modulation, uneven potential distribution, high switching losses, and are prone to device failure.
Method used
An array-type shielded gate field-effect transistor is used. By setting an array of shielded gate structures around the device region and using a dielectric filling layer to isolate the gate and the shielded gate structure, a three-dimensional charge depletion effect is provided. Furthermore, the shielded gate structure and the gate are led out independently to avoid affecting the gate.
Benefits of technology
It achieves better electric field modulation effect, uniform potential distribution, reduced switching loss, improved avalanche capability, and prevents device failure.
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Abstract
本申请提供了一种阵列式屏蔽栅场效应晶体管与电子设备，涉及半导体技术领域。该阵列式屏蔽栅场效应晶体管包括器件区、栅极、介质填充层以及阵列排布的屏蔽栅结构，屏蔽栅结构设置于器件区的四周，栅极与屏蔽栅结构之间通过介质填充层隔离，栅极与器件区之间也通过介质填充层隔离；其中，屏蔽栅结构的表面与栅极的表面齐平。本申请提供的阵列式屏蔽栅场效应晶体管与电子设备具有电场调制效果更好、蔽栅结构电位分布更加均匀、整体器件的开关损耗更小、不易出现器件失效的情况的优点。
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