半导体装置

Abstract

本揭露提供一种半导体装置，其包括第一源极 / 漏极特征、第二源极 / 漏极特征、功能电路及电压放电电路。第一源极 / 漏极特征及第二源极 / 漏极特征设置于基板上方，其中第一源极 / 漏极特征及第二源极 / 漏极特征由绝缘特征分隔开。功能电路位于基板上方。电压放电电路在绝缘特征下方以及在第一源极 / 漏极特征与第二源极 / 漏极特征之间延伸，其中电压放电电路与功能电路并联。

Claims

1. A semiconductor device, characterized by comprising: Include: A first source / drain feature and a second source / drain feature are disposed above a substrate, wherein the first source / drain feature and the second source / drain feature are separated by an insulating feature; A functional circuit is located above the substrate; and A voltage discharge circuit extends below the insulation feature and between the first source / drain feature and the second source / drain feature, wherein the voltage discharge circuit is connected in parallel with the functional circuit.

2. A semiconductor device, characterized by comprising: Include: A first source / drain feature of a first dopant type is located in a substrate of a second dopant type opposite to the first dopant type; A second source / drain feature of the first dopant type is located in the substrate, the first source / drain feature and the second source / drain feature are spaced apart from each other in a first direction and define a first axis; A third source / drain feature and a fourth source / drain feature are located in the substrate. The third source / drain feature and the fourth source / drain feature are spaced apart from each other in the first direction and defined on a second direction perpendicular to the first direction and spaced apart from the first axis by a second axis. An insulating feature is located between the first source / drain feature and the second source / drain feature, and between the third source / drain feature and the fourth source / drain feature; A functional circuit is located above the substrate; and A voltage discharge circuit extends below the insulation feature and between the first source / drain feature and the second source / drain feature, wherein the voltage discharge circuit is connected in parallel with the functional circuit.

3. A semiconductor device, characterized by comprising: Include: A first source / drain feature of a first dopant type is located in a substrate of a second dopant type opposite to the first dopant type; A second source / drain feature of the first dopant type is located in the substrate; An insulating feature is located between the first source / drain feature and the second source / drain feature and extends toward the substrate to a selected depth; A first contact is electrically connected to the first source / drain feature and a first node; A second contact is electrically connected to the second source / drain feature and a second node; A functional circuit is located above the substrate; and A voltage discharge circuit extends below the insulation feature and between the first source / drain feature and the second source / drain feature, wherein the voltage discharge circuit is connected in parallel with the functional circuit.

4. The semiconductor device according to claim 3, wherein Further includes: First shallow trench isolation features; and A second shallow trench isolation feature; wherein: The first source / drain feature is located between the first shallow trench isolation feature and the insulation feature; and The second source / drain feature is located between the second shallow trench isolation feature and the insulation feature.

5. The semiconductor device according to claim 3 or 4, wherein Further includes: A first oxide over polysilicon defines the edge structure; and A second oxide over polysilicon defines the edge structure; wherein: The insulation feature is a continuous oxide-on-polysilicon defined edge structure; The first source / drain feature is located between the polysilicon-defined edge structure on the first oxide and the polysilicon-defined edge structure on the continuous oxide; and The second source / drain feature is located between the polysilicon defined edge structure on the second oxide and the polysilicon defined edge structure on the continuous oxide.

6. The semiconductor device according to claim 3 or 4, wherein Further includes: A first continuous oxide over polysilicon defines the edge structure; and A second continuous oxide over polysilicon defines the edge structure; wherein: The insulation feature is defined by a central continuous oxide-on-polysilicon edge structure; The first source / drain feature is located between the polysilicon defined edge structure on the first continuous oxide and the polysilicon defined edge structure on the central continuous oxide; and The second source / drain feature is located between the polysilicon defined edge structure on the second continuous oxide and the polysilicon defined edge structure on the central continuous oxide.

7. The semiconductor device according to claim 3 or 4, wherein Further includes: A first floating virtual gate; and A second floating virtual gate; wherein: The first source / drain feature is located between the first floating virtual gate and the insulating feature; and The second source / drain feature is located between the second floating dummy gate and the insulating feature.

8. The semiconductor device according to claim 3 or 4, wherein in: The first source / drain feature and the second source / drain feature are spaced apart from each other in a first direction and define a first axis; The semiconductor device further includes a third source / drain feature and a fourth source / drain feature, the third source / drain feature and the fourth source / drain feature being spaced apart from each other in the first direction and defined on a second direction perpendicular to the first direction and spaced apart from the first axis by a second axis. The first contact is electrically connected to the third source / drain feature; The second contact is electrically connected to the fourth source / drain feature; and The insulation feature is located between the third source / drain feature and the fourth source / drain feature.

9. The semiconductor device according to claim 3 or 4, wherein in: The first source / drain feature and the second source / drain feature are spaced apart from each other in a first direction and define a first axis; The semiconductor device further includes a third source / drain feature and a fourth source / drain feature, the third source / drain feature and the fourth source / drain feature being spaced apart from each other in the first direction and defined on a second direction perpendicular to the first direction and spaced apart from the first axis by a second axis. This insulation feature is a first insulation feature; and The semiconductor device further includes a second insulating feature located between the third source / drain feature and the fourth source / drain feature and extending toward the substrate to a second selected depth.

10. The semiconductor device according to claim 3 or 4, wherein in: The first source / drain feature and the second source / drain feature are spaced apart from each other in a first direction and define a first axis; The semiconductor device further includes a third source / drain feature and a fourth source / drain feature, the third source / drain feature and the fourth source / drain feature being spaced apart from each other in the first direction and defining a second axis parallel to the first axis; The insulation feature includes a first insulation feature section and a second insulation feature section; The first insulating feature segment has a first width in the first direction; The second insulating feature segment has a second width in the first direction; The first insulating feature segment is located between the first source / drain feature and the second source / drain feature; and The second insulating feature segment is located between the third source / drain feature and the fourth source / drain feature.

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