半导体装置结构
By employing multilayer structures and photolithography in semiconductor manufacturing to form nanostructured channel field-effect transistors, the complexity and cost issues of integrated circuit manufacturing have been resolved, improving device performance and production efficiency.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Utility models(China)
- Current Assignee / Owner
- TAIWAN SEMICONDUCTOR MANUFACTURING CO LTD
- Filing Date
- 2025-08-15
- Publication Date
- 2026-07-17
AI Technical Summary
In the current integrated circuit manufacturing process, as device size shrinks, the complexity of processing and manufacturing increases, requiring improvements in processes to increase production efficiency and reduce costs.
A multilayer semiconductor structure is adopted, including a combination of a first semiconductor layer, a gate dielectric layer, a work function layer, a binder layer, and a gate electrode layer. Nanostructured channel field-effect transistors are formed through photolithography and self-alignment processes, and the device performance is optimized by utilizing different materials and process steps.
It improves device performance, reduces manufacturing complexity and enhances production efficiency. It is applicable to various field-effect transistor structures such as HGAA, VGAA, and fork-type field-effect transistors, and increases the functional density of the device while reducing resistance.
Smart Images
Figure CN224521488U_ABST
Abstract
Claims
1. A semiconductor device structure, characterized by, Include: A first semiconductor layer is disposed in a first region above a substrate; A gate dielectric layer is disposed in the first region above the first semiconductor layer; One or more work function layers are disposed on the gate dielectric layer in the first region; An adhesive layer is disposed in the first region on the one or more work function layers; A gate electrode layer is disposed on the adhesive layer in the first region; as well as A second semiconductor layer is disposed in a second region above the substrate, wherein the gate dielectric layer is disposed above the second semiconductor layer in the second region, the adhesive layer is disposed on the gate dielectric layer in the second region, and the gate electrode layer is disposed on the adhesive layer in the second region.
2. The semiconductor device structure of claim 1, wherein, It also includes an interface layer disposed in the first region between the first semiconductor layer and the gate dielectric layer, and in the second region between the second semiconductor layer and the gate dielectric layer.
3. The semiconductor device structure of claim 1, wherein, The first region includes a first PMOS region and a first NMOS region, and the second region includes a second PMOS region and a second NMOS region.
4. The semiconductor device structure of claim 3, wherein The one or more work function layers include a p-type work function layer disposed in the first PMOS region and an n-type work function layer disposed in the first NMOS region.
5. The semiconductor device structure of claim 4, wherein, The adhesive layer is in contact with the p-type work function layer in the first PMOS region and with the n-type work function layer in the first NMOS region.
6. The semiconductor device structure as described in claim 3, characterized in that, The one or more work function layers include a first work function layer disposed in the first PMOS region and a second work function layer disposed on the first work function layer in the first PMOS region, and the first work function layer is disposed in the first NMOS region.
7. A semiconductor device structure, characterized by, Include: A first semiconductor layer is disposed in a first region above a substrate; A gate dielectric layer is disposed above the first semiconductor layer in the first region; One or more work function layers are disposed on the gate dielectric layer in the first region; A gate electrode layer is disposed on one or more work function layers in the first region; as well as A second semiconductor layer is disposed in a second region above the substrate, wherein the gate dielectric layer is disposed above the second semiconductor layer in the second region, and the gate electrode layer is disposed on the gate dielectric layer in the second region.
8. The semiconductor device structure of claim 7, wherein, The one or more work function layers include a first work function layer and a second work function layer disposed on the first work function layer.
9. A semiconductor device structure, characterized by, Include: A first semiconductor layer is disposed in a first region above a substrate; A gate dielectric layer is disposed above the first semiconductor layer in the first region; One or more work function layers are disposed on the gate dielectric layer in the first region; A gate electrode layer is disposed on one or more work function layers in the first region; A second semiconductor layer is disposed in a second region above the substrate, wherein the gate dielectric layer is disposed above the second semiconductor layer in the second region, and the gate electrode layer is disposed on the gate dielectric layer in the second region; A first gate structure is disposed in the first region; and A second gate structure is disposed in the second region.
10. The semiconductor device structure of claim 9, wherein, The first gate structure includes the gate dielectric layer, the one or more work function layers, and the gate electrode layer, and the second gate structure includes the gate dielectric layer and the gate electrode layer. The first gate structure includes the gate dielectric layer, the one or more work function layers, and the gate electrode layer, and the second gate structure includes the gate dielectric layer and the gate electrode layer.